arch/ppc-chrp/efika/include/asm/mpc5200b.h

   1 #ifndef ASM_MPC5200B_H
   2 #define ASM_MPC5200B_H
   3
   4 #include <inttypes.h>
   5
   6 #define __BV32(num)     ((0x80000000 >> (num)))
   7 #define __BV16(num)     ((0x8000 >> (num)))
   8 #define __BV08(num) ((0x80 >> (num)))
   9
  10 typedef struct regs {
  11     uint32_t    gpr[32];
  12     uint32_t    srr0;
  13     uint32_t    srr1;
  14     uint32_t    ctr;
  15     uint32_t    lr;
  16     uint32_t    xer;
  17     uint32_t    ccr;
  18     uint32_t    dar;
  19     uint32_t    dsisr;
  20 } regs_t;
  21
  22 typedef struct fpuregs {
  23     double      fpr[32];
  24     uint32_t    fpscr;
  25 } fpuregs_t;
  26
  27 typedef struct context {
  28     regs_t      cpu;
  29     fpuregs_t   fpu;
  30 } context_t;
  31
  32 #define SIZEOF_ALL_REGISTERS (sizeof(context_t))
  33
  34 static inline uint32_t rdmsr() {
  35     uint32_t msr; asm volatile("mfmsr %0":"=r"(msr)); return msr;
  36 }
  37
  38 static inline void wrmsr(uint32_t msr) {
  39     asm volatile("mtmsr %0"::"r"(msr));
  40 }
  41
  42 /* Machine State Register */
  43 #define MSR_POW 0x00040000
  44 #define MSR_TGPR 0x00020000
  45 #define MSR_ILE 0x00010000
  46 #define MSR_EE  0x00008000
  47 #define MSR_PR  0x00004000
  48 #define MSR_FP  0x00002000
  49 #define MSR_ME  0x00001000
  50 #define MSR_FE0 0x00000800
  51 #define MSR_SE  0x00000400
  52 #define MSR_BE  0x00000200
  53 #define MSR_FE1 0x00000100
  54 #define MSR_IP  0x00000040
  55 #define MSR_IS  0x00000020
  56 #define MSR_DS  0x00000010
  57 #define MSR_RI  0x00000002
  58 #define MSR_LE  0x00000001
  59
  60 #define rdspr(reg) \
  61     ({ unsigned long val; asm volatile("mfspr %0,%1":"=r"(val):"i"(reg)); val; })
  62
  63 #define wrspr(reg, val) \
  64     do { asm volatile("mtspr %0,%1"::"i"(reg),"r"(val)); } while(0)
  65
  66 /* SPR registers */
  67 #define XER     0x001   /* Integer Exception Register */
  68 #define LR      0x008   /* Link Register */
  69 #define CTR     0x009   /* Count Register */
  70 #define DEC     0x016   /* Decrementer */
  71 #define SDR1    0x019   /* MMU base address */
  72 #define SRR0    0x01A   /* Save/Restore Register 0 */
  73 #define SRR1    0x01B   /* Save/Restore Register 1 */
  74 #define TBLU    0x10C   /* Time Base Lower */
  75 #define TBUU    0x10D   /* Time Base Upper */
  76 #define SPRG0   0x110   /* Special Purpose Register General 0 */
  77 #define SPRG1   0x111   /* Special Purpose Register General 1 */
  78 #define SPRG2   0x112   /* Special Purpose Register General 2 */
  79 #define SPRG3   0x113   /* Special Purpose Register General 3 */
  80 #define SPRG4   0x114   /* Special Purpose Register General 4 */
  81 #define SPRG5   0x115   /* Special Purpose Register General 5 */
  82 #define SPRG6   0x116   /* Special Purpose Register General 6 */
  83 #define SPRG7   0x117   /* Special Purpose Register General 7 */
  84
  85 #define DMISS   0x3d0
  86 #define DCMP    0x3d1
  87 #define HASH1   0xd32
  88 #define HASH2   0x3d3
  89 #define IMISS   0x3d4
  90 #define ICMP    0x3d5
  91 #define RPA             0x3d6
  92
  93 static inline struct KernelBase *getKernelBase()
  94 {
  95     return (struct KernelBase *)rdspr(SPRG4);
  96 }
  97
  98 static inline struct ExecBase *getSysBase()
  99 {
 100     return (struct ExecBase *)rdspr(SPRG5);
 101 }
 102
 103 /* Interrupt controller */
 104
 105 typedef struct {
 106         uint32_t        ictl_pim;               /* Peripheral interrupt mask register */
 107         uint32_t        ictl_ppri[3];   /* Peripheral priority and HI/LO select register */
 108         uint32_t        ictl_ee;                /* External enable and external types register */
 109         uint32_t        ictl_cpmim;             /* Critical Priority and Main Interrupt Mask Register */
 110         uint32_t        ictl_mip[2];    /* Main Interrupt Priority and INT/SMI Select Register */
 111         uint32_t        __pad1;
 112         uint32_t        ictl_pmce;              /* PerStat, MainStat, CritStat Encoded Register */
 113         uint32_t        ictl_cis;               /* Critical Interrupt Status All Register */
 114         uint32_t        ictl_mis;               /* Main Interrupt Status All Register */
 115         uint32_t        ictl_pis;               /* Peripheral Interrupt Status All Register */
 116         uint32_t        __pad2;
 117         uint32_t        ictl_bes;               /* Bus Error Status Register */
 118         uint32_t        __pad3;
 119         uint32_t        ictl_mie;               /* Main Interrupt Emulation All Register */
 120         uint32_t        ictl_pie;               /* Peripheral Interrupt Emulation All Register */
 121         uint32_t        ictl_iie;               /* IRQ Interrupt Emulation All Register */
 122 } mpc5200b_ictl_t;
 123
 124 #define MPC5200B_IRQ0           0       /* IRQ 0 */
 125 #define MPC5200B_ST0            1       /* Slice Timer 0 */
 126 #define MPC5200B_HI_INT         2       /* HI_int */
 127 #define MPC5200B_WAKEUP         3       /* WakeUp from deep-sleep */
 128
 129 #define MPC5200B_ST1            4       /* Slice Timer 1 */
 130 #define MPC5200B_IRQ1           5       /* IRQ 1 */
 131 #define MPC5200B_IRQ2           6       /* IRQ 2 */
 132 #define MPC5200B_IRQ3           7       /* IRQ 3 */
 133 #define MPC5200B_LO_INT         8       /* LO_int */
 134 #define MPC5200B_RTC_PINT       9       /* RTC Periodic Int */
 135 #define MPC5200B_RTC_SINT       10      /* RTC Stopwatch and Alarm Int */
 136 #define MPC5200B_GPIO_STD       11      /* GPIO interrupts */
 137 #define MPC5200B_GPIO_WKUP      12      /* GPIO wakeup */
 138 #define MPC5200B_TMR0           13      /* Timer 0 */
 139 #define MPC5200B_TMR1           14      /* Timer 1 */
 140 #define MPC5200B_TMR2           15      /* Timer 2 */
 141 #define MPC5200B_TMR3           16      /* Timer 3 */
 142 #define MPC5200B_TMR4           17      /* Timer 4 */
 143 #define MPC5200B_TMR5           18      /* Timer 5 */
 144 #define MPC5200B_TMR6           19      /* Timer 6 */
 145 #define MPC5200B_TMR7           20      /* Timer 7 */
 146
 147 #define MPC5200B_BESTCOMM       21
 148 #define MPC5200B_PSC1           22
 149 #define MPC5200B_PSC2           23
 150 #define MPC5200B_PSC3           24
 151 #define MPC5200B_PSC6           25
 152 #define MPC5200B_ETHER          26
 153 #define MPC5200B_USB            27
 154 #define MPC5200B_ATA            28
 155 #define MPC5200B_PCICM          29
 156 #define MPC5200B_PCISC_RX       30
 157 #define MPC5200B_PCISC_TX       31
 158 #define MPC5200B_PSC4           32
 159 #define MPC5200B_PSC5           33
 160 #define MPC5200B_SPI_MODF       34
 161 #define MPC5200B_SPI_SPIF       35
 162 #define MPC5200B_I2C1           36
 163 #define MPC5200B_I2C2           37
 164 #define MPC5200B_CAN1           38
 165 #define MPC5200B_CAN2           39
 166 #define MPC5200B_XLB            42
 167 #define MPC5200B_BDLC           43
 168 #define MPC5200B_BESTCOMMLP     44
 169
 170 #define PER_BESTCOMM            0
 171 #define PER_PSC1                        1
 172 #define PER_PSC2                        2
 173 #define PER_PSC3                        3
 174 #define PER_PSC6                        4
 175 #define PER_ETHER                       5
 176 #define PER_USB                         6
 177 #define PER_ATA                         7
 178 #define PER_PCICM                       8
 179 #define PER_PCISC_RX            9
 180 #define PER_PCISC_TX            10
 181 #define PER_PSC4                        11
 182 #define PER_PSC5                        12
 183 #define PER_SPI_MODF            13
 184 #define PER_SPI_SPIF            14
 185 #define PER_I2C1                        15
 186 #define PER_I2C2                        16
 187 #define PER_CAN1                        17
 188 #define PER_CAN2                        18
 189 #define PER_XLB                         21
 190 #define PER_BDLC                        22
 191 #define PER_BESTCOMMLP          23
 192
 193 #define ICTL_PIM_BESTCOMM       __BV32(PER_BESTCOMM)
 194 #define ICTL_PIM_PSC1           __BV32(PER_PSC1)
 195 #define ICTL_PIM_PSC2           __BV32(PER_PSC2)
 196 #define ICTL_PIM_PSC3           __BV32(PER_PSC3)
 197 #define ICTL_PIM_PSC6           __BV32(PER_PSC6)
 198 #define ICTL_PIM_ETHER          __BV32(PER_ETHER)
 199 #define ICTL_PIM_USB            __BV32(PER_USB)
 200 #define ICTL_PIM_ATA            __BV32(PER_ATA)
 201 #define ICTL_PIM_PCICM          __BV32(PER_PCICM)
 202 #define ICTL_PIM_PCISC_RX       __BV32(PER_PCISC_RX)
 203 #define ICTL_PIM_PCISC_TX       __BV32(PER_PCISC_TX)
 204 #define ICTL_PIM_PSC4           __BV32(PER_PSC4)
 205 #define ICTL_PIM_PSC5           __BV32(PER_PSC5)
 206 #define ICTL_PIM_SPI_MODF       __BV32(PER_SPI_MODF)
 207 #define ICTL_PIM_SPI_SPIF       __BV32(PER_SPI_SPIF)
 208 #define ICTL_PIM_I2C1           __BV32(PER_I2C1)
 209 #define ICTL_PIM_I2C2           __BV32(PER_I2C2)
 210 #define ICTL_PIM_CAN1           __BV32(PER_CAN1)
 211 #define ICTL_PIM_CAN2           __BV32(PER_CAN2)
 212 #define ICTL_PIM_XLB            __BV32(PER_XLB)
 213 #define ICTL_PIM_BDLC           __BV32(PER_BDLC)
 214 #define ICTL_PIM_BESTCOMMLP     __BV32(PER_BESTCOMMLP)
 215
 216 #define ICTL_EE_MEE                     __BV32(19)
 217 #define ICTL_EE_CEB                     __BV32(31)
 218
 219 /* Slice timer */
 220 typedef struct {
 221         volatile uint32_t       slt_tc; /* Terminal count register */
 222         volatile uint32_t       slt_cf; /* Control field register */
 223         volatile uint32_t       slt_cv; /* Count value register. Read only! */
 224         volatile uint32_t       slt_ts; /* Timer Status register */
 225 } slt_t;
 226
 227 #define SLT_CF_RUNWAIT          0x04000000      /* Run/Wait */
 228 #define SLT_CF_INTRENA          0x02000000      /* Interrupt enable */
 229 #define SLT_CF_ENABLE           0x01000000      /* Enable/Disable timer */
 230
 231 #define SLT_TS_ST                       0x01000000      /* Terminal count reached. Write 1 to clear */
 232
 233
 234 /* Ata device */
 235 typedef struct {
 236         volatile uint32_t       ata_config;
 237         volatile uint32_t       ata_status;
 238
 239         volatile uint32_t       ata_pio1;
 240         volatile uint32_t       ata_pio2;
 241         volatile uint32_t       ata_dma1;
 242         volatile uint32_t       ata_dma2;
 243         volatile uint32_t       ata_udma1;
 244         volatile uint32_t       ata_udma2;
 245         volatile uint32_t       ata_udma3;
 246         volatile uint32_t       ata_udma4;
 247         volatile uint32_t       ata_udma5;
 248         volatile uint32_t       ata_invalid;
 249 } ata_5k2_t;
 250
 251
 252 /* bestcomm */
 253
 254 typedef struct {
 255         uint32_t        bc_taskBar;
 256         uint32_t        bc_currentPointer;
 257         uint32_t        bc_endPointer;
 258         uint32_t        bc_variablePointer;
 259         uint32_t        bc_interruptVector;
 260         uint32_t        bc_interruptPending;
 261         uint32_t        bc_interruptMask;
 262         uint16_t        bc_tcr[16];
 263         uint8_t         bc_ipr[32];
 264         uint32_t        bc_requestMuxControl;
 265         uint32_t        bc_taskSize[2];
 266 } bestcomm_t;
 267
 268 /* Bestcomm's task description table */
 269 typedef struct {
 270         uint32_t        start;
 271         uint32_t        stop;
 272         uint32_t        var;
 273         uint32_t        fdt;
 274         uint32_t        exec_status;
 275         uint32_t        mvtp;
 276         uint32_t        context;
 277         uint32_t        litbase;
 278 } bestcomm_tdt_t;
 279
 280 #endif /* ASM_MPC5200B_H */