arch/common/hidd.pci/pci.h

   1 #ifndef _PCI_H
   2 #define _PCI_H
   3
   4 /*
   5     Copyright © 2004-2006, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8
   9 #include <exec/types.h>
  10 #include <exec/libraries.h>
  11 #include <exec/execbase.h>
  12 #include <exec/nodes.h>
  13 #include <exec/lists.h>
  14 #include <exec/semaphores.h>
  15 #include <dos/bptr.h>
  16
  17 #include <aros/libcall.h>
  18 #include <aros/asmcall.h>
  19
  20 #include <oop/oop.h>
  21
  22 #include <aros/arossupportbase.h>
  23 #include <exec/execbase.h>
  24
  25 #include LC_LIBDEFS_FILE
  26
  27 /* Private data and structures unavailable outside the pci base classes */
  28
  29 struct DriverNode {
  30     struct Node         node;
  31     OOP_Class           *driverClass;   /* Driver class */
  32     OOP_Object          *driverObject;  /* Driver object */
  33     ULONG               highBus;
  34     struct List         devices;        /* List of defices behind this node */
  35 };
  36
  37 struct DrvInstData {
  38     BOOL DirectBus;
  39 };
  40
  41 struct PciDevice {
  42     struct MinNode      node;
  43     OOP_Object          *device;
  44 };
  45
  46 typedef struct DeviceData {
  47     OOP_Object          *driver;
  48     UBYTE               bus,dev,sub;
  49     UBYTE               isBridge;
  50     UBYTE               subbus;
  51     UWORD               VendorID;
  52     UWORD               ProductID;
  53     UBYTE               RevisionID;
  54     UBYTE               Interface;
  55     UBYTE               SubClass;
  56     UBYTE               Class;
  57     UWORD               SubsysVID;
  58     UWORD               SubsystemID;
  59     UBYTE               INTLine;
  60     UBYTE               IRQLine;
  61     UBYTE               HeaderType;
  62     struct {
  63         IPTR            addr;
  64         IPTR            size;
  65     } BaseReg[6];
  66     ULONG               RomBase;
  67     ULONG               RomSize;
  68
  69     STRPTR              strClass;
  70     STRPTR              strSubClass;
  71     STRPTR              strInterface;
  72 } tDeviceData;
  73
  74 struct pci_staticdata {
  75     struct SignalSemaphore driver_lock;
  76     struct List         drivers;
  77
  78     APTR                MemPool;
  79
  80     OOP_AttrBase        hiddAB;
  81     OOP_AttrBase        hiddPCIAB;
  82     OOP_AttrBase        hiddPCIDriverAB;
  83     OOP_AttrBase        hiddPCIBusAB;
  84     OOP_AttrBase        hiddPCIDeviceAB;
  85
  86     OOP_Class           *pciClass;
  87     OOP_Class           *pciDeviceClass;
  88     OOP_Class           *pciDriverClass;
  89
  90     ULONG               users;
  91
  92     /* Most commonly used methods have already the mID's stored here */
  93     OOP_MethodID        mid_RB;
  94     OOP_MethodID        mid_RW;
  95     OOP_MethodID        mid_RL;
  96     OOP_MethodID        mid_WB;
  97     OOP_MethodID        mid_WW;
  98     OOP_MethodID        mid_WL;
  99 };
 100
 101 struct pcibase {
 102     struct Library              LibNode;
 103     struct ExecBase             *sysBase;
 104     BPTR                        segList;
 105     APTR                        MemPool;
 106     struct pci_staticdata       psd;
 107 };
 108
 109 OOP_Class *init_pcideviceclass(struct pci_staticdata *);
 110 void free_pcideviceclass(struct pci_staticdata *, OOP_Class *cl);
 111
 112 #define BASE(lib) ((struct pcibase*)(lib))
 113
 114 #define PSD(cl) (&BASE(cl->UserData)->psd)
 115
 116 /* PCI Configspace offsets */
 117 #define PCICS_VENDOR            0x00
 118 #define PCICS_PRODUCT           0x02
 119 #define PCICS_COMMAND           0x04
 120 #define PCICS_STATUS            0x06
 121 #define PCICS_REVISION          0x08
 122 #define PCICS_PROGIF            0x09
 123 #define PCICS_SUBCLASS          0x0a
 124 #define PCICS_CLASS             0x0b
 125 #define PCICS_CACHELS           0x0c
 126 #define PCICS_LATENCY           0x0d
 127 #define PCICS_HEADERTYPE        0x0e
 128 #define PCICS_BIST              0x0f
 129 #define PCICS_BAR0              0x10
 130 #define PCICS_BAR1              0x14
 131 #define PCICS_BAR2              0x18
 132 #define PCICS_BAR3              0x1c
 133 #define PCICS_BAR4              0x20
 134 #define PCICS_BAR5              0x24
 135 #define PCICS_CARDBUS_CIS       0x28
 136 #define PCICS_SUBVENDOR         0x2c
 137 #define PCICS_SUBSYSTEM         0x2e
 138 #define PCICS_EXPROM_BASE       0x30
 139 #define PCICS_CAP_PTR           0x34
 140 #define PCICS_INT_LINE          0x3c
 141 #define PCICS_INT_PIN           0x3d
 142 #define PCICS_MIN_GNT           0x3e
 143 #define PCICS_MAX_LAT           0x3f
 144
 145 /* PCI Headertypes */
 146 #define PCIHT_MASK              0x7f
 147 #define PCIHT_MULTIFUNC         0x80
 148
 149 #define PCIHT_NORMAL            0x00
 150 #define PCIHT_BRIDGE            0x01
 151 #define PCIHT_CARDBUS           0x02
 152
 153 /* PCI Command register bits */
 154 #define PCICMB_IODECODE         0
 155 #define PCICMB_MEMDECODE        1
 156 #define PCICMB_BUSMASTER        2
 157 #define PCICMB_SPECIAL          3
 158 #define PCICMB_INVALIDATE       4
 159 #define PCICMB_VGASNOOP         5
 160 #define PCICMB_PARITY           6
 161 #define PCICMB_STEPPING         7
 162 #define PCICMB_SERR             8
 163 #define PCICMB_FASTB2B          9
 164
 165 #define PCICMF_IODECODE         (1 << PCICMB_IODECODE)
 166 #define PCICMF_MEMDECODE        (1 << PCICMB_MEMDECODE)
 167 #define PCICMF_BUSMASTER        (1 << PCICMB_BUSMASTER)
 168 #define PCICMF_SPECIAL          (1 << PCICMB_SPECIAL)
 169 #define PCICMF_INVALIDATE       (1 << PCICMB_INVALIDATE)
 170 #define PCICMF_VGASNOOP         (1 << PCICMB_VGASNOOP)
 171 #define PCICMF_PARITY           (1 << PCICMB_PARITY)
 172 #define PCICMF_STEPPING         (1 << PCICMB_STEPPING)
 173 #define PCICMF_SERR             (1 << PCICMB_SERR)
 174 #define PCICMF_FASTB2B          (1 << PCICMB_FASTB2B)
 175
 176 /* PCI Status register bits */
 177 #define PCISTB_CAPABILITES      4
 178 #define PCISTB_66MHZ            5
 179 #define PCISTB_FASTB2B          7
 180 #define PCISTB_PARITY           8
 181 #define PCISTB_SIG_TGT_ABORT    11
 182 #define PCISTB_REC_TGT_ABORT    12
 183 #define PCISTB_REC_MAS_ABORT    13
 184 #define PCISTB_SIG_SYSERR       14
 185 #define PCISTB_PARITYERR        15
 186
 187 #define PCISTF_CAPABILITES      (1 << PCISTB_CAPABILITES)
 188 #define PCISTF_66MHZ            (1 << PCISTB_66MHZ)
 189 #define PCISTF_FASTB2B          (1 << PCISTB_FASTB2B)
 190 #define PCISTF_PARITY           (1 << PCISTB_PARITY)
 191 #define PCISTF_SIG_TGT_ABORT    (1 << PCISTB_SIG_TGT_ABORT)
 192 #define PCISTF_REC_TGT_ABORT    (1 << PCISTB_REC_TGT_ABORT)
 193 #define PCISTF_REC_MAS_ABORT    (1 << PCISTB_REC_MAS_ABORT)
 194 #define PCISTF_SIG_SYSERR       (1 << PCISTB_SIG_SYSERR)
 195 #define PCISTF_PARITYERR        (1 << PCISTB_PARITYERR)
 196
 197 #define PCIST_DEVSEL_MASK       0x600
 198 #define PCIST_DEVSEL_FAST       0x000
 199 #define PCIST_DEVSEL_MEDIUM     0x200
 200 #define PCIST_DEVSEL_SLOW       0x400
 201
 202 /* PCI BIST register */
 203 #define PCIBSB_START            6
 204 #define PCIBSB_CAPABLE          7
 205
 206 #define PCIBSF_START            (1 << PCIBSB_START)
 207 #define PCIBSF_CAPABLE          (1 << PCIBSB_CAPABLE)
 208
 209 #define PCIBS_CODEMASK          0x0f
 210
 211 /* PCI BaseAddressRegister defines */
 212 #define PCIBAR_MASK_TYPE        0x01
 213 #define PCIBAR_TYPE_MMAP        0x00
 214 #define PCIBAR_TYPE_IO          0x01
 215 #define PCIBAR_MASK_MEM         0xfffffff0
 216 #define PCIBAR_MASK_IO          0xfffffffc
 217
 218 #define PCIBAR_MEMTYPE_MASK     0x06
 219 #define PCIBAR_MEMTYPE_32BIT    0x00
 220 #define PCIBAR_MEMTYPE_64BIT    0x04
 221
 222 #define PCIBARB_PREFETCHABLE    3
 223 #define PCIBARF_PREFETCHABLE    (1 << PCIBARB_PREFETCHABLE)
 224
 225 /*
 226  * PCI-to-PCI bridge header defines
 227  * First 16 bytes are the same as normal PCI dev
 228  */
 229 #define PCIBR_BAR0              0x10
 230 #define PCIBR_BAR1              0x14
 231 #define PCIBR_PRIBUS            0x18
 232 #define PCIBR_SECBUS            0x19
 233 #define PCIBR_SUBBUS            0x1a
 234 #define PCIBR_SECLATENCY        0x1b
 235 #define PCIBR_IOBASE            0x1c
 236 #define PCIBR_IOLIMIT           0x1d
 237 #define PCIBR_SECSTATUS         0x1e
 238 #define PCIBR_MEMBASE           0x20
 239 #define PCIBR_MEMLIMIT          0x22
 240 #define PCIBR_PREFETCHBASE      0x24
 241 #define PCIBR_PREFETCHLIMIT     0x26
 242 #define PCIBR_PREBASEUPPER      0x28
 243 #define PCIBR_PRELIMITUPPER     0x2c
 244 #define PCIBR_IOBASEUPPER       0x30
 245 #define PCIBR_IOLIMITUPPER      0x32
 246 #define PCIBR_CAPPTR            0x34
 247 #define PCIBR_EXPROMBASE        0x38
 248 #define PCIBR_INT_LINE          0x3c
 249 #define PCIBR_INT_PIN           0x3d
 250 #define PCIBR_CONTROL           0x3e
 251
 252 #define PCICTRLB_ISAENABLE      2
 253 #define PCICTRLB_VGAENABLE      3
 254
 255 #define PCICTRLF_ISAENABLE      (1 << PCICTRLB_ISAENABLE)
 256 #define PCICTRLF_VGAENABLE      (1 << PCICTRLF_ISAENABLE)
 257
 258 #endif /* _PCI_H */
 259