arch/arm/mach-msm/timer.c

   1 /* linux/arch/arm/mach-msm/timer.c
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/time.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/clk.h>
  21 #include <linux/clockchips.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24
  25 #include <asm/mach/time.h>
  26 #include <mach/msm_iomap.h>
  27
  28 #ifndef MSM_DGT_BASE
  29 #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
  30 #endif
  31
  32 #define TIMER_MATCH_VAL         0x0000
  33 #define TIMER_COUNT_VAL         0x0004
  34 #define TIMER_ENABLE            0x0008
  35 #define TIMER_ENABLE_CLR_ON_MATCH_EN    2
  36 #define TIMER_ENABLE_EN                 1
  37 #define TIMER_CLEAR             0x000C
  38 #define DGT_CLK_CTL             0x0034
  39 enum {
  40         DGT_CLK_CTL_DIV_1 = 0,
  41         DGT_CLK_CTL_DIV_2 = 1,
  42         DGT_CLK_CTL_DIV_3 = 2,
  43         DGT_CLK_CTL_DIV_4 = 3,
  44 };
  45 #define CSR_PROTECTION          0x0020
  46 #define CSR_PROTECTION_EN               1
  47
  48 #define GPT_HZ 32768
  49
  50 enum timer_location {
  51         LOCAL_TIMER = 0,
  52         GLOBAL_TIMER = 1,
  53 };
  54
  55 #ifdef MSM_TMR0_BASE
  56 #define MSM_TMR_GLOBAL          (MSM_TMR0_BASE - MSM_TMR_BASE)
  57 #else
  58 #define MSM_TMR_GLOBAL          0
  59 #endif
  60
  61 #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
  62
  63 #if defined(CONFIG_ARCH_QSD8X50)
  64 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
  65 #define MSM_DGT_SHIFT (0)
  66 #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
  67 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
  68 #define MSM_DGT_SHIFT (0)
  69 #else
  70 #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
  71 #define MSM_DGT_SHIFT (5)
  72 #endif
  73
  74 struct msm_clock {
  75         struct clock_event_device   clockevent;
  76         struct clocksource          clocksource;
  77         struct irqaction            irq;
  78         void __iomem                *regbase;
  79         uint32_t                    freq;
  80         uint32_t                    shift;
  81         void __iomem                *global_counter;
  82         void __iomem                *local_counter;
  83 };
  84
  85 enum {
  86         MSM_CLOCK_GPT,
  87         MSM_CLOCK_DGT,
  88         NR_TIMERS,
  89 };
  90
  91
  92 static struct msm_clock msm_clocks[];
  93 static struct clock_event_device *local_clock_event;
  94
  95 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  96 {
  97         struct clock_event_device *evt = dev_id;
  98         if (smp_processor_id() != 0)
  99                 evt = local_clock_event;
 100         if (evt->event_handler == NULL)
 101                 return IRQ_HANDLED;
 102         evt->event_handler(evt);
 103         return IRQ_HANDLED;
 104 }
 105
 106 static cycle_t msm_read_timer_count(struct clocksource *cs)
 107 {
 108         struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
 109
 110         return readl(clk->global_counter);
 111 }
 112
 113 static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
 114 {
 115 #ifdef CONFIG_SMP
 116         int i;
 117         for (i = 0; i < NR_TIMERS; i++)
 118                 if (evt == &(msm_clocks[i].clockevent))
 119                         return &msm_clocks[i];
 120         return &msm_clocks[MSM_GLOBAL_TIMER];
 121 #else
 122         return container_of(evt, struct msm_clock, clockevent);
 123 #endif
 124 }
 125
 126 static int msm_timer_set_next_event(unsigned long cycles,
 127                                     struct clock_event_device *evt)
 128 {
 129         struct msm_clock *clock = clockevent_to_clock(evt);
 130         uint32_t now = readl(clock->local_counter);
 131         uint32_t alarm = now + (cycles << clock->shift);
 132
 133         writel(alarm, clock->regbase + TIMER_MATCH_VAL);
 134         return 0;
 135 }
 136
 137 static void msm_timer_set_mode(enum clock_event_mode mode,
 138                               struct clock_event_device *evt)
 139 {
 140         struct msm_clock *clock = clockevent_to_clock(evt);
 141
 142         switch (mode) {
 143         case CLOCK_EVT_MODE_RESUME:
 144         case CLOCK_EVT_MODE_PERIODIC:
 145                 break;
 146         case CLOCK_EVT_MODE_ONESHOT:
 147                 writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
 148                 break;
 149         case CLOCK_EVT_MODE_UNUSED:
 150         case CLOCK_EVT_MODE_SHUTDOWN:
 151                 writel(0, clock->regbase + TIMER_ENABLE);
 152                 break;
 153         }
 154 }
 155
 156 static struct msm_clock msm_clocks[] = {
 157         [MSM_CLOCK_GPT] = {
 158                 .clockevent = {
 159                         .name           = "gp_timer",
 160                         .features       = CLOCK_EVT_FEAT_ONESHOT,
 161                         .shift          = 32,
 162                         .rating         = 200,
 163                         .set_next_event = msm_timer_set_next_event,
 164                         .set_mode       = msm_timer_set_mode,
 165                 },
 166                 .clocksource = {
 167                         .name           = "gp_timer",
 168                         .rating         = 200,
 169                         .read           = msm_read_timer_count,
 170                         .mask           = CLOCKSOURCE_MASK(32),
 171                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 172                 },
 173                 .irq = {
 174                         .name    = "gp_timer",
 175                         .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
 176                         .handler = msm_timer_interrupt,
 177                         .dev_id  = &msm_clocks[0].clockevent,
 178                         .irq     = INT_GP_TIMER_EXP
 179                 },
 180                 .regbase = MSM_GPT_BASE,
 181                 .freq = GPT_HZ,
 182                 .local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL,
 183                 .global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL +
 184                         MSM_TMR_GLOBAL,
 185         },
 186         [MSM_CLOCK_DGT] = {
 187                 .clockevent = {
 188                         .name           = "dg_timer",
 189                         .features       = CLOCK_EVT_FEAT_ONESHOT,
 190                         .shift          = 32 + MSM_DGT_SHIFT,
 191                         .rating         = 300,
 192                         .set_next_event = msm_timer_set_next_event,
 193                         .set_mode       = msm_timer_set_mode,
 194                 },
 195                 .clocksource = {
 196                         .name           = "dg_timer",
 197                         .rating         = 300,
 198                         .read           = msm_read_timer_count,
 199                         .mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
 200                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 201                 },
 202                 .irq = {
 203                         .name    = "dg_timer",
 204                         .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
 205                         .handler = msm_timer_interrupt,
 206                         .dev_id  = &msm_clocks[1].clockevent,
 207                         .irq     = INT_DEBUG_TIMER_EXP
 208                 },
 209                 .regbase = MSM_DGT_BASE,
 210                 .freq = DGT_HZ >> MSM_DGT_SHIFT,
 211                 .shift = MSM_DGT_SHIFT,
 212                 .local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL,
 213                 .global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL +
 214                         MSM_TMR_GLOBAL,
 215         }
 216 };
 217
 218 static void __init msm_timer_init(void)
 219 {
 220         int i;
 221         int res;
 222
 223 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
 224         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 225 #endif
 226
 227         for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
 228                 struct msm_clock *clock = &msm_clocks[i];
 229                 struct clock_event_device *ce = &clock->clockevent;
 230                 struct clocksource *cs = &clock->clocksource;
 231                 writel(0, clock->regbase + TIMER_ENABLE);
 232                 writel(0, clock->regbase + TIMER_CLEAR);
 233                 writel(~0, clock->regbase + TIMER_MATCH_VAL);
 234
 235                 ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
 236                 /* allow at least 10 seconds to notice that the timer wrapped */
 237                 ce->max_delta_ns =
 238                         clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
 239                 /* 4 gets rounded down to 3 */
 240                 ce->min_delta_ns = clockevent_delta2ns(4, ce);
 241                 ce->cpumask = cpumask_of(0);
 242
 243                 res = clocksource_register_hz(cs, clock->freq);
 244                 if (res)
 245                         printk(KERN_ERR "msm_timer_init: clocksource_register "
 246                                "failed for %s\n", cs->name);
 247
 248                 res = setup_irq(clock->irq.irq, &clock->irq);
 249                 if (res)
 250                         printk(KERN_ERR "msm_timer_init: setup_irq "
 251                                "failed for %s\n", cs->name);
 252
 253                 clockevents_register_device(ce);
 254         }
 255 }
 256
 257 #ifdef CONFIG_SMP
 258 void __cpuinit local_timer_setup(struct clock_event_device *evt)
 259 {
 260         struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
 261
 262         /* Use existing clock_event for cpu 0 */
 263         if (!smp_processor_id())
 264                 return;
 265
 266         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 267
 268         if (!local_clock_event) {
 269                 writel(0, clock->regbase  + TIMER_ENABLE);
 270                 writel(0, clock->regbase + TIMER_CLEAR);
 271                 writel(~0, clock->regbase + TIMER_MATCH_VAL);
 272         }
 273         evt->irq = clock->irq.irq;
 274         evt->name = "local_timer";
 275         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 276         evt->rating = clock->clockevent.rating;
 277         evt->set_mode = msm_timer_set_mode;
 278         evt->set_next_event = msm_timer_set_next_event;
 279         evt->shift = clock->clockevent.shift;
 280         evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
 281         evt->max_delta_ns =
 282                 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
 283         evt->min_delta_ns = clockevent_delta2ns(4, evt);
 284
 285         local_clock_event = evt;
 286
 287         gic_enable_ppi(clock->irq.irq);
 288
 289         clockevents_register_device(evt);
 290 }
 291
 292 inline int local_timer_ack(void)
 293 {
 294         return 1;
 295 }
 296
 297 #endif
 298
 299 struct sys_timer msm_timer = {
 300         .init = msm_timer_init
 301 };