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ocfs2: Make the left masklogs compat.
[taoma-kernel.git] / drivers / ata / sata_promise.c
blobf03ad48273ffe10117cc82984f0f4b3be0f34bcc
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/gfp.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include "sata_promise.h"
48
49 #define DRV_NAME "sata_promise"
50 #define DRV_VERSION "2.12"
51
52 enum {
53 PDC_MAX_PORTS = 4,
54 PDC_MMIO_BAR = 3,
55 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
56
57 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
58 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
59 PDC_FLASH_CTL = 0x44, /* Flash control register */
60 PDC_PCI_CTL = 0x48, /* PCI control/status reg */
61 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
62 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
63 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
64 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
65
66 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
67 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
68 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
69 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
70 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
71 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
72 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
73 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
74 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
75 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
76 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
77 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
78
79 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
80 PDC_SATA_ERROR = 0x04,
81 PDC_PHYMODE4 = 0x14,
82 PDC_LINK_LAYER_ERRORS = 0x6C,
83 PDC_FPDMA_CTLSTAT = 0xD8,
84 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
85 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
86
87 /* PDC_FPDMA_CTLSTAT bit definitions */
88 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
89 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
90 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
91
92 /* PDC_GLOBAL_CTL bit definitions */
93 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
94 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
95 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
96 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
97 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
98 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
99 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
100 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
101 PDC_DRIVE_ERR = (1 << 21), /* drive error */
102 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
103 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
104 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
105 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
106 PDC2_ATA_DMA_CNT_ERR,
107 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
108 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
109 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
110 PDC1_ERR_MASK | PDC2_ERR_MASK,
111
112 board_2037x = 0, /* FastTrak S150 TX2plus */
113 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
114 board_20319 = 2, /* FastTrak S150 TX4 */
115 board_20619 = 3, /* FastTrak TX4000 */
116 board_2057x = 4, /* SATAII150 Tx2plus */
117 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
118 board_40518 = 6, /* SATAII150 Tx4 */
119
120 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
121
122 /* Sequence counter control registers bit definitions */
123 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
124
125 /* Feature register values */
126 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
127 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
128
129 /* Device/Head register values */
130 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
131
132 /* PDC_CTLSTAT bit definitions */
133 PDC_DMA_ENABLE = (1 << 7),
134 PDC_IRQ_DISABLE = (1 << 10),
135 PDC_RESET = (1 << 11), /* HDMA reset */
136
137 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
138 ATA_FLAG_MMIO |
139 ATA_FLAG_PIO_POLLING,
140
141 /* ap->flags bits */
142 PDC_FLAG_GEN_II = (1 << 24),
143 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
144 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
145 };
146
147 struct pdc_port_priv {
148 u8 *pkt;
149 dma_addr_t pkt_dma;
150 };
151
152 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
153 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
154 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
155 static int pdc_common_port_start(struct ata_port *ap);
156 static int pdc_sata_port_start(struct ata_port *ap);
157 static void pdc_qc_prep(struct ata_queued_cmd *qc);
158 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
159 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
160 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
161 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
162 static void pdc_irq_clear(struct ata_port *ap);
163 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
164 static void pdc_freeze(struct ata_port *ap);
165 static void pdc_sata_freeze(struct ata_port *ap);
166 static void pdc_thaw(struct ata_port *ap);
167 static void pdc_sata_thaw(struct ata_port *ap);
168 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
169 unsigned long deadline);
170 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
171 unsigned long deadline);
172 static void pdc_error_handler(struct ata_port *ap);
173 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
174 static int pdc_pata_cable_detect(struct ata_port *ap);
175 static int pdc_sata_cable_detect(struct ata_port *ap);
176
177 static struct scsi_host_template pdc_ata_sht = {
178 ATA_BASE_SHT(DRV_NAME),
179 .sg_tablesize = PDC_MAX_PRD,
180 .dma_boundary = ATA_DMA_BOUNDARY,
181 };
182
183 static const struct ata_port_operations pdc_common_ops = {
184 .inherits = &ata_sff_port_ops,
185
186 .sff_tf_load = pdc_tf_load_mmio,
187 .sff_exec_command = pdc_exec_command_mmio,
188 .check_atapi_dma = pdc_check_atapi_dma,
189 .qc_prep = pdc_qc_prep,
190 .qc_issue = pdc_qc_issue,
191
192 .sff_irq_clear = pdc_irq_clear,
193 .lost_interrupt = ATA_OP_NULL,
194
195 .post_internal_cmd = pdc_post_internal_cmd,
196 .error_handler = pdc_error_handler,
197 };
198
199 static struct ata_port_operations pdc_sata_ops = {
200 .inherits = &pdc_common_ops,
201 .cable_detect = pdc_sata_cable_detect,
202 .freeze = pdc_sata_freeze,
203 .thaw = pdc_sata_thaw,
204 .scr_read = pdc_sata_scr_read,
205 .scr_write = pdc_sata_scr_write,
206 .port_start = pdc_sata_port_start,
207 .hardreset = pdc_sata_hardreset,
208 };
209
210 /* First-generation chips need a more restrictive ->check_atapi_dma op,
211 and ->freeze/thaw that ignore the hotplug controls. */
212 static struct ata_port_operations pdc_old_sata_ops = {
213 .inherits = &pdc_sata_ops,
214 .freeze = pdc_freeze,
215 .thaw = pdc_thaw,
216 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
217 };
218
219 static struct ata_port_operations pdc_pata_ops = {
220 .inherits = &pdc_common_ops,
221 .cable_detect = pdc_pata_cable_detect,
222 .freeze = pdc_freeze,
223 .thaw = pdc_thaw,
224 .port_start = pdc_common_port_start,
225 .softreset = pdc_pata_softreset,
226 };
227
228 static const struct ata_port_info pdc_port_info[] = {
229 [board_2037x] =
230 {
231 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
232 PDC_FLAG_SATA_PATA,
233 .pio_mask = ATA_PIO4,
234 .mwdma_mask = ATA_MWDMA2,
235 .udma_mask = ATA_UDMA6,
236 .port_ops = &pdc_old_sata_ops,
237 },
238
239 [board_2037x_pata] =
240 {
241 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
242 .pio_mask = ATA_PIO4,
243 .mwdma_mask = ATA_MWDMA2,
244 .udma_mask = ATA_UDMA6,
245 .port_ops = &pdc_pata_ops,
246 },
247
248 [board_20319] =
249 {
250 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
251 PDC_FLAG_4_PORTS,
252 .pio_mask = ATA_PIO4,
253 .mwdma_mask = ATA_MWDMA2,
254 .udma_mask = ATA_UDMA6,
255 .port_ops = &pdc_old_sata_ops,
256 },
257
258 [board_20619] =
259 {
260 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
261 PDC_FLAG_4_PORTS,
262 .pio_mask = ATA_PIO4,
263 .mwdma_mask = ATA_MWDMA2,
264 .udma_mask = ATA_UDMA6,
265 .port_ops = &pdc_pata_ops,
266 },
267
268 [board_2057x] =
269 {
270 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
271 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
272 .pio_mask = ATA_PIO4,
273 .mwdma_mask = ATA_MWDMA2,
274 .udma_mask = ATA_UDMA6,
275 .port_ops = &pdc_sata_ops,
276 },
277
278 [board_2057x_pata] =
279 {
280 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
281 PDC_FLAG_GEN_II,
282 .pio_mask = ATA_PIO4,
283 .mwdma_mask = ATA_MWDMA2,
284 .udma_mask = ATA_UDMA6,
285 .port_ops = &pdc_pata_ops,
286 },
287
288 [board_40518] =
289 {
290 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
291 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
292 .pio_mask = ATA_PIO4,
293 .mwdma_mask = ATA_MWDMA2,
294 .udma_mask = ATA_UDMA6,
295 .port_ops = &pdc_sata_ops,
296 },
297 };
298
299 static const struct pci_device_id pdc_ata_pci_tbl[] = {
300 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
301 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
302 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
303 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
304 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
305 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
306 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
307 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
308 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
309 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
310
311 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
312 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
313 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
314 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
315 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
316 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
317
318 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
319
320 { } /* terminate list */
321 };
322
323 static struct pci_driver pdc_ata_pci_driver = {
324 .name = DRV_NAME,
325 .id_table = pdc_ata_pci_tbl,
326 .probe = pdc_ata_init_one,
327 .remove = ata_pci_remove_one,
328 };
329
330 static int pdc_common_port_start(struct ata_port *ap)
331 {
332 struct device *dev = ap->host->dev;
333 struct pdc_port_priv *pp;
334 int rc;
335
336 /* we use the same prd table as bmdma, allocate it */
337 rc = ata_bmdma_port_start(ap);
338 if (rc)
339 return rc;
340
341 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
342 if (!pp)
343 return -ENOMEM;
344
345 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
346 if (!pp->pkt)
347 return -ENOMEM;
348
349 ap->private_data = pp;
350
351 return 0;
352 }
353
354 static int pdc_sata_port_start(struct ata_port *ap)
355 {
356 int rc;
357
358 rc = pdc_common_port_start(ap);
359 if (rc)
360 return rc;
361
362 /* fix up PHYMODE4 align timing */
363 if (ap->flags & PDC_FLAG_GEN_II) {
364 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
365 unsigned int tmp;
366
367 tmp = readl(sata_mmio + PDC_PHYMODE4);
368 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
369 writel(tmp, sata_mmio + PDC_PHYMODE4);
370 }
371
372 return 0;
373 }
374
375 static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
376 {
377 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
378 u32 tmp;
379
380 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
381 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
382 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
383
384 /* It's not allowed to write to the entire FPDMA_CTLSTAT register
385 when NCQ is running. So do a byte-sized write to bits 10 and 11. */
386 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
387 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
388 }
389
390 static void pdc_fpdma_reset(struct ata_port *ap)
391 {
392 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
393 u8 tmp;
394
395 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
396 tmp &= 0x7F;
397 tmp |= PDC_FPDMA_CTLSTAT_RESET;
398 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
399 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
400 udelay(100);
401 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
402 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
403 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
404
405 pdc_fpdma_clear_interrupt_flag(ap);
406 }
407
408 static void pdc_not_at_command_packet_phase(struct ata_port *ap)
409 {
410 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
411 unsigned int i;
412 u32 tmp;
413
414 /* check not at ASIC packet command phase */
415 for (i = 0; i < 100; ++i) {
416 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
417 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
418 if ((tmp & 0xF) != 1)
419 break;
420 udelay(100);
421 }
422 }
423
424 static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
425 {
426 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
427
428 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
429 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
430 }
431
432 static void pdc_reset_port(struct ata_port *ap)
433 {
434 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
435 unsigned int i;
436 u32 tmp;
437
438 if (ap->flags & PDC_FLAG_GEN_II)
439 pdc_not_at_command_packet_phase(ap);
440
441 tmp = readl(ata_ctlstat_mmio);
442 tmp |= PDC_RESET;
443 writel(tmp, ata_ctlstat_mmio);
444
445 for (i = 11; i > 0; i--) {
446 tmp = readl(ata_ctlstat_mmio);
447 if (tmp & PDC_RESET)
448 break;
449
450 udelay(100);
451
452 tmp |= PDC_RESET;
453 writel(tmp, ata_ctlstat_mmio);
454 }
455
456 tmp &= ~PDC_RESET;
457 writel(tmp, ata_ctlstat_mmio);
458 readl(ata_ctlstat_mmio); /* flush */
459
460 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
461 pdc_fpdma_reset(ap);
462 pdc_clear_internal_debug_record_error_register(ap);
463 }
464 }
465
466 static int pdc_pata_cable_detect(struct ata_port *ap)
467 {
468 u8 tmp;
469 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
470
471 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
472 if (tmp & 0x01)
473 return ATA_CBL_PATA40;
474 return ATA_CBL_PATA80;
475 }
476
477 static int pdc_sata_cable_detect(struct ata_port *ap)
478 {
479 return ATA_CBL_SATA;
480 }
481
482 static int pdc_sata_scr_read(struct ata_link *link,
483 unsigned int sc_reg, u32 *val)
484 {
485 if (sc_reg > SCR_CONTROL)
486 return -EINVAL;
487 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
488 return 0;
489 }
490
491 static int pdc_sata_scr_write(struct ata_link *link,
492 unsigned int sc_reg, u32 val)
493 {
494 if (sc_reg > SCR_CONTROL)
495 return -EINVAL;
496 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
497 return 0;
498 }
499
500 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
501 {
502 struct ata_port *ap = qc->ap;
503 dma_addr_t sg_table = ap->bmdma_prd_dma;
504 unsigned int cdb_len = qc->dev->cdb_len;
505 u8 *cdb = qc->cdb;
506 struct pdc_port_priv *pp = ap->private_data;
507 u8 *buf = pp->pkt;
508 __le32 *buf32 = (__le32 *) buf;
509 unsigned int dev_sel, feature;
510
511 /* set control bits (byte 0), zero delay seq id (byte 3),
512 * and seq id (byte 2)
513 */
514 switch (qc->tf.protocol) {
515 case ATAPI_PROT_DMA:
516 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
517 buf32[0] = cpu_to_le32(PDC_PKT_READ);
518 else
519 buf32[0] = 0;
520 break;
521 case ATAPI_PROT_NODATA:
522 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
523 break;
524 default:
525 BUG();
526 break;
527 }
528 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
529 buf32[2] = 0; /* no next-packet */
530
531 /* select drive */
532 if (sata_scr_valid(&ap->link))
533 dev_sel = PDC_DEVICE_SATA;
534 else
535 dev_sel = qc->tf.device;
536
537 buf[12] = (1 << 5) | ATA_REG_DEVICE;
538 buf[13] = dev_sel;
539 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
540 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
541
542 buf[16] = (1 << 5) | ATA_REG_NSECT;
543 buf[17] = qc->tf.nsect;
544 buf[18] = (1 << 5) | ATA_REG_LBAL;
545 buf[19] = qc->tf.lbal;
546
547 /* set feature and byte counter registers */
548 if (qc->tf.protocol != ATAPI_PROT_DMA)
549 feature = PDC_FEATURE_ATAPI_PIO;
550 else
551 feature = PDC_FEATURE_ATAPI_DMA;
552
553 buf[20] = (1 << 5) | ATA_REG_FEATURE;
554 buf[21] = feature;
555 buf[22] = (1 << 5) | ATA_REG_BYTEL;
556 buf[23] = qc->tf.lbam;
557 buf[24] = (1 << 5) | ATA_REG_BYTEH;
558 buf[25] = qc->tf.lbah;
559
560 /* send ATAPI packet command 0xA0 */
561 buf[26] = (1 << 5) | ATA_REG_CMD;
562 buf[27] = qc->tf.command;
563
564 /* select drive and check DRQ */
565 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
566 buf[29] = dev_sel;
567
568 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
569 BUG_ON(cdb_len & ~0x1E);
570
571 /* append the CDB as the final part */
572 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
573 memcpy(buf+31, cdb, cdb_len);
574 }
575
576 /**
577 * pdc_fill_sg - Fill PCI IDE PRD table
578 * @qc: Metadata associated with taskfile to be transferred
579 *
580 * Fill PCI IDE PRD (scatter-gather) table with segments
581 * associated with the current disk command.
582 * Make sure hardware does not choke on it.
583 *
584 * LOCKING:
585 * spin_lock_irqsave(host lock)
586 *
587 */
588 static void pdc_fill_sg(struct ata_queued_cmd *qc)
589 {
590 struct ata_port *ap = qc->ap;
591 struct ata_bmdma_prd *prd = ap->bmdma_prd;
592 struct scatterlist *sg;
593 const u32 SG_COUNT_ASIC_BUG = 41*4;
594 unsigned int si, idx;
595 u32 len;
596
597 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
598 return;
599
600 idx = 0;
601 for_each_sg(qc->sg, sg, qc->n_elem, si) {
602 u32 addr, offset;
603 u32 sg_len;
604
605 /* determine if physical DMA addr spans 64K boundary.
606 * Note h/w doesn't support 64-bit, so we unconditionally
607 * truncate dma_addr_t to u32.
608 */
609 addr = (u32) sg_dma_address(sg);
610 sg_len = sg_dma_len(sg);
611
612 while (sg_len) {
613 offset = addr & 0xffff;
614 len = sg_len;
615 if ((offset + sg_len) > 0x10000)
616 len = 0x10000 - offset;
617
618 prd[idx].addr = cpu_to_le32(addr);
619 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
620 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
621
622 idx++;
623 sg_len -= len;
624 addr += len;
625 }
626 }
627
628 len = le32_to_cpu(prd[idx - 1].flags_len);
629
630 if (len > SG_COUNT_ASIC_BUG) {
631 u32 addr;
632
633 VPRINTK("Splitting last PRD.\n");
634
635 addr = le32_to_cpu(prd[idx - 1].addr);
636 prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
637 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
638
639 addr = addr + len - SG_COUNT_ASIC_BUG;
640 len = SG_COUNT_ASIC_BUG;
641 prd[idx].addr = cpu_to_le32(addr);
642 prd[idx].flags_len = cpu_to_le32(len);
643 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
644
645 idx++;
646 }
647
648 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
649 }
650
651 static void pdc_qc_prep(struct ata_queued_cmd *qc)
652 {
653 struct pdc_port_priv *pp = qc->ap->private_data;
654 unsigned int i;
655
656 VPRINTK("ENTER\n");
657
658 switch (qc->tf.protocol) {
659 case ATA_PROT_DMA:
660 pdc_fill_sg(qc);
661 /*FALLTHROUGH*/
662 case ATA_PROT_NODATA:
663 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
664 qc->dev->devno, pp->pkt);
665 if (qc->tf.flags & ATA_TFLAG_LBA48)
666 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
667 else
668 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
669 pdc_pkt_footer(&qc->tf, pp->pkt, i);
670 break;
671 case ATAPI_PROT_PIO:
672 pdc_fill_sg(qc);
673 break;
674 case ATAPI_PROT_DMA:
675 pdc_fill_sg(qc);
676 /*FALLTHROUGH*/
677 case ATAPI_PROT_NODATA:
678 pdc_atapi_pkt(qc);
679 break;
680 default:
681 break;
682 }
683 }
684
685 static int pdc_is_sataii_tx4(unsigned long flags)
686 {
687 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
688 return (flags & mask) == mask;
689 }
690
691 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
692 int is_sataii_tx4)
693 {
694 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
695 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
696 }
697
698 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
699 {
700 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
701 }
702
703 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
704 {
705 const struct ata_host *host = ap->host;
706 unsigned int nr_ports = pdc_sata_nr_ports(ap);
707 unsigned int i;
708
709 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
710 ;
711 BUG_ON(i >= nr_ports);
712 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
713 }
714
715 static void pdc_freeze(struct ata_port *ap)
716 {
717 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
718 u32 tmp;
719
720 tmp = readl(ata_mmio + PDC_CTLSTAT);
721 tmp |= PDC_IRQ_DISABLE;
722 tmp &= ~PDC_DMA_ENABLE;
723 writel(tmp, ata_mmio + PDC_CTLSTAT);
724 readl(ata_mmio + PDC_CTLSTAT); /* flush */
725 }
726
727 static void pdc_sata_freeze(struct ata_port *ap)
728 {
729 struct ata_host *host = ap->host;
730 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
731 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
732 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
733 u32 hotplug_status;
734
735 /* Disable hotplug events on this port.
736 *
737 * Locking:
738 * 1) hotplug register accesses must be serialised via host->lock
739 * 2) ap->lock == &ap->host->lock
740 * 3) ->freeze() and ->thaw() are called with ap->lock held
741 */
742 hotplug_status = readl(host_mmio + hotplug_offset);
743 hotplug_status |= 0x11 << (ata_no + 16);
744 writel(hotplug_status, host_mmio + hotplug_offset);
745 readl(host_mmio + hotplug_offset); /* flush */
746
747 pdc_freeze(ap);
748 }
749
750 static void pdc_thaw(struct ata_port *ap)
751 {
752 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
753 u32 tmp;
754
755 /* clear IRQ */
756 readl(ata_mmio + PDC_COMMAND);
757
758 /* turn IRQ back on */
759 tmp = readl(ata_mmio + PDC_CTLSTAT);
760 tmp &= ~PDC_IRQ_DISABLE;
761 writel(tmp, ata_mmio + PDC_CTLSTAT);
762 readl(ata_mmio + PDC_CTLSTAT); /* flush */
763 }
764
765 static void pdc_sata_thaw(struct ata_port *ap)
766 {
767 struct ata_host *host = ap->host;
768 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
769 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
770 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
771 u32 hotplug_status;
772
773 pdc_thaw(ap);
774
775 /* Enable hotplug events on this port.
776 * Locking: see pdc_sata_freeze().
777 */
778 hotplug_status = readl(host_mmio + hotplug_offset);
779 hotplug_status |= 0x11 << ata_no;
780 hotplug_status &= ~(0x11 << (ata_no + 16));
781 writel(hotplug_status, host_mmio + hotplug_offset);
782 readl(host_mmio + hotplug_offset); /* flush */
783 }
784
785 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
786 unsigned long deadline)
787 {
788 pdc_reset_port(link->ap);
789 return ata_sff_softreset(link, class, deadline);
790 }
791
792 static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
793 {
794 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
795 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
796
797 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
798 return (ata_mmio - host_mmio - 0x200) / 0x80;
799 }
800
801 static void pdc_hard_reset_port(struct ata_port *ap)
802 {
803 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
804 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
805 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
806 u8 tmp;
807
808 spin_lock(&ap->host->lock);
809
810 tmp = readb(pcictl_b1_mmio);
811 tmp &= ~(0x10 << ata_no);
812 writeb(tmp, pcictl_b1_mmio);
813 readb(pcictl_b1_mmio); /* flush */
814 udelay(100);
815 tmp |= (0x10 << ata_no);
816 writeb(tmp, pcictl_b1_mmio);
817 readb(pcictl_b1_mmio); /* flush */
818
819 spin_unlock(&ap->host->lock);
820 }
821
822 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
823 unsigned long deadline)
824 {
825 if (link->ap->flags & PDC_FLAG_GEN_II)
826 pdc_not_at_command_packet_phase(link->ap);
827 /* hotplug IRQs should have been masked by pdc_sata_freeze() */
828 pdc_hard_reset_port(link->ap);
829 pdc_reset_port(link->ap);
830
831 /* sata_promise can't reliably acquire the first D2H Reg FIS
832 * after hardreset. Do non-waiting hardreset and request
833 * follow-up SRST.
834 */
835 return sata_std_hardreset(link, class, deadline);
836 }
837
838 static void pdc_error_handler(struct ata_port *ap)
839 {
840 if (!(ap->pflags & ATA_PFLAG_FROZEN))
841 pdc_reset_port(ap);
842
843 ata_sff_error_handler(ap);
844 }
845
846 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
847 {
848 struct ata_port *ap = qc->ap;
849
850 /* make DMA engine forget about the failed command */
851 if (qc->flags & ATA_QCFLAG_FAILED)
852 pdc_reset_port(ap);
853 }
854
855 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
856 u32 port_status, u32 err_mask)
857 {
858 struct ata_eh_info *ehi = &ap->link.eh_info;
859 unsigned int ac_err_mask = 0;
860
861 ata_ehi_clear_desc(ehi);
862 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
863 port_status &= err_mask;
864
865 if (port_status & PDC_DRIVE_ERR)
866 ac_err_mask |= AC_ERR_DEV;
867 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
868 ac_err_mask |= AC_ERR_OTHER;
869 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
870 ac_err_mask |= AC_ERR_ATA_BUS;
871 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
872 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
873 ac_err_mask |= AC_ERR_HOST_BUS;
874
875 if (sata_scr_valid(&ap->link)) {
876 u32 serror;
877
878 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
879 ehi->serror |= serror;
880 }
881
882 qc->err_mask |= ac_err_mask;
883
884 pdc_reset_port(ap);
885
886 ata_port_abort(ap);
887 }
888
889 static unsigned int pdc_host_intr(struct ata_port *ap,
890 struct ata_queued_cmd *qc)
891 {
892 unsigned int handled = 0;
893 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
894 u32 port_status, err_mask;
895
896 err_mask = PDC_ERR_MASK;
897 if (ap->flags & PDC_FLAG_GEN_II)
898 err_mask &= ~PDC1_ERR_MASK;
899 else
900 err_mask &= ~PDC2_ERR_MASK;
901 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
902 if (unlikely(port_status & err_mask)) {
903 pdc_error_intr(ap, qc, port_status, err_mask);
904 return 1;
905 }
906
907 switch (qc->tf.protocol) {
908 case ATA_PROT_DMA:
909 case ATA_PROT_NODATA:
910 case ATAPI_PROT_DMA:
911 case ATAPI_PROT_NODATA:
912 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
913 ata_qc_complete(qc);
914 handled = 1;
915 break;
916 default:
917 ap->stats.idle_irq++;
918 break;
919 }
920
921 return handled;
922 }
923
924 static void pdc_irq_clear(struct ata_port *ap)
925 {
926 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
927
928 readl(ata_mmio + PDC_COMMAND);
929 }
930
931 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
932 {
933 struct ata_host *host = dev_instance;
934 struct ata_port *ap;
935 u32 mask = 0;
936 unsigned int i, tmp;
937 unsigned int handled = 0;
938 void __iomem *host_mmio;
939 unsigned int hotplug_offset, ata_no;
940 u32 hotplug_status;
941 int is_sataii_tx4;
942
943 VPRINTK("ENTER\n");
944
945 if (!host || !host->iomap[PDC_MMIO_BAR]) {
946 VPRINTK("QUICK EXIT\n");
947 return IRQ_NONE;
948 }
949
950 host_mmio = host->iomap[PDC_MMIO_BAR];
951
952 spin_lock(&host->lock);
953
954 /* read and clear hotplug flags for all ports */
955 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
956 hotplug_offset = PDC2_SATA_PLUG_CSR;
957 hotplug_status = readl(host_mmio + hotplug_offset);
958 if (hotplug_status & 0xff)
959 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
960 hotplug_status &= 0xff; /* clear uninteresting bits */
961 } else
962 hotplug_status = 0;
963
964 /* reading should also clear interrupts */
965 mask = readl(host_mmio + PDC_INT_SEQMASK);
966
967 if (mask == 0xffffffff && hotplug_status == 0) {
968 VPRINTK("QUICK EXIT 2\n");
969 goto done_irq;
970 }
971
972 mask &= 0xffff; /* only 16 SEQIDs possible */
973 if (mask == 0 && hotplug_status == 0) {
974 VPRINTK("QUICK EXIT 3\n");
975 goto done_irq;
976 }
977
978 writel(mask, host_mmio + PDC_INT_SEQMASK);
979
980 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
981
982 for (i = 0; i < host->n_ports; i++) {
983 VPRINTK("port %u\n", i);
984 ap = host->ports[i];
985
986 /* check for a plug or unplug event */
987 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
988 tmp = hotplug_status & (0x11 << ata_no);
989 if (tmp) {
990 struct ata_eh_info *ehi = &ap->link.eh_info;
991 ata_ehi_clear_desc(ehi);
992 ata_ehi_hotplugged(ehi);
993 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
994 ata_port_freeze(ap);
995 ++handled;
996 continue;
997 }
998
999 /* check for a packet interrupt */
1000 tmp = mask & (1 << (i + 1));
1001 if (tmp) {
1002 struct ata_queued_cmd *qc;
1003
1004 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1005 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1006 handled += pdc_host_intr(ap, qc);
1007 }
1008 }
1009
1010 VPRINTK("EXIT\n");
1011
1012 done_irq:
1013 spin_unlock(&host->lock);
1014 return IRQ_RETVAL(handled);
1015 }
1016
1017 static void pdc_packet_start(struct ata_queued_cmd *qc)
1018 {
1019 struct ata_port *ap = qc->ap;
1020 struct pdc_port_priv *pp = ap->private_data;
1021 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1022 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1023 unsigned int port_no = ap->port_no;
1024 u8 seq = (u8) (port_no + 1);
1025
1026 VPRINTK("ENTER, ap %p\n", ap);
1027
1028 writel(0x00000001, host_mmio + (seq * 4));
1029 readl(host_mmio + (seq * 4)); /* flush */
1030
1031 pp->pkt[2] = seq;
1032 wmb(); /* flush PRD, pkt writes */
1033 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1034 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1035 }
1036
1037 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1038 {
1039 switch (qc->tf.protocol) {
1040 case ATAPI_PROT_NODATA:
1041 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1042 break;
1043 /*FALLTHROUGH*/
1044 case ATA_PROT_NODATA:
1045 if (qc->tf.flags & ATA_TFLAG_POLLING)
1046 break;
1047 /*FALLTHROUGH*/
1048 case ATAPI_PROT_DMA:
1049 case ATA_PROT_DMA:
1050 pdc_packet_start(qc);
1051 return 0;
1052 default:
1053 break;
1054 }
1055 return ata_sff_qc_issue(qc);
1056 }
1057
1058 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1059 {
1060 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1061 ata_sff_tf_load(ap, tf);
1062 }
1063
1064 static void pdc_exec_command_mmio(struct ata_port *ap,
1065 const struct ata_taskfile *tf)
1066 {
1067 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1068 ata_sff_exec_command(ap, tf);
1069 }
1070
1071 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1072 {
1073 u8 *scsicmd = qc->scsicmd->cmnd;
1074 int pio = 1; /* atapi dma off by default */
1075
1076 /* Whitelist commands that may use DMA. */
1077 switch (scsicmd[0]) {
1078 case WRITE_12:
1079 case WRITE_10:
1080 case WRITE_6:
1081 case READ_12:
1082 case READ_10:
1083 case READ_6:
1084 case 0xad: /* READ_DVD_STRUCTURE */
1085 case 0xbe: /* READ_CD */
1086 pio = 0;
1087 }
1088 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1089 if (scsicmd[0] == WRITE_10) {
1090 unsigned int lba =
1091 (scsicmd[2] << 24) |
1092 (scsicmd[3] << 16) |
1093 (scsicmd[4] << 8) |
1094 scsicmd[5];
1095 if (lba >= 0xFFFF4FA2)
1096 pio = 1;
1097 }
1098 return pio;
1099 }
1100
1101 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1102 {
1103 /* First generation chips cannot use ATAPI DMA on SATA ports */
1104 return 1;
1105 }
1106
1107 static void pdc_ata_setup_port(struct ata_port *ap,
1108 void __iomem *base, void __iomem *scr_addr)
1109 {
1110 ap->ioaddr.cmd_addr = base;
1111 ap->ioaddr.data_addr = base;
1112 ap->ioaddr.feature_addr =
1113 ap->ioaddr.error_addr = base + 0x4;
1114 ap->ioaddr.nsect_addr = base + 0x8;
1115 ap->ioaddr.lbal_addr = base + 0xc;
1116 ap->ioaddr.lbam_addr = base + 0x10;
1117 ap->ioaddr.lbah_addr = base + 0x14;
1118 ap->ioaddr.device_addr = base + 0x18;
1119 ap->ioaddr.command_addr =
1120 ap->ioaddr.status_addr = base + 0x1c;
1121 ap->ioaddr.altstatus_addr =
1122 ap->ioaddr.ctl_addr = base + 0x38;
1123 ap->ioaddr.scr_addr = scr_addr;
1124 }
1125
1126 static void pdc_host_init(struct ata_host *host)
1127 {
1128 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1129 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1130 int hotplug_offset;
1131 u32 tmp;
1132
1133 if (is_gen2)
1134 hotplug_offset = PDC2_SATA_PLUG_CSR;
1135 else
1136 hotplug_offset = PDC_SATA_PLUG_CSR;
1137
1138 /*
1139 * Except for the hotplug stuff, this is voodoo from the
1140 * Promise driver. Label this entire section
1141 * "TODO: figure out why we do this"
1142 */
1143
1144 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1145 tmp = readl(host_mmio + PDC_FLASH_CTL);
1146 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1147 if (!is_gen2)
1148 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1149 writel(tmp, host_mmio + PDC_FLASH_CTL);
1150
1151 /* clear plug/unplug flags for all ports */
1152 tmp = readl(host_mmio + hotplug_offset);
1153 writel(tmp | 0xff, host_mmio + hotplug_offset);
1154
1155 tmp = readl(host_mmio + hotplug_offset);
1156 if (is_gen2) /* unmask plug/unplug ints */
1157 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1158 else /* mask plug/unplug ints */
1159 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1160
1161 /* don't initialise TBG or SLEW on 2nd generation chips */
1162 if (is_gen2)
1163 return;
1164
1165 /* reduce TBG clock to 133 Mhz. */
1166 tmp = readl(host_mmio + PDC_TBG_MODE);
1167 tmp &= ~0x30000; /* clear bit 17, 16*/
1168 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1169 writel(tmp, host_mmio + PDC_TBG_MODE);
1170
1171 readl(host_mmio + PDC_TBG_MODE); /* flush */
1172 msleep(10);
1173
1174 /* adjust slew rate control register. */
1175 tmp = readl(host_mmio + PDC_SLEW_CTL);
1176 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1177 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1178 writel(tmp, host_mmio + PDC_SLEW_CTL);
1179 }
1180
1181 static int pdc_ata_init_one(struct pci_dev *pdev,
1182 const struct pci_device_id *ent)
1183 {
1184 static int printed_version;
1185 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1186 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1187 struct ata_host *host;
1188 void __iomem *host_mmio;
1189 int n_ports, i, rc;
1190 int is_sataii_tx4;
1191
1192 if (!printed_version++)
1193 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1194
1195 /* enable and acquire resources */
1196 rc = pcim_enable_device(pdev);
1197 if (rc)
1198 return rc;
1199
1200 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1201 if (rc == -EBUSY)
1202 pcim_pin_device(pdev);
1203 if (rc)
1204 return rc;
1205 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1206
1207 /* determine port configuration and setup host */
1208 n_ports = 2;
1209 if (pi->flags & PDC_FLAG_4_PORTS)
1210 n_ports = 4;
1211 for (i = 0; i < n_ports; i++)
1212 ppi[i] = pi;
1213
1214 if (pi->flags & PDC_FLAG_SATA_PATA) {
1215 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1216 if (!(tmp & 0x80))
1217 ppi[n_ports++] = pi + 1;
1218 }
1219
1220 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1221 if (!host) {
1222 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1223 return -ENOMEM;
1224 }
1225 host->iomap = pcim_iomap_table(pdev);
1226
1227 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1228 for (i = 0; i < host->n_ports; i++) {
1229 struct ata_port *ap = host->ports[i];
1230 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1231 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1232 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1233
1234 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1235
1236 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1237 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1238 }
1239
1240 /* initialize adapter */
1241 pdc_host_init(host);
1242
1243 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1244 if (rc)
1245 return rc;
1246 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1247 if (rc)
1248 return rc;
1249
1250 /* start host, request IRQ and attach */
1251 pci_set_master(pdev);
1252 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1253 &pdc_ata_sht);
1254 }
1255
1256 static int __init pdc_ata_init(void)
1257 {
1258 return pci_register_driver(&pdc_ata_pci_driver);
1259 }
1260
1261 static void __exit pdc_ata_exit(void)
1262 {
1263 pci_unregister_driver(&pdc_ata_pci_driver);
1264 }
1265
1266 MODULE_AUTHOR("Jeff Garzik");
1267 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1268 MODULE_LICENSE("GPL");
1269 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1270 MODULE_VERSION(DRV_VERSION);
1271
1272 module_init(pdc_ata_init);
1273 module_exit(pdc_ata_exit);
The kernel tree for Tao Ma.