drivers/gpu/drm/nouveau/nv50_gpio.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_hw.h"
  28
  29 #include "nv50_display.h"
  30
  31 static void nv50_gpio_isr(struct drm_device *dev);
  32 static void nv50_gpio_isr_bh(struct work_struct *work);
  33
  34 struct nv50_gpio_priv {
  35         struct list_head handlers;
  36         spinlock_t lock;
  37 };
  38
  39 struct nv50_gpio_handler {
  40         struct drm_device *dev;
  41         struct list_head head;
  42         struct work_struct work;
  43         bool inhibit;
  44
  45         struct dcb_gpio_entry *gpio;
  46
  47         void (*handler)(void *data, int state);
  48         void *data;
  49 };
  50
  51 static int
  52 nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
  53 {
  54         const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
  55
  56         if (gpio->line >= 32)
  57                 return -EINVAL;
  58
  59         *reg = nv50_gpio_reg[gpio->line >> 3];
  60         *shift = (gpio->line & 7) << 2;
  61         return 0;
  62 }
  63
  64 int
  65 nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
  66 {
  67         struct dcb_gpio_entry *gpio;
  68         uint32_t r, s, v;
  69
  70         gpio = nouveau_bios_gpio_entry(dev, tag);
  71         if (!gpio)
  72                 return -ENOENT;
  73
  74         if (nv50_gpio_location(gpio, &r, &s))
  75                 return -EINVAL;
  76
  77         v = nv_rd32(dev, r) >> (s + 2);
  78         return ((v & 1) == (gpio->state[1] & 1));
  79 }
  80
  81 int
  82 nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
  83 {
  84         struct dcb_gpio_entry *gpio;
  85         uint32_t r, s, v;
  86
  87         gpio = nouveau_bios_gpio_entry(dev, tag);
  88         if (!gpio)
  89                 return -ENOENT;
  90
  91         if (nv50_gpio_location(gpio, &r, &s))
  92                 return -EINVAL;
  93
  94         v  = nv_rd32(dev, r) & ~(0x3 << s);
  95         v |= (gpio->state[state] ^ 2) << s;
  96         nv_wr32(dev, r, v);
  97         return 0;
  98 }
  99
 100 int
 101 nv50_gpio_irq_register(struct drm_device *dev, enum dcb_gpio_tag tag,
 102                        void (*handler)(void *, int), void *data)
 103 {
 104         struct drm_nouveau_private *dev_priv = dev->dev_private;
 105         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 106         struct nv50_gpio_priv *priv = pgpio->priv;
 107         struct nv50_gpio_handler *gpioh;
 108         struct dcb_gpio_entry *gpio;
 109         unsigned long flags;
 110
 111         gpio = nouveau_bios_gpio_entry(dev, tag);
 112         if (!gpio)
 113                 return -ENOENT;
 114
 115         gpioh = kzalloc(sizeof(*gpioh), GFP_KERNEL);
 116         if (!gpioh)
 117                 return -ENOMEM;
 118
 119         INIT_WORK(&gpioh->work, nv50_gpio_isr_bh);
 120         gpioh->dev  = dev;
 121         gpioh->gpio = gpio;
 122         gpioh->handler = handler;
 123         gpioh->data = data;
 124
 125         spin_lock_irqsave(&priv->lock, flags);
 126         list_add(&gpioh->head, &priv->handlers);
 127         spin_unlock_irqrestore(&priv->lock, flags);
 128         return 0;
 129 }
 130
 131 void
 132 nv50_gpio_irq_unregister(struct drm_device *dev, enum dcb_gpio_tag tag,
 133                          void (*handler)(void *, int), void *data)
 134 {
 135         struct drm_nouveau_private *dev_priv = dev->dev_private;
 136         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 137         struct nv50_gpio_priv *priv = pgpio->priv;
 138         struct nv50_gpio_handler *gpioh, *tmp;
 139         struct dcb_gpio_entry *gpio;
 140         unsigned long flags;
 141
 142         gpio = nouveau_bios_gpio_entry(dev, tag);
 143         if (!gpio)
 144                 return;
 145
 146         spin_lock_irqsave(&priv->lock, flags);
 147         list_for_each_entry_safe(gpioh, tmp, &priv->handlers, head) {
 148                 if (gpioh->gpio != gpio ||
 149                     gpioh->handler != handler ||
 150                     gpioh->data != data)
 151                         continue;
 152                 list_del(&gpioh->head);
 153                 kfree(gpioh);
 154         }
 155         spin_unlock_irqrestore(&priv->lock, flags);
 156 }
 157
 158 bool
 159 nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
 160 {
 161         struct dcb_gpio_entry *gpio;
 162         u32 reg, mask;
 163
 164         gpio = nouveau_bios_gpio_entry(dev, tag);
 165         if (!gpio)
 166                 return false;
 167
 168         reg  = gpio->line < 16 ? 0xe050 : 0xe070;
 169         mask = 0x00010001 << (gpio->line & 0xf);
 170
 171         nv_wr32(dev, reg + 4, mask);
 172         reg = nv_mask(dev, reg + 0, mask, on ? mask : 0);
 173         return (reg & mask) == mask;
 174 }
 175
 176 static int
 177 nv50_gpio_create(struct drm_device *dev)
 178 {
 179         struct drm_nouveau_private *dev_priv = dev->dev_private;
 180         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 181         struct nv50_gpio_priv *priv;
 182
 183         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 184         if (!priv)
 185                 return -ENOMEM;
 186
 187         INIT_LIST_HEAD(&priv->handlers);
 188         spin_lock_init(&priv->lock);
 189         pgpio->priv = priv;
 190         return 0;
 191 }
 192
 193 static void
 194 nv50_gpio_destroy(struct drm_device *dev)
 195 {
 196         struct drm_nouveau_private *dev_priv = dev->dev_private;
 197         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 198
 199         kfree(pgpio->priv);
 200         pgpio->priv = NULL;
 201 }
 202
 203 int
 204 nv50_gpio_init(struct drm_device *dev)
 205 {
 206         struct drm_nouveau_private *dev_priv = dev->dev_private;
 207         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 208         struct nv50_gpio_priv *priv;
 209         int ret;
 210
 211         if (!pgpio->priv) {
 212                 ret = nv50_gpio_create(dev);
 213                 if (ret)
 214                         return ret;
 215         }
 216         priv = pgpio->priv;
 217
 218         /* disable, and ack any pending gpio interrupts */
 219         nv_wr32(dev, 0xe050, 0x00000000);
 220         nv_wr32(dev, 0xe054, 0xffffffff);
 221         if (dev_priv->chipset >= 0x90) {
 222                 nv_wr32(dev, 0xe070, 0x00000000);
 223                 nv_wr32(dev, 0xe074, 0xffffffff);
 224         }
 225
 226         nouveau_irq_register(dev, 21, nv50_gpio_isr);
 227         return 0;
 228 }
 229
 230 void
 231 nv50_gpio_fini(struct drm_device *dev)
 232 {
 233         struct drm_nouveau_private *dev_priv = dev->dev_private;
 234
 235         nv_wr32(dev, 0xe050, 0x00000000);
 236         if (dev_priv->chipset >= 0x90)
 237                 nv_wr32(dev, 0xe070, 0x00000000);
 238         nouveau_irq_unregister(dev, 21);
 239
 240         nv50_gpio_destroy(dev);
 241 }
 242
 243 static void
 244 nv50_gpio_isr_bh(struct work_struct *work)
 245 {
 246         struct nv50_gpio_handler *gpioh =
 247                 container_of(work, struct nv50_gpio_handler, work);
 248         struct drm_nouveau_private *dev_priv = gpioh->dev->dev_private;
 249         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 250         struct nv50_gpio_priv *priv = pgpio->priv;
 251         unsigned long flags;
 252         int state;
 253
 254         state = pgpio->get(gpioh->dev, gpioh->gpio->tag);
 255         if (state < 0)
 256                 return;
 257
 258         gpioh->handler(gpioh->data, state);
 259
 260         spin_lock_irqsave(&priv->lock, flags);
 261         gpioh->inhibit = false;
 262         spin_unlock_irqrestore(&priv->lock, flags);
 263 }
 264
 265 static void
 266 nv50_gpio_isr(struct drm_device *dev)
 267 {
 268         struct drm_nouveau_private *dev_priv = dev->dev_private;
 269         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 270         struct nv50_gpio_priv *priv = pgpio->priv;
 271         struct nv50_gpio_handler *gpioh;
 272         u32 intr0, intr1 = 0;
 273         u32 hi, lo, ch;
 274
 275         intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
 276         if (dev_priv->chipset >= 0x90)
 277                 intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
 278
 279         hi = (intr0 & 0x0000ffff) | (intr1 << 16);
 280         lo = (intr0 >> 16) | (intr1 & 0xffff0000);
 281         ch = hi | lo;
 282
 283         nv_wr32(dev, 0xe054, intr0);
 284         if (dev_priv->chipset >= 0x90)
 285                 nv_wr32(dev, 0xe074, intr1);
 286
 287         spin_lock(&priv->lock);
 288         list_for_each_entry(gpioh, &priv->handlers, head) {
 289                 if (!(ch & (1 << gpioh->gpio->line)))
 290                         continue;
 291
 292                 if (gpioh->inhibit)
 293                         continue;
 294                 gpioh->inhibit = true;
 295
 296                 queue_work(dev_priv->wq, &gpioh->work);
 297         }
 298         spin_unlock(&priv->lock);
 299 }