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ocfs2: Make the left masklogs compat.
[taoma-kernel.git] / drivers / net / mlx4 / main.c
blob2765a3ce9c24db25d1fbc5616cebf3da8f0c3e24
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42
43 #include <linux/mlx4/device.h>
44 #include <linux/mlx4/doorbell.h>
45
46 #include "mlx4.h"
47 #include "fw.h"
48 #include "icm.h"
49
50 MODULE_AUTHOR("Roland Dreier");
51 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
52 MODULE_LICENSE("Dual BSD/GPL");
53 MODULE_VERSION(DRV_VERSION);
54
55 struct workqueue_struct *mlx4_wq;
56
57 #ifdef CONFIG_MLX4_DEBUG
58
59 int mlx4_debug_level = 0;
60 module_param_named(debug_level, mlx4_debug_level, int, 0644);
61 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
62
63 #endif /* CONFIG_MLX4_DEBUG */
64
65 #ifdef CONFIG_PCI_MSI
66
67 static int msi_x = 1;
68 module_param(msi_x, int, 0444);
69 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
70
71 #else /* CONFIG_PCI_MSI */
72
73 #define msi_x (0)
74
75 #endif /* CONFIG_PCI_MSI */
76
77 static char mlx4_version[] __devinitdata =
78 DRV_NAME ": Mellanox ConnectX core driver v"
79 DRV_VERSION " (" DRV_RELDATE ")\n";
80
81 static struct mlx4_profile default_profile = {
82 .num_qp = 1 << 17,
83 .num_srq = 1 << 16,
84 .rdmarc_per_qp = 1 << 4,
85 .num_cq = 1 << 16,
86 .num_mcg = 1 << 13,
87 .num_mpt = 1 << 17,
88 .num_mtt = 1 << 20,
89 };
90
91 static int log_num_mac = 2;
92 module_param_named(log_num_mac, log_num_mac, int, 0444);
93 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
94
95 static int log_num_vlan;
96 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
97 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
98
99 static int use_prio;
100 module_param_named(use_prio, use_prio, bool, 0444);
101 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
102 "(0/1, default 0)");
103
104 static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
105 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
106 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
107
108 int mlx4_check_port_params(struct mlx4_dev *dev,
109 enum mlx4_port_type *port_type)
110 {
111 int i;
112
113 for (i = 0; i < dev->caps.num_ports - 1; i++) {
114 if (port_type[i] != port_type[i + 1]) {
115 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
116 mlx4_err(dev, "Only same port types supported "
117 "on this HCA, aborting.\n");
118 return -EINVAL;
119 }
120 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
121 port_type[i + 1] == MLX4_PORT_TYPE_IB)
122 return -EINVAL;
123 }
124 }
125
126 for (i = 0; i < dev->caps.num_ports; i++) {
127 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
128 mlx4_err(dev, "Requested port type for port %d is not "
129 "supported on this HCA\n", i + 1);
130 return -EINVAL;
131 }
132 }
133 return 0;
134 }
135
136 static void mlx4_set_port_mask(struct mlx4_dev *dev)
137 {
138 int i;
139
140 dev->caps.port_mask = 0;
141 for (i = 1; i <= dev->caps.num_ports; ++i)
142 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
143 dev->caps.port_mask |= 1 << (i - 1);
144 }
145 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
146 {
147 int err;
148 int i;
149
150 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
151 if (err) {
152 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
153 return err;
154 }
155
156 if (dev_cap->min_page_sz > PAGE_SIZE) {
157 mlx4_err(dev, "HCA minimum page size of %d bigger than "
158 "kernel PAGE_SIZE of %ld, aborting.\n",
159 dev_cap->min_page_sz, PAGE_SIZE);
160 return -ENODEV;
161 }
162 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
163 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
164 "aborting.\n",
165 dev_cap->num_ports, MLX4_MAX_PORTS);
166 return -ENODEV;
167 }
168
169 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
170 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
171 "PCI resource 2 size of 0x%llx, aborting.\n",
172 dev_cap->uar_size,
173 (unsigned long long) pci_resource_len(dev->pdev, 2));
174 return -ENODEV;
175 }
176
177 dev->caps.num_ports = dev_cap->num_ports;
178 for (i = 1; i <= dev->caps.num_ports; ++i) {
179 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
180 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
181 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
182 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
183 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
184 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
185 dev->caps.def_mac[i] = dev_cap->def_mac[i];
186 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
187 dev->caps.trans_type[i] = dev_cap->trans_type[i];
188 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
189 dev->caps.wavelength[i] = dev_cap->wavelength[i];
190 dev->caps.trans_code[i] = dev_cap->trans_code[i];
191 }
192
193 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
194 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
195 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
196 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
197 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
198 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
199 dev->caps.max_wqes = dev_cap->max_qp_sz;
200 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
201 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
202 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
203 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
204 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
205 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
206 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
207 /*
208 * Subtract 1 from the limit because we need to allocate a
209 * spare CQE so the HCA HW can tell the difference between an
210 * empty CQ and a full CQ.
211 */
212 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
213 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
214 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
215 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
216 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
217 dev->caps.mtts_per_seg);
218 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
219 dev->caps.reserved_uars = dev_cap->reserved_uars;
220 dev->caps.reserved_pds = dev_cap->reserved_pds;
221 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
222 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
223 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
224 dev->caps.flags = dev_cap->flags;
225 dev->caps.bmme_flags = dev_cap->bmme_flags;
226 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
227 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
228 dev->caps.udp_rss = dev_cap->udp_rss;
229 dev->caps.loopback_support = dev_cap->loopback_support;
230 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
231
232 dev->caps.log_num_macs = log_num_mac;
233 dev->caps.log_num_vlans = log_num_vlan;
234 dev->caps.log_num_prios = use_prio ? 3 : 0;
235
236 for (i = 1; i <= dev->caps.num_ports; ++i) {
237 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
238 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
239 else
240 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
241 dev->caps.possible_type[i] = dev->caps.port_type[i];
242 mlx4_priv(dev)->sense.sense_allowed[i] =
243 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
244
245 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
246 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
247 mlx4_warn(dev, "Requested number of MACs is too much "
248 "for port %d, reducing to %d.\n",
249 i, 1 << dev->caps.log_num_macs);
250 }
251 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
252 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
253 mlx4_warn(dev, "Requested number of VLANs is too much "
254 "for port %d, reducing to %d.\n",
255 i, 1 << dev->caps.log_num_vlans);
256 }
257 }
258
259 mlx4_set_port_mask(dev);
260
261 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
262 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
263 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
264 (1 << dev->caps.log_num_macs) *
265 (1 << dev->caps.log_num_vlans) *
266 (1 << dev->caps.log_num_prios) *
267 dev->caps.num_ports;
268 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
269
270 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
271 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
272 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
273 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
274
275 return 0;
276 }
277
278 /*
279 * Change the port configuration of the device.
280 * Every user of this function must hold the port mutex.
281 */
282 int mlx4_change_port_types(struct mlx4_dev *dev,
283 enum mlx4_port_type *port_types)
284 {
285 int err = 0;
286 int change = 0;
287 int port;
288
289 for (port = 0; port < dev->caps.num_ports; port++) {
290 /* Change the port type only if the new type is different
291 * from the current, and not set to Auto */
292 if (port_types[port] != dev->caps.port_type[port + 1]) {
293 change = 1;
294 dev->caps.port_type[port + 1] = port_types[port];
295 }
296 }
297 if (change) {
298 mlx4_unregister_device(dev);
299 for (port = 1; port <= dev->caps.num_ports; port++) {
300 mlx4_CLOSE_PORT(dev, port);
301 err = mlx4_SET_PORT(dev, port);
302 if (err) {
303 mlx4_err(dev, "Failed to set port %d, "
304 "aborting\n", port);
305 goto out;
306 }
307 }
308 mlx4_set_port_mask(dev);
309 err = mlx4_register_device(dev);
310 }
311
312 out:
313 return err;
314 }
315
316 static ssize_t show_port_type(struct device *dev,
317 struct device_attribute *attr,
318 char *buf)
319 {
320 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
321 port_attr);
322 struct mlx4_dev *mdev = info->dev;
323 char type[8];
324
325 sprintf(type, "%s",
326 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
327 "ib" : "eth");
328 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
329 sprintf(buf, "auto (%s)\n", type);
330 else
331 sprintf(buf, "%s\n", type);
332
333 return strlen(buf);
334 }
335
336 static ssize_t set_port_type(struct device *dev,
337 struct device_attribute *attr,
338 const char *buf, size_t count)
339 {
340 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
341 port_attr);
342 struct mlx4_dev *mdev = info->dev;
343 struct mlx4_priv *priv = mlx4_priv(mdev);
344 enum mlx4_port_type types[MLX4_MAX_PORTS];
345 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
346 int i;
347 int err = 0;
348
349 if (!strcmp(buf, "ib\n"))
350 info->tmp_type = MLX4_PORT_TYPE_IB;
351 else if (!strcmp(buf, "eth\n"))
352 info->tmp_type = MLX4_PORT_TYPE_ETH;
353 else if (!strcmp(buf, "auto\n"))
354 info->tmp_type = MLX4_PORT_TYPE_AUTO;
355 else {
356 mlx4_err(mdev, "%s is not supported port type\n", buf);
357 return -EINVAL;
358 }
359
360 mlx4_stop_sense(mdev);
361 mutex_lock(&priv->port_mutex);
362 /* Possible type is always the one that was delivered */
363 mdev->caps.possible_type[info->port] = info->tmp_type;
364
365 for (i = 0; i < mdev->caps.num_ports; i++) {
366 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
367 mdev->caps.possible_type[i+1];
368 if (types[i] == MLX4_PORT_TYPE_AUTO)
369 types[i] = mdev->caps.port_type[i+1];
370 }
371
372 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
373 for (i = 1; i <= mdev->caps.num_ports; i++) {
374 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
375 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
376 err = -EINVAL;
377 }
378 }
379 }
380 if (err) {
381 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
382 "Set only 'eth' or 'ib' for both ports "
383 "(should be the same)\n");
384 goto out;
385 }
386
387 mlx4_do_sense_ports(mdev, new_types, types);
388
389 err = mlx4_check_port_params(mdev, new_types);
390 if (err)
391 goto out;
392
393 /* We are about to apply the changes after the configuration
394 * was verified, no need to remember the temporary types
395 * any more */
396 for (i = 0; i < mdev->caps.num_ports; i++)
397 priv->port[i + 1].tmp_type = 0;
398
399 err = mlx4_change_port_types(mdev, new_types);
400
401 out:
402 mlx4_start_sense(mdev);
403 mutex_unlock(&priv->port_mutex);
404 return err ? err : count;
405 }
406
407 static int mlx4_load_fw(struct mlx4_dev *dev)
408 {
409 struct mlx4_priv *priv = mlx4_priv(dev);
410 int err;
411
412 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
413 GFP_HIGHUSER | __GFP_NOWARN, 0);
414 if (!priv->fw.fw_icm) {
415 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
416 return -ENOMEM;
417 }
418
419 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
420 if (err) {
421 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
422 goto err_free;
423 }
424
425 err = mlx4_RUN_FW(dev);
426 if (err) {
427 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
428 goto err_unmap_fa;
429 }
430
431 return 0;
432
433 err_unmap_fa:
434 mlx4_UNMAP_FA(dev);
435
436 err_free:
437 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
438 return err;
439 }
440
441 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
442 int cmpt_entry_sz)
443 {
444 struct mlx4_priv *priv = mlx4_priv(dev);
445 int err;
446
447 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
448 cmpt_base +
449 ((u64) (MLX4_CMPT_TYPE_QP *
450 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
451 cmpt_entry_sz, dev->caps.num_qps,
452 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
453 0, 0);
454 if (err)
455 goto err;
456
457 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
458 cmpt_base +
459 ((u64) (MLX4_CMPT_TYPE_SRQ *
460 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
461 cmpt_entry_sz, dev->caps.num_srqs,
462 dev->caps.reserved_srqs, 0, 0);
463 if (err)
464 goto err_qp;
465
466 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
467 cmpt_base +
468 ((u64) (MLX4_CMPT_TYPE_CQ *
469 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
470 cmpt_entry_sz, dev->caps.num_cqs,
471 dev->caps.reserved_cqs, 0, 0);
472 if (err)
473 goto err_srq;
474
475 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
476 cmpt_base +
477 ((u64) (MLX4_CMPT_TYPE_EQ *
478 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
479 cmpt_entry_sz,
480 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
481 if (err)
482 goto err_cq;
483
484 return 0;
485
486 err_cq:
487 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
488
489 err_srq:
490 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
491
492 err_qp:
493 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
494
495 err:
496 return err;
497 }
498
499 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
500 struct mlx4_init_hca_param *init_hca, u64 icm_size)
501 {
502 struct mlx4_priv *priv = mlx4_priv(dev);
503 u64 aux_pages;
504 int err;
505
506 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
507 if (err) {
508 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
509 return err;
510 }
511
512 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
513 (unsigned long long) icm_size >> 10,
514 (unsigned long long) aux_pages << 2);
515
516 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
517 GFP_HIGHUSER | __GFP_NOWARN, 0);
518 if (!priv->fw.aux_icm) {
519 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
520 return -ENOMEM;
521 }
522
523 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
524 if (err) {
525 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
526 goto err_free_aux;
527 }
528
529 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
530 if (err) {
531 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
532 goto err_unmap_aux;
533 }
534
535 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
536 init_hca->eqc_base, dev_cap->eqc_entry_sz,
537 dev->caps.num_eqs, dev->caps.num_eqs,
538 0, 0);
539 if (err) {
540 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
541 goto err_unmap_cmpt;
542 }
543
544 /*
545 * Reserved MTT entries must be aligned up to a cacheline
546 * boundary, since the FW will write to them, while the driver
547 * writes to all other MTT entries. (The variable
548 * dev->caps.mtt_entry_sz below is really the MTT segment
549 * size, not the raw entry size)
550 */
551 dev->caps.reserved_mtts =
552 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
553 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
554
555 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
556 init_hca->mtt_base,
557 dev->caps.mtt_entry_sz,
558 dev->caps.num_mtt_segs,
559 dev->caps.reserved_mtts, 1, 0);
560 if (err) {
561 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
562 goto err_unmap_eq;
563 }
564
565 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
566 init_hca->dmpt_base,
567 dev_cap->dmpt_entry_sz,
568 dev->caps.num_mpts,
569 dev->caps.reserved_mrws, 1, 1);
570 if (err) {
571 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
572 goto err_unmap_mtt;
573 }
574
575 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
576 init_hca->qpc_base,
577 dev_cap->qpc_entry_sz,
578 dev->caps.num_qps,
579 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
580 0, 0);
581 if (err) {
582 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
583 goto err_unmap_dmpt;
584 }
585
586 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
587 init_hca->auxc_base,
588 dev_cap->aux_entry_sz,
589 dev->caps.num_qps,
590 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
591 0, 0);
592 if (err) {
593 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
594 goto err_unmap_qp;
595 }
596
597 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
598 init_hca->altc_base,
599 dev_cap->altc_entry_sz,
600 dev->caps.num_qps,
601 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
602 0, 0);
603 if (err) {
604 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
605 goto err_unmap_auxc;
606 }
607
608 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
609 init_hca->rdmarc_base,
610 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
611 dev->caps.num_qps,
612 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
613 0, 0);
614 if (err) {
615 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
616 goto err_unmap_altc;
617 }
618
619 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
620 init_hca->cqc_base,
621 dev_cap->cqc_entry_sz,
622 dev->caps.num_cqs,
623 dev->caps.reserved_cqs, 0, 0);
624 if (err) {
625 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
626 goto err_unmap_rdmarc;
627 }
628
629 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
630 init_hca->srqc_base,
631 dev_cap->srq_entry_sz,
632 dev->caps.num_srqs,
633 dev->caps.reserved_srqs, 0, 0);
634 if (err) {
635 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
636 goto err_unmap_cq;
637 }
638
639 /*
640 * It's not strictly required, but for simplicity just map the
641 * whole multicast group table now. The table isn't very big
642 * and it's a lot easier than trying to track ref counts.
643 */
644 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
645 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
646 dev->caps.num_mgms + dev->caps.num_amgms,
647 dev->caps.num_mgms + dev->caps.num_amgms,
648 0, 0);
649 if (err) {
650 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
651 goto err_unmap_srq;
652 }
653
654 return 0;
655
656 err_unmap_srq:
657 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
658
659 err_unmap_cq:
660 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
661
662 err_unmap_rdmarc:
663 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
664
665 err_unmap_altc:
666 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
667
668 err_unmap_auxc:
669 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
670
671 err_unmap_qp:
672 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
673
674 err_unmap_dmpt:
675 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
676
677 err_unmap_mtt:
678 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
679
680 err_unmap_eq:
681 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
682
683 err_unmap_cmpt:
684 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
685 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
686 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
687 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
688
689 err_unmap_aux:
690 mlx4_UNMAP_ICM_AUX(dev);
691
692 err_free_aux:
693 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
694
695 return err;
696 }
697
698 static void mlx4_free_icms(struct mlx4_dev *dev)
699 {
700 struct mlx4_priv *priv = mlx4_priv(dev);
701
702 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
703 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
704 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
705 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
706 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
707 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
708 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
709 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
710 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
711 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
712 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
713 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
714 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
715 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
716
717 mlx4_UNMAP_ICM_AUX(dev);
718 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
719 }
720
721 static void mlx4_close_hca(struct mlx4_dev *dev)
722 {
723 mlx4_CLOSE_HCA(dev, 0);
724 mlx4_free_icms(dev);
725 mlx4_UNMAP_FA(dev);
726 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
727 }
728
729 static int mlx4_init_hca(struct mlx4_dev *dev)
730 {
731 struct mlx4_priv *priv = mlx4_priv(dev);
732 struct mlx4_adapter adapter;
733 struct mlx4_dev_cap dev_cap;
734 struct mlx4_mod_stat_cfg mlx4_cfg;
735 struct mlx4_profile profile;
736 struct mlx4_init_hca_param init_hca;
737 u64 icm_size;
738 int err;
739
740 err = mlx4_QUERY_FW(dev);
741 if (err) {
742 if (err == -EACCES)
743 mlx4_info(dev, "non-primary physical function, skipping.\n");
744 else
745 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
746 return err;
747 }
748
749 err = mlx4_load_fw(dev);
750 if (err) {
751 mlx4_err(dev, "Failed to start FW, aborting.\n");
752 return err;
753 }
754
755 mlx4_cfg.log_pg_sz_m = 1;
756 mlx4_cfg.log_pg_sz = 0;
757 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
758 if (err)
759 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
760
761 err = mlx4_dev_cap(dev, &dev_cap);
762 if (err) {
763 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
764 goto err_stop_fw;
765 }
766
767 profile = default_profile;
768
769 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
770 if ((long long) icm_size < 0) {
771 err = icm_size;
772 goto err_stop_fw;
773 }
774
775 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
776
777 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
778 if (err)
779 goto err_stop_fw;
780
781 err = mlx4_INIT_HCA(dev, &init_hca);
782 if (err) {
783 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
784 goto err_free_icm;
785 }
786
787 err = mlx4_QUERY_ADAPTER(dev, &adapter);
788 if (err) {
789 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
790 goto err_close;
791 }
792
793 priv->eq_table.inta_pin = adapter.inta_pin;
794 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
795
796 return 0;
797
798 err_close:
799 mlx4_CLOSE_HCA(dev, 0);
800
801 err_free_icm:
802 mlx4_free_icms(dev);
803
804 err_stop_fw:
805 mlx4_UNMAP_FA(dev);
806 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
807
808 return err;
809 }
810
811 static int mlx4_setup_hca(struct mlx4_dev *dev)
812 {
813 struct mlx4_priv *priv = mlx4_priv(dev);
814 int err;
815 int port;
816 __be32 ib_port_default_caps;
817
818 err = mlx4_init_uar_table(dev);
819 if (err) {
820 mlx4_err(dev, "Failed to initialize "
821 "user access region table, aborting.\n");
822 return err;
823 }
824
825 err = mlx4_uar_alloc(dev, &priv->driver_uar);
826 if (err) {
827 mlx4_err(dev, "Failed to allocate driver access region, "
828 "aborting.\n");
829 goto err_uar_table_free;
830 }
831
832 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
833 if (!priv->kar) {
834 mlx4_err(dev, "Couldn't map kernel access region, "
835 "aborting.\n");
836 err = -ENOMEM;
837 goto err_uar_free;
838 }
839
840 err = mlx4_init_pd_table(dev);
841 if (err) {
842 mlx4_err(dev, "Failed to initialize "
843 "protection domain table, aborting.\n");
844 goto err_kar_unmap;
845 }
846
847 err = mlx4_init_mr_table(dev);
848 if (err) {
849 mlx4_err(dev, "Failed to initialize "
850 "memory region table, aborting.\n");
851 goto err_pd_table_free;
852 }
853
854 err = mlx4_init_eq_table(dev);
855 if (err) {
856 mlx4_err(dev, "Failed to initialize "
857 "event queue table, aborting.\n");
858 goto err_mr_table_free;
859 }
860
861 err = mlx4_cmd_use_events(dev);
862 if (err) {
863 mlx4_err(dev, "Failed to switch to event-driven "
864 "firmware commands, aborting.\n");
865 goto err_eq_table_free;
866 }
867
868 err = mlx4_NOP(dev);
869 if (err) {
870 if (dev->flags & MLX4_FLAG_MSI_X) {
871 mlx4_warn(dev, "NOP command failed to generate MSI-X "
872 "interrupt IRQ %d).\n",
873 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
874 mlx4_warn(dev, "Trying again without MSI-X.\n");
875 } else {
876 mlx4_err(dev, "NOP command failed to generate interrupt "
877 "(IRQ %d), aborting.\n",
878 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
879 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
880 }
881
882 goto err_cmd_poll;
883 }
884
885 mlx4_dbg(dev, "NOP command IRQ test passed\n");
886
887 err = mlx4_init_cq_table(dev);
888 if (err) {
889 mlx4_err(dev, "Failed to initialize "
890 "completion queue table, aborting.\n");
891 goto err_cmd_poll;
892 }
893
894 err = mlx4_init_srq_table(dev);
895 if (err) {
896 mlx4_err(dev, "Failed to initialize "
897 "shared receive queue table, aborting.\n");
898 goto err_cq_table_free;
899 }
900
901 err = mlx4_init_qp_table(dev);
902 if (err) {
903 mlx4_err(dev, "Failed to initialize "
904 "queue pair table, aborting.\n");
905 goto err_srq_table_free;
906 }
907
908 err = mlx4_init_mcg_table(dev);
909 if (err) {
910 mlx4_err(dev, "Failed to initialize "
911 "multicast group table, aborting.\n");
912 goto err_qp_table_free;
913 }
914
915 for (port = 1; port <= dev->caps.num_ports; port++) {
916 ib_port_default_caps = 0;
917 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
918 if (err)
919 mlx4_warn(dev, "failed to get port %d default "
920 "ib capabilities (%d). Continuing with "
921 "caps = 0\n", port, err);
922 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
923 err = mlx4_SET_PORT(dev, port);
924 if (err) {
925 mlx4_err(dev, "Failed to set port %d, aborting\n",
926 port);
927 goto err_mcg_table_free;
928 }
929 }
930
931 return 0;
932
933 err_mcg_table_free:
934 mlx4_cleanup_mcg_table(dev);
935
936 err_qp_table_free:
937 mlx4_cleanup_qp_table(dev);
938
939 err_srq_table_free:
940 mlx4_cleanup_srq_table(dev);
941
942 err_cq_table_free:
943 mlx4_cleanup_cq_table(dev);
944
945 err_cmd_poll:
946 mlx4_cmd_use_polling(dev);
947
948 err_eq_table_free:
949 mlx4_cleanup_eq_table(dev);
950
951 err_mr_table_free:
952 mlx4_cleanup_mr_table(dev);
953
954 err_pd_table_free:
955 mlx4_cleanup_pd_table(dev);
956
957 err_kar_unmap:
958 iounmap(priv->kar);
959
960 err_uar_free:
961 mlx4_uar_free(dev, &priv->driver_uar);
962
963 err_uar_table_free:
964 mlx4_cleanup_uar_table(dev);
965 return err;
966 }
967
968 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
969 {
970 struct mlx4_priv *priv = mlx4_priv(dev);
971 struct msix_entry *entries;
972 int nreq;
973 int err;
974 int i;
975
976 if (msi_x) {
977 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
978 num_possible_cpus() + 1);
979 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
980 if (!entries)
981 goto no_msi;
982
983 for (i = 0; i < nreq; ++i)
984 entries[i].entry = i;
985
986 retry:
987 err = pci_enable_msix(dev->pdev, entries, nreq);
988 if (err) {
989 /* Try again if at least 2 vectors are available */
990 if (err > 1) {
991 mlx4_info(dev, "Requested %d vectors, "
992 "but only %d MSI-X vectors available, "
993 "trying again\n", nreq, err);
994 nreq = err;
995 goto retry;
996 }
997 kfree(entries);
998 goto no_msi;
999 }
1000
1001 dev->caps.num_comp_vectors = nreq - 1;
1002 for (i = 0; i < nreq; ++i)
1003 priv->eq_table.eq[i].irq = entries[i].vector;
1004
1005 dev->flags |= MLX4_FLAG_MSI_X;
1006
1007 kfree(entries);
1008 return;
1009 }
1010
1011 no_msi:
1012 dev->caps.num_comp_vectors = 1;
1013
1014 for (i = 0; i < 2; ++i)
1015 priv->eq_table.eq[i].irq = dev->pdev->irq;
1016 }
1017
1018 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1019 {
1020 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1021 int err = 0;
1022
1023 info->dev = dev;
1024 info->port = port;
1025 mlx4_init_mac_table(dev, &info->mac_table);
1026 mlx4_init_vlan_table(dev, &info->vlan_table);
1027
1028 sprintf(info->dev_name, "mlx4_port%d", port);
1029 info->port_attr.attr.name = info->dev_name;
1030 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1031 info->port_attr.show = show_port_type;
1032 info->port_attr.store = set_port_type;
1033 sysfs_attr_init(&info->port_attr.attr);
1034
1035 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1036 if (err) {
1037 mlx4_err(dev, "Failed to create file for port %d\n", port);
1038 info->port = -1;
1039 }
1040
1041 return err;
1042 }
1043
1044 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1045 {
1046 if (info->port < 0)
1047 return;
1048
1049 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1050 }
1051
1052 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1053 {
1054 struct mlx4_priv *priv;
1055 struct mlx4_dev *dev;
1056 int err;
1057 int port;
1058
1059 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1060
1061 err = pci_enable_device(pdev);
1062 if (err) {
1063 dev_err(&pdev->dev, "Cannot enable PCI device, "
1064 "aborting.\n");
1065 return err;
1066 }
1067
1068 /*
1069 * Check for BARs. We expect 0: 1MB
1070 */
1071 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1072 pci_resource_len(pdev, 0) != 1 << 20) {
1073 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1074 err = -ENODEV;
1075 goto err_disable_pdev;
1076 }
1077 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1078 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1079 err = -ENODEV;
1080 goto err_disable_pdev;
1081 }
1082
1083 err = pci_request_regions(pdev, DRV_NAME);
1084 if (err) {
1085 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1086 goto err_disable_pdev;
1087 }
1088
1089 pci_set_master(pdev);
1090
1091 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1092 if (err) {
1093 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1094 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1095 if (err) {
1096 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1097 goto err_release_regions;
1098 }
1099 }
1100 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1101 if (err) {
1102 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1103 "consistent PCI DMA mask.\n");
1104 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1105 if (err) {
1106 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1107 "aborting.\n");
1108 goto err_release_regions;
1109 }
1110 }
1111
1112 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1113 if (!priv) {
1114 dev_err(&pdev->dev, "Device struct alloc failed, "
1115 "aborting.\n");
1116 err = -ENOMEM;
1117 goto err_release_regions;
1118 }
1119
1120 dev = &priv->dev;
1121 dev->pdev = pdev;
1122 INIT_LIST_HEAD(&priv->ctx_list);
1123 spin_lock_init(&priv->ctx_lock);
1124
1125 mutex_init(&priv->port_mutex);
1126
1127 INIT_LIST_HEAD(&priv->pgdir_list);
1128 mutex_init(&priv->pgdir_mutex);
1129
1130 /*
1131 * Now reset the HCA before we touch the PCI capabilities or
1132 * attempt a firmware command, since a boot ROM may have left
1133 * the HCA in an undefined state.
1134 */
1135 err = mlx4_reset(dev);
1136 if (err) {
1137 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1138 goto err_free_dev;
1139 }
1140
1141 if (mlx4_cmd_init(dev)) {
1142 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1143 goto err_free_dev;
1144 }
1145
1146 err = mlx4_init_hca(dev);
1147 if (err)
1148 goto err_cmd;
1149
1150 err = mlx4_alloc_eq_table(dev);
1151 if (err)
1152 goto err_close;
1153
1154 mlx4_enable_msi_x(dev);
1155
1156 err = mlx4_setup_hca(dev);
1157 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1158 dev->flags &= ~MLX4_FLAG_MSI_X;
1159 pci_disable_msix(pdev);
1160 err = mlx4_setup_hca(dev);
1161 }
1162
1163 if (err)
1164 goto err_free_eq;
1165
1166 for (port = 1; port <= dev->caps.num_ports; port++) {
1167 err = mlx4_init_port_info(dev, port);
1168 if (err)
1169 goto err_port;
1170 }
1171
1172 err = mlx4_register_device(dev);
1173 if (err)
1174 goto err_port;
1175
1176 mlx4_sense_init(dev);
1177 mlx4_start_sense(dev);
1178
1179 pci_set_drvdata(pdev, dev);
1180
1181 return 0;
1182
1183 err_port:
1184 for (--port; port >= 1; --port)
1185 mlx4_cleanup_port_info(&priv->port[port]);
1186
1187 mlx4_cleanup_mcg_table(dev);
1188 mlx4_cleanup_qp_table(dev);
1189 mlx4_cleanup_srq_table(dev);
1190 mlx4_cleanup_cq_table(dev);
1191 mlx4_cmd_use_polling(dev);
1192 mlx4_cleanup_eq_table(dev);
1193 mlx4_cleanup_mr_table(dev);
1194 mlx4_cleanup_pd_table(dev);
1195 mlx4_cleanup_uar_table(dev);
1196
1197 err_free_eq:
1198 mlx4_free_eq_table(dev);
1199
1200 err_close:
1201 if (dev->flags & MLX4_FLAG_MSI_X)
1202 pci_disable_msix(pdev);
1203
1204 mlx4_close_hca(dev);
1205
1206 err_cmd:
1207 mlx4_cmd_cleanup(dev);
1208
1209 err_free_dev:
1210 kfree(priv);
1211
1212 err_release_regions:
1213 pci_release_regions(pdev);
1214
1215 err_disable_pdev:
1216 pci_disable_device(pdev);
1217 pci_set_drvdata(pdev, NULL);
1218 return err;
1219 }
1220
1221 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1222 const struct pci_device_id *id)
1223 {
1224 printk_once(KERN_INFO "%s", mlx4_version);
1225
1226 return __mlx4_init_one(pdev, id);
1227 }
1228
1229 static void mlx4_remove_one(struct pci_dev *pdev)
1230 {
1231 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1232 struct mlx4_priv *priv = mlx4_priv(dev);
1233 int p;
1234
1235 if (dev) {
1236 mlx4_stop_sense(dev);
1237 mlx4_unregister_device(dev);
1238
1239 for (p = 1; p <= dev->caps.num_ports; p++) {
1240 mlx4_cleanup_port_info(&priv->port[p]);
1241 mlx4_CLOSE_PORT(dev, p);
1242 }
1243
1244 mlx4_cleanup_mcg_table(dev);
1245 mlx4_cleanup_qp_table(dev);
1246 mlx4_cleanup_srq_table(dev);
1247 mlx4_cleanup_cq_table(dev);
1248 mlx4_cmd_use_polling(dev);
1249 mlx4_cleanup_eq_table(dev);
1250 mlx4_cleanup_mr_table(dev);
1251 mlx4_cleanup_pd_table(dev);
1252
1253 iounmap(priv->kar);
1254 mlx4_uar_free(dev, &priv->driver_uar);
1255 mlx4_cleanup_uar_table(dev);
1256 mlx4_free_eq_table(dev);
1257 mlx4_close_hca(dev);
1258 mlx4_cmd_cleanup(dev);
1259
1260 if (dev->flags & MLX4_FLAG_MSI_X)
1261 pci_disable_msix(pdev);
1262
1263 kfree(priv);
1264 pci_release_regions(pdev);
1265 pci_disable_device(pdev);
1266 pci_set_drvdata(pdev, NULL);
1267 }
1268 }
1269
1270 int mlx4_restart_one(struct pci_dev *pdev)
1271 {
1272 mlx4_remove_one(pdev);
1273 return __mlx4_init_one(pdev, NULL);
1274 }
1275
1276 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
1277 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1278 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1279 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1280 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1281 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1282 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1283 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1284 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1285 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1286 { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
1287 { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
1288 { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
1289 { PCI_VDEVICE(MELLANOX, 0x1002) }, /* MT25400 Family [ConnectX-2 Virtual Function] */
1290 { PCI_VDEVICE(MELLANOX, 0x1003) }, /* MT27500 Family [ConnectX-3] */
1291 { PCI_VDEVICE(MELLANOX, 0x1004) }, /* MT27500 Family [ConnectX-3 Virtual Function] */
1292 { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
1293 { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
1294 { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
1295 { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
1296 { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
1297 { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
1298 { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
1299 { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
1300 { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
1301 { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
1302 { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
1303 { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
1304 { 0, }
1305 };
1306
1307 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1308
1309 static struct pci_driver mlx4_driver = {
1310 .name = DRV_NAME,
1311 .id_table = mlx4_pci_table,
1312 .probe = mlx4_init_one,
1313 .remove = __devexit_p(mlx4_remove_one)
1314 };
1315
1316 static int __init mlx4_verify_params(void)
1317 {
1318 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1319 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
1320 return -1;
1321 }
1322
1323 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1324 pr_warning("mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1325 return -1;
1326 }
1327
1328 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
1329 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1330 return -1;
1331 }
1332
1333 return 0;
1334 }
1335
1336 static int __init mlx4_init(void)
1337 {
1338 int ret;
1339
1340 if (mlx4_verify_params())
1341 return -EINVAL;
1342
1343 mlx4_catas_init();
1344
1345 mlx4_wq = create_singlethread_workqueue("mlx4");
1346 if (!mlx4_wq)
1347 return -ENOMEM;
1348
1349 ret = pci_register_driver(&mlx4_driver);
1350 return ret < 0 ? ret : 0;
1351 }
1352
1353 static void __exit mlx4_cleanup(void)
1354 {
1355 pci_unregister_driver(&mlx4_driver);
1356 destroy_workqueue(mlx4_wq);
1357 }
1358
1359 module_init(mlx4_init);
1360 module_exit(mlx4_cleanup);
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