drivers/net/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/compiler.h>
  38 #include <linux/list.h>
  39 #include <linux/mutex.h>
  40 #include <linux/netdevice.h>
  41
  42 #include <linux/mlx4/device.h>
  43 #include <linux/mlx4/qp.h>
  44 #include <linux/mlx4/cq.h>
  45 #include <linux/mlx4/srq.h>
  46 #include <linux/mlx4/doorbell.h>
  47 #include <linux/mlx4/cmd.h>
  48
  49 #include "en_port.h"
  50
  51 #define DRV_NAME        "mlx4_en"
  52 #define DRV_VERSION     "1.5.1.6"
  53 #define DRV_RELDATE     "August 2010"
  54
  55 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  56
  57 /*
  58  * Device constants
  59  */
  60
  61
  62 #define MLX4_EN_PAGE_SHIFT      12
  63 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  64 #define MAX_RX_RINGS            16
  65 #define TXBB_SIZE               64
  66 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  67 #define STAMP_STRIDE            64
  68 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  69 #define STAMP_SHIFT             31
  70 #define STAMP_VAL               0x7fffffff
  71 #define STATS_DELAY             (HZ / 4)
  72
  73 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  74 #define MAX_DESC_SIZE           512
  75 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  76
  77 /*
  78  * OS related constants and tunables
  79  */
  80
  81 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  82
  83 #define MLX4_EN_ALLOC_ORDER     2
  84 #define MLX4_EN_ALLOC_SIZE      (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
  85
  86 #define MLX4_EN_MAX_LRO_DESCRIPTORS     32
  87
  88 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
  89  * and 4K allocations) */
  90 enum {
  91         FRAG_SZ0 = 512 - NET_IP_ALIGN,
  92         FRAG_SZ1 = 1024,
  93         FRAG_SZ2 = 4096,
  94         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
  95 };
  96 #define MLX4_EN_MAX_RX_FRAGS    4
  97
  98 /* Maximum ring sizes */
  99 #define MLX4_EN_MAX_TX_SIZE     8192
 100 #define MLX4_EN_MAX_RX_SIZE     8192
 101
 102 /* Minimum ring size for our page-allocation sceme to work */
 103 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 104 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 105
 106 #define MLX4_EN_SMALL_PKT_SIZE          64
 107 #define MLX4_EN_NUM_TX_RINGS            8
 108 #define MLX4_EN_NUM_PPP_RINGS           8
 109 #define MAX_TX_RINGS                    (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
 110 #define MLX4_EN_DEF_TX_RING_SIZE        512
 111 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 112
 113 /* Target number of packets to coalesce with interrupt moderation */
 114 #define MLX4_EN_RX_COAL_TARGET  44
 115 #define MLX4_EN_RX_COAL_TIME    0x10
 116
 117 #define MLX4_EN_TX_COAL_PKTS    5
 118 #define MLX4_EN_TX_COAL_TIME    0x80
 119
 120 #define MLX4_EN_RX_RATE_LOW             400000
 121 #define MLX4_EN_RX_COAL_TIME_LOW        0
 122 #define MLX4_EN_RX_RATE_HIGH            450000
 123 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 124 #define MLX4_EN_RX_SIZE_THRESH          1024
 125 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 126 #define MLX4_EN_SAMPLE_INTERVAL         0
 127
 128 #define MLX4_EN_AUTO_CONF       0xffff
 129
 130 #define MLX4_EN_DEF_RX_PAUSE    1
 131 #define MLX4_EN_DEF_TX_PAUSE    1
 132
 133 /* Interval between successive polls in the Tx routine when polling is used
 134    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 135 #define MLX4_EN_TX_POLL_MODER   16
 136 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 137
 138 #define ETH_LLC_SNAP_SIZE       8
 139
 140 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 141 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 142 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 143
 144 #define MLX4_EN_MIN_MTU         46
 145 #define ETH_BCAST               0xffffffffffffULL
 146
 147 #define MLX4_EN_LOOPBACK_RETRIES        5
 148 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 149
 150 #ifdef MLX4_EN_PERF_STAT
 151 /* Number of samples to 'average' */
 152 #define AVG_SIZE                        128
 153 #define AVG_FACTOR                      1024
 154 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 155
 156 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 157 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 158 #define AVG_PERF_COUNTER(cnt, sample) \
 159         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 160 #define GET_PERF_COUNTER(cnt)           (cnt)
 161 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 162
 163 #else
 164
 165 #define NUM_PERF_STATS                  0
 166 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 167 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 168 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 169 #define GET_PERF_COUNTER(cnt)           (0)
 170 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 171 #endif /* MLX4_EN_PERF_STAT */
 172
 173 /*
 174  * Configurables
 175  */
 176
 177 enum cq_type {
 178         RX = 0,
 179         TX = 1,
 180 };
 181
 182
 183 /*
 184  * Useful macros
 185  */
 186 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 187 #define XNOR(x, y)              (!(x) == !(y))
 188 #define ILLEGAL_MAC(addr)       (addr == 0xffffffffffffULL || addr == 0x0)
 189
 190
 191 struct mlx4_en_tx_info {
 192         struct sk_buff *skb;
 193         u32 nr_txbb;
 194         u8 linear;
 195         u8 data_offset;
 196         u8 inl;
 197 };
 198
 199
 200 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 201 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 202 #define MLX4_EN_MEMTYPE_PAD     0x100
 203 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 204
 205
 206 struct mlx4_en_tx_desc {
 207         struct mlx4_wqe_ctrl_seg ctrl;
 208         union {
 209                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 210                 struct mlx4_wqe_lso_seg lso;
 211                 struct mlx4_wqe_inline_seg inl;
 212         };
 213 };
 214
 215 #define MLX4_EN_USE_SRQ         0x01000000
 216
 217 struct mlx4_en_rx_alloc {
 218         struct page *page;
 219         u16 offset;
 220 };
 221
 222 struct mlx4_en_tx_ring {
 223         struct mlx4_hwq_resources wqres;
 224         u32 size ; /* number of TXBBs */
 225         u32 size_mask;
 226         u16 stride;
 227         u16 cqn;        /* index of port CQ associated with this ring */
 228         u32 prod;
 229         u32 cons;
 230         u32 buf_size;
 231         u32 doorbell_qpn;
 232         void *buf;
 233         u16 poll_cnt;
 234         int blocked;
 235         struct mlx4_en_tx_info *tx_info;
 236         u8 *bounce_buf;
 237         u32 last_nr_txbb;
 238         struct mlx4_qp qp;
 239         struct mlx4_qp_context context;
 240         int qpn;
 241         enum mlx4_qp_state qp_state;
 242         struct mlx4_srq dummy;
 243         unsigned long bytes;
 244         unsigned long packets;
 245         spinlock_t comp_lock;
 246 };
 247
 248 struct mlx4_en_rx_desc {
 249         /* actual number of entries depends on rx ring stride */
 250         struct mlx4_wqe_data_seg data[0];
 251 };
 252
 253 struct mlx4_en_rx_ring {
 254         struct mlx4_hwq_resources wqres;
 255         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 256         u32 size ;      /* number of Rx descs*/
 257         u32 actual_size;
 258         u32 size_mask;
 259         u16 stride;
 260         u16 log_stride;
 261         u16 cqn;        /* index of port CQ associated with this ring */
 262         u32 prod;
 263         u32 cons;
 264         u32 buf_size;
 265         void *buf;
 266         void *rx_info;
 267         unsigned long bytes;
 268         unsigned long packets;
 269 };
 270
 271
 272 static inline int mlx4_en_can_lro(__be16 status)
 273 {
 274         return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4       |
 275                                      MLX4_CQE_STATUS_IPV4F      |
 276                                      MLX4_CQE_STATUS_IPV6       |
 277                                      MLX4_CQE_STATUS_IPV4OPT    |
 278                                      MLX4_CQE_STATUS_TCP        |
 279                                      MLX4_CQE_STATUS_UDP        |
 280                                      MLX4_CQE_STATUS_IPOK)) ==
 281                 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 282                             MLX4_CQE_STATUS_IPOK |
 283                             MLX4_CQE_STATUS_TCP);
 284 }
 285
 286 struct mlx4_en_cq {
 287         struct mlx4_cq          mcq;
 288         struct mlx4_hwq_resources wqres;
 289         int                     ring;
 290         spinlock_t              lock;
 291         struct net_device      *dev;
 292         struct napi_struct      napi;
 293         /* Per-core Tx cq processing support */
 294         struct timer_list timer;
 295         int size;
 296         int buf_size;
 297         unsigned vector;
 298         enum cq_type is_tx;
 299         u16 moder_time;
 300         u16 moder_cnt;
 301         struct mlx4_cqe *buf;
 302 #define MLX4_EN_OPCODE_ERROR    0x1e
 303 };
 304
 305 struct mlx4_en_port_profile {
 306         u32 flags;
 307         u32 tx_ring_num;
 308         u32 rx_ring_num;
 309         u32 tx_ring_size;
 310         u32 rx_ring_size;
 311         u8 rx_pause;
 312         u8 rx_ppp;
 313         u8 tx_pause;
 314         u8 tx_ppp;
 315 };
 316
 317 struct mlx4_en_profile {
 318         int rss_xor;
 319         int tcp_rss;
 320         int udp_rss;
 321         u8 rss_mask;
 322         u32 active_ports;
 323         u32 small_pkt_int;
 324         u8 no_reset;
 325         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 326 };
 327
 328 struct mlx4_en_dev {
 329         struct mlx4_dev         *dev;
 330         struct pci_dev          *pdev;
 331         struct mutex            state_lock;
 332         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 333         u32                     port_cnt;
 334         bool                    device_up;
 335         struct mlx4_en_profile  profile;
 336         u32                     LSO_support;
 337         struct workqueue_struct *workqueue;
 338         struct device           *dma_device;
 339         void __iomem            *uar_map;
 340         struct mlx4_uar         priv_uar;
 341         struct mlx4_mr          mr;
 342         u32                     priv_pdn;
 343         spinlock_t              uar_lock;
 344         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 345 };
 346
 347
 348 struct mlx4_en_rss_map {
 349         int base_qpn;
 350         struct mlx4_qp qps[MAX_RX_RINGS];
 351         enum mlx4_qp_state state[MAX_RX_RINGS];
 352         struct mlx4_qp indir_qp;
 353         enum mlx4_qp_state indir_state;
 354 };
 355
 356 struct mlx4_en_rss_context {
 357         __be32 base_qpn;
 358         __be32 default_qpn;
 359         u16 reserved;
 360         u8 hash_fn;
 361         u8 flags;
 362         __be32 rss_key[10];
 363         __be32 base_qpn_udp;
 364 };
 365
 366 struct mlx4_en_port_state {
 367         int link_state;
 368         int link_speed;
 369         int transciver;
 370 };
 371
 372 struct mlx4_en_pkt_stats {
 373         unsigned long broadcast;
 374         unsigned long rx_prio[8];
 375         unsigned long tx_prio[8];
 376 #define NUM_PKT_STATS           17
 377 };
 378
 379 struct mlx4_en_port_stats {
 380         unsigned long tso_packets;
 381         unsigned long queue_stopped;
 382         unsigned long wake_queue;
 383         unsigned long tx_timeout;
 384         unsigned long rx_alloc_failed;
 385         unsigned long rx_chksum_good;
 386         unsigned long rx_chksum_none;
 387         unsigned long tx_chksum_offload;
 388 #define NUM_PORT_STATS          8
 389 };
 390
 391 struct mlx4_en_perf_stats {
 392         u32 tx_poll;
 393         u64 tx_pktsz_avg;
 394         u32 inflight_avg;
 395         u16 tx_coal_avg;
 396         u16 rx_coal_avg;
 397         u32 napi_quota;
 398 #define NUM_PERF_COUNTERS               6
 399 };
 400
 401 struct mlx4_en_frag_info {
 402         u16 frag_size;
 403         u16 frag_prefix_size;
 404         u16 frag_stride;
 405         u16 frag_align;
 406         u16 last_offset;
 407
 408 };
 409
 410 struct mlx4_en_priv {
 411         struct mlx4_en_dev *mdev;
 412         struct mlx4_en_port_profile *prof;
 413         struct net_device *dev;
 414         struct vlan_group *vlgrp;
 415         struct net_device_stats stats;
 416         struct net_device_stats ret_stats;
 417         struct mlx4_en_port_state port_state;
 418         spinlock_t stats_lock;
 419
 420         unsigned long last_moder_packets;
 421         unsigned long last_moder_tx_packets;
 422         unsigned long last_moder_bytes;
 423         unsigned long last_moder_jiffies;
 424         int last_moder_time;
 425         u16 rx_usecs;
 426         u16 rx_frames;
 427         u16 tx_usecs;
 428         u16 tx_frames;
 429         u32 pkt_rate_low;
 430         u16 rx_usecs_low;
 431         u32 pkt_rate_high;
 432         u16 rx_usecs_high;
 433         u16 sample_interval;
 434         u16 adaptive_rx_coal;
 435         u32 msg_enable;
 436         u32 loopback_ok;
 437         u32 validate_loopback;
 438
 439         struct mlx4_hwq_resources res;
 440         int link_state;
 441         int last_link_state;
 442         bool port_up;
 443         int port;
 444         int registered;
 445         int allocated;
 446         int stride;
 447         int rx_csum;
 448         u64 mac;
 449         int mac_index;
 450         unsigned max_mtu;
 451         int base_qpn;
 452
 453         struct mlx4_en_rss_map rss_map;
 454         u32 flags;
 455 #define MLX4_EN_FLAG_PROMISC    0x1
 456         u32 tx_ring_num;
 457         u32 rx_ring_num;
 458         u32 rx_skb_size;
 459         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 460         u16 num_frags;
 461         u16 log_rx_info;
 462
 463         struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
 464         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 465         struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
 466         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 467         struct work_struct mcast_task;
 468         struct work_struct mac_task;
 469         struct work_struct watchdog_task;
 470         struct work_struct linkstate_task;
 471         struct delayed_work stats_task;
 472         struct mlx4_en_perf_stats pstats;
 473         struct mlx4_en_pkt_stats pkstats;
 474         struct mlx4_en_port_stats port_stats;
 475         char *mc_addrs;
 476         int mc_addrs_cnt;
 477         struct mlx4_en_stat_out_mbox hw_stats;
 478         int vids[128];
 479 };
 480
 481
 482 void mlx4_en_destroy_netdev(struct net_device *dev);
 483 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 484                         struct mlx4_en_port_profile *prof);
 485
 486 int mlx4_en_start_port(struct net_device *dev);
 487 void mlx4_en_stop_port(struct net_device *dev);
 488
 489 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 490 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 491
 492 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 493                       int entries, int ring, enum cq_type mode);
 494 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 495 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 496 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 497 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 498 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 499
 500 void mlx4_en_poll_tx_cq(unsigned long data);
 501 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 502 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
 503 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 504
 505 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 506                            u32 size, u16 stride);
 507 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 508 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 509                              struct mlx4_en_tx_ring *ring,
 510                              int cq);
 511 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 512                                 struct mlx4_en_tx_ring *ring);
 513
 514 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 515                            struct mlx4_en_rx_ring *ring,
 516                            u32 size, u16 stride);
 517 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 518                              struct mlx4_en_rx_ring *ring);
 519 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 520 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 521                                 struct mlx4_en_rx_ring *ring);
 522 int mlx4_en_process_rx_cq(struct net_device *dev,
 523                           struct mlx4_en_cq *cq,
 524                           int budget);
 525 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 526 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 527                              int is_tx, int rss, int qpn, int cqn,
 528                              struct mlx4_qp_context *context);
 529 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 530 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 531 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 532
 533 void mlx4_en_calc_rx_buf(struct net_device *dev);
 534 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 535 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 536 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 537 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 538
 539 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 540 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
 541 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
 542                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
 543 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 544                            u8 promisc);
 545
 546 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 547 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 548
 549 #define MLX4_EN_NUM_SELF_TEST   5
 550 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 551 u64 mlx4_en_mac_to_u64(u8 *addr);
 552
 553 /*
 554  * Globals
 555  */
 556 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 557
 558
 559
 560 /*
 561  * printk / logging functions
 562  */
 563
 564 int en_print(const char *level, const struct mlx4_en_priv *priv,
 565              const char *format, ...) __attribute__ ((format (printf, 3, 4)));
 566
 567 #define en_dbg(mlevel, priv, format, arg...)                    \
 568 do {                                                            \
 569         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
 570                 en_print(KERN_DEBUG, priv, format, ##arg);      \
 571 } while (0)
 572 #define en_warn(priv, format, arg...)                   \
 573         en_print(KERN_WARNING, priv, format, ##arg)
 574 #define en_err(priv, format, arg...)                    \
 575         en_print(KERN_ERR, priv, format, ##arg)
 576 #define en_info(priv, format, arg...)                   \
 577         en_print(KERN_INFO, priv, format, ## arg)
 578
 579 #define mlx4_err(mdev, format, arg...)                  \
 580         pr_err("%s %s: " format, DRV_NAME,              \
 581                dev_name(&mdev->pdev->dev), ##arg)
 582 #define mlx4_info(mdev, format, arg...)                 \
 583         pr_info("%s %s: " format, DRV_NAME,             \
 584                 dev_name(&mdev->pdev->dev), ##arg)
 585 #define mlx4_warn(mdev, format, arg...)                 \
 586         pr_warning("%s %s: " format, DRV_NAME,          \
 587                    dev_name(&mdev->pdev->dev), ##arg)
 588
 589 #endif