?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ocfs2: Make the left masklogs compat.
[taoma-kernel.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
blob39b6f16c87fae687f8e6b28e1ed7964e92a5ee97
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/wireless.h>
38 #include <linux/firmware.h>
39 #include <linux/etherdevice.h>
40 #include <asm/unaligned.h>
41 #include <net/mac80211.h>
42
43 #include "iwl-fh.h"
44 #include "iwl-3945-fh.h"
45 #include "iwl-commands.h"
46 #include "iwl-sta.h"
47 #include "iwl-3945.h"
48 #include "iwl-eeprom.h"
49 #include "iwl-core.h"
50 #include "iwl-helpers.h"
51 #include "iwl-led.h"
52 #include "iwl-3945-led.h"
53 #include "iwl-3945-debugfs.h"
54 #include "iwl-legacy.h"
55
56 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
57 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
58 IWL_RATE_##r##M_IEEE, \
59 IWL_RATE_##ip##M_INDEX, \
60 IWL_RATE_##in##M_INDEX, \
61 IWL_RATE_##rp##M_INDEX, \
62 IWL_RATE_##rn##M_INDEX, \
63 IWL_RATE_##pp##M_INDEX, \
64 IWL_RATE_##np##M_INDEX, \
65 IWL_RATE_##r##M_INDEX_TABLE, \
66 IWL_RATE_##ip##M_INDEX_TABLE }
67
68 /*
69 * Parameter order:
70 * rate, prev rate, next rate, prev tgg rate, next tgg rate
71 *
72 * If there isn't a valid next or previous rate then INV is used which
73 * maps to IWL_RATE_INVALID
74 *
75 */
76 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
77 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
78 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
79 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
80 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
81 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
82 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
83 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
84 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
85 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
86 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
87 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
88 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
89 };
90
91 static inline u8 iwl3945_get_prev_ieee_rate(u8 rate_index)
92 {
93 u8 rate = iwl3945_rates[rate_index].prev_ieee;
94
95 if (rate == IWL_RATE_INVALID)
96 rate = rate_index;
97 return rate;
98 }
99
100 /* 1 = enable the iwl3945_disable_events() function */
101 #define IWL_EVT_DISABLE (0)
102 #define IWL_EVT_DISABLE_SIZE (1532/32)
103
104 /**
105 * iwl3945_disable_events - Disable selected events in uCode event log
106 *
107 * Disable an event by writing "1"s into "disable"
108 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
109 * Default values of 0 enable uCode events to be logged.
110 * Use for only special debugging. This function is just a placeholder as-is,
111 * you'll need to provide the special bits! ...
112 * ... and set IWL_EVT_DISABLE to 1. */
113 void iwl3945_disable_events(struct iwl_priv *priv)
114 {
115 int i;
116 u32 base; /* SRAM address of event log header */
117 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
118 u32 array_size; /* # of u32 entries in array */
119 static const u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
120 0x00000000, /* 31 - 0 Event id numbers */
121 0x00000000, /* 63 - 32 */
122 0x00000000, /* 95 - 64 */
123 0x00000000, /* 127 - 96 */
124 0x00000000, /* 159 - 128 */
125 0x00000000, /* 191 - 160 */
126 0x00000000, /* 223 - 192 */
127 0x00000000, /* 255 - 224 */
128 0x00000000, /* 287 - 256 */
129 0x00000000, /* 319 - 288 */
130 0x00000000, /* 351 - 320 */
131 0x00000000, /* 383 - 352 */
132 0x00000000, /* 415 - 384 */
133 0x00000000, /* 447 - 416 */
134 0x00000000, /* 479 - 448 */
135 0x00000000, /* 511 - 480 */
136 0x00000000, /* 543 - 512 */
137 0x00000000, /* 575 - 544 */
138 0x00000000, /* 607 - 576 */
139 0x00000000, /* 639 - 608 */
140 0x00000000, /* 671 - 640 */
141 0x00000000, /* 703 - 672 */
142 0x00000000, /* 735 - 704 */
143 0x00000000, /* 767 - 736 */
144 0x00000000, /* 799 - 768 */
145 0x00000000, /* 831 - 800 */
146 0x00000000, /* 863 - 832 */
147 0x00000000, /* 895 - 864 */
148 0x00000000, /* 927 - 896 */
149 0x00000000, /* 959 - 928 */
150 0x00000000, /* 991 - 960 */
151 0x00000000, /* 1023 - 992 */
152 0x00000000, /* 1055 - 1024 */
153 0x00000000, /* 1087 - 1056 */
154 0x00000000, /* 1119 - 1088 */
155 0x00000000, /* 1151 - 1120 */
156 0x00000000, /* 1183 - 1152 */
157 0x00000000, /* 1215 - 1184 */
158 0x00000000, /* 1247 - 1216 */
159 0x00000000, /* 1279 - 1248 */
160 0x00000000, /* 1311 - 1280 */
161 0x00000000, /* 1343 - 1312 */
162 0x00000000, /* 1375 - 1344 */
163 0x00000000, /* 1407 - 1376 */
164 0x00000000, /* 1439 - 1408 */
165 0x00000000, /* 1471 - 1440 */
166 0x00000000, /* 1503 - 1472 */
167 };
168
169 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
170 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
171 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
172 return;
173 }
174
175 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
176 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
177
178 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
179 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
180 disable_ptr);
181 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
182 iwl_write_targ_mem(priv,
183 disable_ptr + (i * sizeof(u32)),
184 evt_disable[i]);
185
186 } else {
187 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
188 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
189 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
190 disable_ptr, array_size);
191 }
192
193 }
194
195 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
196 {
197 int idx;
198
199 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
200 if (iwl3945_rates[idx].plcp == plcp)
201 return idx;
202 return -1;
203 }
204
205 #ifdef CONFIG_IWLWIFI_DEBUG
206 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
207
208 static const char *iwl3945_get_tx_fail_reason(u32 status)
209 {
210 switch (status & TX_STATUS_MSK) {
211 case TX_3945_STATUS_SUCCESS:
212 return "SUCCESS";
213 TX_STATUS_ENTRY(SHORT_LIMIT);
214 TX_STATUS_ENTRY(LONG_LIMIT);
215 TX_STATUS_ENTRY(FIFO_UNDERRUN);
216 TX_STATUS_ENTRY(MGMNT_ABORT);
217 TX_STATUS_ENTRY(NEXT_FRAG);
218 TX_STATUS_ENTRY(LIFE_EXPIRE);
219 TX_STATUS_ENTRY(DEST_PS);
220 TX_STATUS_ENTRY(ABORTED);
221 TX_STATUS_ENTRY(BT_RETRY);
222 TX_STATUS_ENTRY(STA_INVALID);
223 TX_STATUS_ENTRY(FRAG_DROPPED);
224 TX_STATUS_ENTRY(TID_DISABLE);
225 TX_STATUS_ENTRY(FRAME_FLUSHED);
226 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
227 TX_STATUS_ENTRY(TX_LOCKED);
228 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
229 }
230
231 return "UNKNOWN";
232 }
233 #else
234 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
235 {
236 return "";
237 }
238 #endif
239
240 /*
241 * get ieee prev rate from rate scale table.
242 * for A and B mode we need to overright prev
243 * value
244 */
245 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
246 {
247 int next_rate = iwl3945_get_prev_ieee_rate(rate);
248
249 switch (priv->band) {
250 case IEEE80211_BAND_5GHZ:
251 if (rate == IWL_RATE_12M_INDEX)
252 next_rate = IWL_RATE_9M_INDEX;
253 else if (rate == IWL_RATE_6M_INDEX)
254 next_rate = IWL_RATE_6M_INDEX;
255 break;
256 case IEEE80211_BAND_2GHZ:
257 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
258 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
259 if (rate == IWL_RATE_11M_INDEX)
260 next_rate = IWL_RATE_5M_INDEX;
261 }
262 break;
263
264 default:
265 break;
266 }
267
268 return next_rate;
269 }
270
271
272 /**
273 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
274 *
275 * When FW advances 'R' index, all entries between old and new 'R' index
276 * need to be reclaimed. As result, some free space forms. If there is
277 * enough free space (> low mark), wake the stack that feeds us.
278 */
279 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
280 int txq_id, int index)
281 {
282 struct iwl_tx_queue *txq = &priv->txq[txq_id];
283 struct iwl_queue *q = &txq->q;
284 struct iwl_tx_info *tx_info;
285
286 BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
287
288 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
289 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
290
291 tx_info = &txq->txb[txq->q.read_ptr];
292 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
293 tx_info->skb = NULL;
294 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
295 }
296
297 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
298 (txq_id != IWL39_CMD_QUEUE_NUM) &&
299 priv->mac80211_registered)
300 iwl_wake_queue(priv, txq);
301 }
302
303 /**
304 * iwl3945_rx_reply_tx - Handle Tx response
305 */
306 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
307 struct iwl_rx_mem_buffer *rxb)
308 {
309 struct iwl_rx_packet *pkt = rxb_addr(rxb);
310 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
311 int txq_id = SEQ_TO_QUEUE(sequence);
312 int index = SEQ_TO_INDEX(sequence);
313 struct iwl_tx_queue *txq = &priv->txq[txq_id];
314 struct ieee80211_tx_info *info;
315 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
316 u32 status = le32_to_cpu(tx_resp->status);
317 int rate_idx;
318 int fail;
319
320 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
321 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
322 "is out of range [0-%d] %d %d\n", txq_id,
323 index, txq->q.n_bd, txq->q.write_ptr,
324 txq->q.read_ptr);
325 return;
326 }
327
328 txq->time_stamp = jiffies;
329 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
330 ieee80211_tx_info_clear_status(info);
331
332 /* Fill the MRR chain with some info about on-chip retransmissions */
333 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
334 if (info->band == IEEE80211_BAND_5GHZ)
335 rate_idx -= IWL_FIRST_OFDM_RATE;
336
337 fail = tx_resp->failure_frame;
338
339 info->status.rates[0].idx = rate_idx;
340 info->status.rates[0].count = fail + 1; /* add final attempt */
341
342 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
343 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
344 IEEE80211_TX_STAT_ACK : 0;
345
346 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
347 txq_id, iwl3945_get_tx_fail_reason(status), status,
348 tx_resp->rate, tx_resp->failure_frame);
349
350 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
351 iwl3945_tx_queue_reclaim(priv, txq_id, index);
352
353 if (status & TX_ABORT_REQUIRED_MSK)
354 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
355 }
356
357
358
359 /*****************************************************************************
360 *
361 * Intel PRO/Wireless 3945ABG/BG Network Connection
362 *
363 * RX handler implementations
364 *
365 *****************************************************************************/
366 #ifdef CONFIG_IWLWIFI_DEBUGFS
367 /*
368 * based on the assumption of all statistics counter are in DWORD
369 * FIXME: This function is for debugging, do not deal with
370 * the case of counters roll-over.
371 */
372 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
373 __le32 *stats)
374 {
375 int i;
376 __le32 *prev_stats;
377 u32 *accum_stats;
378 u32 *delta, *max_delta;
379
380 prev_stats = (__le32 *)&priv->_3945.statistics;
381 accum_stats = (u32 *)&priv->_3945.accum_statistics;
382 delta = (u32 *)&priv->_3945.delta_statistics;
383 max_delta = (u32 *)&priv->_3945.max_delta;
384
385 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
386 i += sizeof(__le32), stats++, prev_stats++, delta++,
387 max_delta++, accum_stats++) {
388 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
389 *delta = (le32_to_cpu(*stats) -
390 le32_to_cpu(*prev_stats));
391 *accum_stats += *delta;
392 if (*delta > *max_delta)
393 *max_delta = *delta;
394 }
395 }
396
397 /* reset accumulative statistics for "no-counter" type statistics */
398 priv->_3945.accum_statistics.general.temperature =
399 priv->_3945.statistics.general.temperature;
400 priv->_3945.accum_statistics.general.ttl_timestamp =
401 priv->_3945.statistics.general.ttl_timestamp;
402 }
403 #endif
404
405 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
406 struct iwl_rx_mem_buffer *rxb)
407 {
408 struct iwl_rx_packet *pkt = rxb_addr(rxb);
409
410 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
411 (int)sizeof(struct iwl3945_notif_statistics),
412 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
413 #ifdef CONFIG_IWLWIFI_DEBUGFS
414 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
415 #endif
416 iwl_recover_from_statistics(priv, pkt);
417
418 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
419 }
420
421 void iwl3945_reply_statistics(struct iwl_priv *priv,
422 struct iwl_rx_mem_buffer *rxb)
423 {
424 struct iwl_rx_packet *pkt = rxb_addr(rxb);
425 __le32 *flag = (__le32 *)&pkt->u.raw;
426
427 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
428 #ifdef CONFIG_IWLWIFI_DEBUGFS
429 memset(&priv->_3945.accum_statistics, 0,
430 sizeof(struct iwl3945_notif_statistics));
431 memset(&priv->_3945.delta_statistics, 0,
432 sizeof(struct iwl3945_notif_statistics));
433 memset(&priv->_3945.max_delta, 0,
434 sizeof(struct iwl3945_notif_statistics));
435 #endif
436 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
437 }
438 iwl3945_hw_rx_statistics(priv, rxb);
439 }
440
441
442 /******************************************************************************
443 *
444 * Misc. internal state and helper functions
445 *
446 ******************************************************************************/
447
448 /* This is necessary only for a number of statistics, see the caller. */
449 static int iwl3945_is_network_packet(struct iwl_priv *priv,
450 struct ieee80211_hdr *header)
451 {
452 /* Filter incoming packets to determine if they are targeted toward
453 * this network, discarding packets coming from ourselves */
454 switch (priv->iw_mode) {
455 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
456 /* packets to our IBSS update information */
457 return !compare_ether_addr(header->addr3, priv->bssid);
458 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
459 /* packets to our IBSS update information */
460 return !compare_ether_addr(header->addr2, priv->bssid);
461 default:
462 return 1;
463 }
464 }
465
466 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
467 struct iwl_rx_mem_buffer *rxb,
468 struct ieee80211_rx_status *stats)
469 {
470 struct iwl_rx_packet *pkt = rxb_addr(rxb);
471 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
472 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
473 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
474 u16 len = le16_to_cpu(rx_hdr->len);
475 struct sk_buff *skb;
476 __le16 fc = hdr->frame_control;
477
478 /* We received data from the HW, so stop the watchdog */
479 if (unlikely(len + IWL39_RX_FRAME_SIZE >
480 PAGE_SIZE << priv->hw_params.rx_page_order)) {
481 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
482 return;
483 }
484
485 /* We only process data packets if the interface is open */
486 if (unlikely(!priv->is_open)) {
487 IWL_DEBUG_DROP_LIMIT(priv,
488 "Dropping packet while interface is not open.\n");
489 return;
490 }
491
492 skb = dev_alloc_skb(128);
493 if (!skb) {
494 IWL_ERR(priv, "dev_alloc_skb failed\n");
495 return;
496 }
497
498 if (!iwl3945_mod_params.sw_crypto)
499 iwl_set_decrypted_flag(priv,
500 (struct ieee80211_hdr *)rxb_addr(rxb),
501 le32_to_cpu(rx_end->status), stats);
502
503 skb_add_rx_frag(skb, 0, rxb->page,
504 (void *)rx_hdr->payload - (void *)pkt, len);
505
506 iwl_update_stats(priv, false, fc, len);
507 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
508
509 ieee80211_rx(priv->hw, skb);
510 priv->alloc_rxb_page--;
511 rxb->page = NULL;
512 }
513
514 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
515
516 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
517 struct iwl_rx_mem_buffer *rxb)
518 {
519 struct ieee80211_hdr *header;
520 struct ieee80211_rx_status rx_status;
521 struct iwl_rx_packet *pkt = rxb_addr(rxb);
522 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
523 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
524 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
525 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
526 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
527 u8 network_packet;
528
529 rx_status.flag = 0;
530 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
531 rx_status.freq =
532 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
533 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
534 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
535
536 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
537 if (rx_status.band == IEEE80211_BAND_5GHZ)
538 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
539
540 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
541 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
542
543 /* set the preamble flag if appropriate */
544 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
545 rx_status.flag |= RX_FLAG_SHORTPRE;
546
547 if ((unlikely(rx_stats->phy_count > 20))) {
548 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
549 rx_stats->phy_count);
550 return;
551 }
552
553 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
554 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
555 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
556 return;
557 }
558
559
560
561 /* Convert 3945's rssi indicator to dBm */
562 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
563
564 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
565 rx_status.signal, rx_stats_sig_avg,
566 rx_stats_noise_diff);
567
568 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
569
570 network_packet = iwl3945_is_network_packet(priv, header);
571
572 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
573 network_packet ? '*' : ' ',
574 le16_to_cpu(rx_hdr->channel),
575 rx_status.signal, rx_status.signal,
576 rx_status.rate_idx);
577
578 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
579
580 if (network_packet) {
581 priv->_3945.last_beacon_time =
582 le32_to_cpu(rx_end->beacon_timestamp);
583 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
584 priv->_3945.last_rx_rssi = rx_status.signal;
585 }
586
587 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
588 }
589
590 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
591 struct iwl_tx_queue *txq,
592 dma_addr_t addr, u16 len, u8 reset, u8 pad)
593 {
594 int count;
595 struct iwl_queue *q;
596 struct iwl3945_tfd *tfd, *tfd_tmp;
597
598 q = &txq->q;
599 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
600 tfd = &tfd_tmp[q->write_ptr];
601
602 if (reset)
603 memset(tfd, 0, sizeof(*tfd));
604
605 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
606
607 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
608 IWL_ERR(priv, "Error can not send more than %d chunks\n",
609 NUM_TFD_CHUNKS);
610 return -EINVAL;
611 }
612
613 tfd->tbs[count].addr = cpu_to_le32(addr);
614 tfd->tbs[count].len = cpu_to_le32(len);
615
616 count++;
617
618 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
619 TFD_CTL_PAD_SET(pad));
620
621 return 0;
622 }
623
624 /**
625 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
626 *
627 * Does NOT advance any indexes
628 */
629 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
630 {
631 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
632 int index = txq->q.read_ptr;
633 struct iwl3945_tfd *tfd = &tfd_tmp[index];
634 struct pci_dev *dev = priv->pci_dev;
635 int i;
636 int counter;
637
638 /* sanity check */
639 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
640 if (counter > NUM_TFD_CHUNKS) {
641 IWL_ERR(priv, "Too many chunks: %i\n", counter);
642 /* @todo issue fatal error, it is quite serious situation */
643 return;
644 }
645
646 /* Unmap tx_cmd */
647 if (counter)
648 pci_unmap_single(dev,
649 dma_unmap_addr(&txq->meta[index], mapping),
650 dma_unmap_len(&txq->meta[index], len),
651 PCI_DMA_TODEVICE);
652
653 /* unmap chunks if any */
654
655 for (i = 1; i < counter; i++)
656 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
657 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
658
659 /* free SKB */
660 if (txq->txb) {
661 struct sk_buff *skb;
662
663 skb = txq->txb[txq->q.read_ptr].skb;
664
665 /* can be called from irqs-disabled context */
666 if (skb) {
667 dev_kfree_skb_any(skb);
668 txq->txb[txq->q.read_ptr].skb = NULL;
669 }
670 }
671 }
672
673 /**
674 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
675 *
676 */
677 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
678 struct iwl_device_cmd *cmd,
679 struct ieee80211_tx_info *info,
680 struct ieee80211_hdr *hdr,
681 int sta_id, int tx_id)
682 {
683 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
684 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
685 u16 rate_mask;
686 int rate;
687 u8 rts_retry_limit;
688 u8 data_retry_limit;
689 __le32 tx_flags;
690 __le16 fc = hdr->frame_control;
691 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
692
693 rate = iwl3945_rates[rate_index].plcp;
694 tx_flags = tx_cmd->tx_flags;
695
696 /* We need to figure out how to get the sta->supp_rates while
697 * in this running context */
698 rate_mask = IWL_RATES_MASK;
699
700
701 /* Set retry limit on DATA packets and Probe Responses*/
702 if (ieee80211_is_probe_resp(fc))
703 data_retry_limit = 3;
704 else
705 data_retry_limit = IWL_DEFAULT_TX_RETRY;
706 tx_cmd->data_retry_limit = data_retry_limit;
707
708 if (tx_id >= IWL39_CMD_QUEUE_NUM)
709 rts_retry_limit = 3;
710 else
711 rts_retry_limit = 7;
712
713 if (data_retry_limit < rts_retry_limit)
714 rts_retry_limit = data_retry_limit;
715 tx_cmd->rts_retry_limit = rts_retry_limit;
716
717 tx_cmd->rate = rate;
718 tx_cmd->tx_flags = tx_flags;
719
720 /* OFDM */
721 tx_cmd->supp_rates[0] =
722 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
723
724 /* CCK */
725 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
726
727 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
728 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
729 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
730 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
731 }
732
733 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
734 {
735 unsigned long flags_spin;
736 struct iwl_station_entry *station;
737
738 if (sta_id == IWL_INVALID_STATION)
739 return IWL_INVALID_STATION;
740
741 spin_lock_irqsave(&priv->sta_lock, flags_spin);
742 station = &priv->stations[sta_id];
743
744 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
745 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
746 station->sta.mode = STA_CONTROL_MODIFY_MSK;
747 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
748 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
749
750 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
751 sta_id, tx_rate);
752 return sta_id;
753 }
754
755 static void iwl3945_set_pwr_vmain(struct iwl_priv *priv)
756 {
757 /*
758 * (for documentation purposes)
759 * to set power to V_AUX, do
760
761 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
762 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
763 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
764 ~APMG_PS_CTRL_MSK_PWR_SRC);
765
766 iwl_poll_bit(priv, CSR_GPIO_IN,
767 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
768 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
769 }
770 */
771
772 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
773 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
774 ~APMG_PS_CTRL_MSK_PWR_SRC);
775
776 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
777 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
778 }
779
780 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
781 {
782 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
783 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
784 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
785 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
786 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
787 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
788 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
789 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
790 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
791 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
792 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
793 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
794
795 /* fake read to flush all prev I/O */
796 iwl_read_direct32(priv, FH39_RSSR_CTRL);
797
798 return 0;
799 }
800
801 static int iwl3945_tx_reset(struct iwl_priv *priv)
802 {
803
804 /* bypass mode */
805 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
806
807 /* RA 0 is active */
808 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
809
810 /* all 6 fifo are active */
811 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
812
813 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
814 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
815 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
816 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
817
818 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
819 priv->_3945.shared_phys);
820
821 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
822 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
823 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
824 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
825 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
826 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
827 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
828 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
829
830
831 return 0;
832 }
833
834 /**
835 * iwl3945_txq_ctx_reset - Reset TX queue context
836 *
837 * Destroys all DMA structures and initialize them again
838 */
839 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
840 {
841 int rc;
842 int txq_id, slots_num;
843
844 iwl3945_hw_txq_ctx_free(priv);
845
846 /* allocate tx queue structure */
847 rc = iwl_alloc_txq_mem(priv);
848 if (rc)
849 return rc;
850
851 /* Tx CMD queue */
852 rc = iwl3945_tx_reset(priv);
853 if (rc)
854 goto error;
855
856 /* Tx queue(s) */
857 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
858 slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
859 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
860 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
861 txq_id);
862 if (rc) {
863 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
864 goto error;
865 }
866 }
867
868 return rc;
869
870 error:
871 iwl3945_hw_txq_ctx_free(priv);
872 return rc;
873 }
874
875
876 /*
877 * Start up 3945's basic functionality after it has been reset
878 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
879 * NOTE: This does not load uCode nor start the embedded processor
880 */
881 static int iwl3945_apm_init(struct iwl_priv *priv)
882 {
883 int ret = iwl_apm_init(priv);
884
885 /* Clear APMG (NIC's internal power management) interrupts */
886 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
887 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
888
889 /* Reset radio chip */
890 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
891 udelay(5);
892 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
893
894 return ret;
895 }
896
897 static void iwl3945_nic_config(struct iwl_priv *priv)
898 {
899 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
900 unsigned long flags;
901 u8 rev_id = 0;
902
903 spin_lock_irqsave(&priv->lock, flags);
904
905 /* Determine HW type */
906 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
907
908 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
909
910 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
911 IWL_DEBUG_INFO(priv, "RTP type\n");
912 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
913 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
914 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
915 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
916 } else {
917 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
918 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
919 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
920 }
921
922 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
923 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
924 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
925 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
926 } else
927 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
928
929 if ((eeprom->board_revision & 0xF0) == 0xD0) {
930 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
931 eeprom->board_revision);
932 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
933 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
934 } else {
935 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
936 eeprom->board_revision);
937 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
938 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
939 }
940
941 if (eeprom->almgor_m_version <= 1) {
942 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
943 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
944 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
945 eeprom->almgor_m_version);
946 } else {
947 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
948 eeprom->almgor_m_version);
949 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
950 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
951 }
952 spin_unlock_irqrestore(&priv->lock, flags);
953
954 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
955 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
956
957 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
958 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
959 }
960
961 int iwl3945_hw_nic_init(struct iwl_priv *priv)
962 {
963 int rc;
964 unsigned long flags;
965 struct iwl_rx_queue *rxq = &priv->rxq;
966
967 spin_lock_irqsave(&priv->lock, flags);
968 priv->cfg->ops->lib->apm_ops.init(priv);
969 spin_unlock_irqrestore(&priv->lock, flags);
970
971 iwl3945_set_pwr_vmain(priv);
972
973 priv->cfg->ops->lib->apm_ops.config(priv);
974
975 /* Allocate the RX queue, or reset if it is already allocated */
976 if (!rxq->bd) {
977 rc = iwl_rx_queue_alloc(priv);
978 if (rc) {
979 IWL_ERR(priv, "Unable to initialize Rx queue\n");
980 return -ENOMEM;
981 }
982 } else
983 iwl3945_rx_queue_reset(priv, rxq);
984
985 iwl3945_rx_replenish(priv);
986
987 iwl3945_rx_init(priv, rxq);
988
989
990 /* Look at using this instead:
991 rxq->need_update = 1;
992 iwl_rx_queue_update_write_ptr(priv, rxq);
993 */
994
995 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
996
997 rc = iwl3945_txq_ctx_reset(priv);
998 if (rc)
999 return rc;
1000
1001 set_bit(STATUS_INIT, &priv->status);
1002
1003 return 0;
1004 }
1005
1006 /**
1007 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1008 *
1009 * Destroy all TX DMA queues and structures
1010 */
1011 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1012 {
1013 int txq_id;
1014
1015 /* Tx queues */
1016 if (priv->txq)
1017 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1018 txq_id++)
1019 if (txq_id == IWL39_CMD_QUEUE_NUM)
1020 iwl_cmd_queue_free(priv);
1021 else
1022 iwl_tx_queue_free(priv, txq_id);
1023
1024 /* free tx queue structure */
1025 iwl_free_txq_mem(priv);
1026 }
1027
1028 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1029 {
1030 int txq_id;
1031
1032 /* stop SCD */
1033 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1034 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1035
1036 /* reset TFD queues */
1037 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1038 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1039 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1040 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1041 1000);
1042 }
1043
1044 iwl3945_hw_txq_ctx_free(priv);
1045 }
1046
1047 /**
1048 * iwl3945_hw_reg_adjust_power_by_temp
1049 * return index delta into power gain settings table
1050 */
1051 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1052 {
1053 return (new_reading - old_reading) * (-11) / 100;
1054 }
1055
1056 /**
1057 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1058 */
1059 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1060 {
1061 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1062 }
1063
1064 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1065 {
1066 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1067 }
1068
1069 /**
1070 * iwl3945_hw_reg_txpower_get_temperature
1071 * get the current temperature by reading from NIC
1072 */
1073 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1074 {
1075 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1076 int temperature;
1077
1078 temperature = iwl3945_hw_get_temperature(priv);
1079
1080 /* driver's okay range is -260 to +25.
1081 * human readable okay range is 0 to +285 */
1082 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1083
1084 /* handle insane temp reading */
1085 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1086 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1087
1088 /* if really really hot(?),
1089 * substitute the 3rd band/group's temp measured at factory */
1090 if (priv->last_temperature > 100)
1091 temperature = eeprom->groups[2].temperature;
1092 else /* else use most recent "sane" value from driver */
1093 temperature = priv->last_temperature;
1094 }
1095
1096 return temperature; /* raw, not "human readable" */
1097 }
1098
1099 /* Adjust Txpower only if temperature variance is greater than threshold.
1100 *
1101 * Both are lower than older versions' 9 degrees */
1102 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1103
1104 /**
1105 * is_temp_calib_needed - determines if new calibration is needed
1106 *
1107 * records new temperature in tx_mgr->temperature.
1108 * replaces tx_mgr->last_temperature *only* if calib needed
1109 * (assumes caller will actually do the calibration!). */
1110 static int is_temp_calib_needed(struct iwl_priv *priv)
1111 {
1112 int temp_diff;
1113
1114 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1115 temp_diff = priv->temperature - priv->last_temperature;
1116
1117 /* get absolute value */
1118 if (temp_diff < 0) {
1119 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1120 temp_diff = -temp_diff;
1121 } else if (temp_diff == 0)
1122 IWL_DEBUG_POWER(priv, "Same temp,\n");
1123 else
1124 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1125
1126 /* if we don't need calibration, *don't* update last_temperature */
1127 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1128 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1129 return 0;
1130 }
1131
1132 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1133
1134 /* assume that caller will actually do calib ...
1135 * update the "last temperature" value */
1136 priv->last_temperature = priv->temperature;
1137 return 1;
1138 }
1139
1140 #define IWL_MAX_GAIN_ENTRIES 78
1141 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1142 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1143
1144 /* radio and DSP power table, each step is 1/2 dB.
1145 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1146 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1147 {
1148 {251, 127}, /* 2.4 GHz, highest power */
1149 {251, 127},
1150 {251, 127},
1151 {251, 127},
1152 {251, 125},
1153 {251, 110},
1154 {251, 105},
1155 {251, 98},
1156 {187, 125},
1157 {187, 115},
1158 {187, 108},
1159 {187, 99},
1160 {243, 119},
1161 {243, 111},
1162 {243, 105},
1163 {243, 97},
1164 {243, 92},
1165 {211, 106},
1166 {211, 100},
1167 {179, 120},
1168 {179, 113},
1169 {179, 107},
1170 {147, 125},
1171 {147, 119},
1172 {147, 112},
1173 {147, 106},
1174 {147, 101},
1175 {147, 97},
1176 {147, 91},
1177 {115, 107},
1178 {235, 121},
1179 {235, 115},
1180 {235, 109},
1181 {203, 127},
1182 {203, 121},
1183 {203, 115},
1184 {203, 108},
1185 {203, 102},
1186 {203, 96},
1187 {203, 92},
1188 {171, 110},
1189 {171, 104},
1190 {171, 98},
1191 {139, 116},
1192 {227, 125},
1193 {227, 119},
1194 {227, 113},
1195 {227, 107},
1196 {227, 101},
1197 {227, 96},
1198 {195, 113},
1199 {195, 106},
1200 {195, 102},
1201 {195, 95},
1202 {163, 113},
1203 {163, 106},
1204 {163, 102},
1205 {163, 95},
1206 {131, 113},
1207 {131, 106},
1208 {131, 102},
1209 {131, 95},
1210 {99, 113},
1211 {99, 106},
1212 {99, 102},
1213 {99, 95},
1214 {67, 113},
1215 {67, 106},
1216 {67, 102},
1217 {67, 95},
1218 {35, 113},
1219 {35, 106},
1220 {35, 102},
1221 {35, 95},
1222 {3, 113},
1223 {3, 106},
1224 {3, 102},
1225 {3, 95} }, /* 2.4 GHz, lowest power */
1226 {
1227 {251, 127}, /* 5.x GHz, highest power */
1228 {251, 120},
1229 {251, 114},
1230 {219, 119},
1231 {219, 101},
1232 {187, 113},
1233 {187, 102},
1234 {155, 114},
1235 {155, 103},
1236 {123, 117},
1237 {123, 107},
1238 {123, 99},
1239 {123, 92},
1240 {91, 108},
1241 {59, 125},
1242 {59, 118},
1243 {59, 109},
1244 {59, 102},
1245 {59, 96},
1246 {59, 90},
1247 {27, 104},
1248 {27, 98},
1249 {27, 92},
1250 {115, 118},
1251 {115, 111},
1252 {115, 104},
1253 {83, 126},
1254 {83, 121},
1255 {83, 113},
1256 {83, 105},
1257 {83, 99},
1258 {51, 118},
1259 {51, 111},
1260 {51, 104},
1261 {51, 98},
1262 {19, 116},
1263 {19, 109},
1264 {19, 102},
1265 {19, 98},
1266 {19, 93},
1267 {171, 113},
1268 {171, 107},
1269 {171, 99},
1270 {139, 120},
1271 {139, 113},
1272 {139, 107},
1273 {139, 99},
1274 {107, 120},
1275 {107, 113},
1276 {107, 107},
1277 {107, 99},
1278 {75, 120},
1279 {75, 113},
1280 {75, 107},
1281 {75, 99},
1282 {43, 120},
1283 {43, 113},
1284 {43, 107},
1285 {43, 99},
1286 {11, 120},
1287 {11, 113},
1288 {11, 107},
1289 {11, 99},
1290 {131, 107},
1291 {131, 99},
1292 {99, 120},
1293 {99, 113},
1294 {99, 107},
1295 {99, 99},
1296 {67, 120},
1297 {67, 113},
1298 {67, 107},
1299 {67, 99},
1300 {35, 120},
1301 {35, 113},
1302 {35, 107},
1303 {35, 99},
1304 {3, 120} } /* 5.x GHz, lowest power */
1305 };
1306
1307 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1308 {
1309 if (index < 0)
1310 return 0;
1311 if (index >= IWL_MAX_GAIN_ENTRIES)
1312 return IWL_MAX_GAIN_ENTRIES - 1;
1313 return (u8) index;
1314 }
1315
1316 /* Kick off thermal recalibration check every 60 seconds */
1317 #define REG_RECALIB_PERIOD (60)
1318
1319 /**
1320 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1321 *
1322 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1323 * or 6 Mbit (OFDM) rates.
1324 */
1325 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1326 s32 rate_index, const s8 *clip_pwrs,
1327 struct iwl_channel_info *ch_info,
1328 int band_index)
1329 {
1330 struct iwl3945_scan_power_info *scan_power_info;
1331 s8 power;
1332 u8 power_index;
1333
1334 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1335
1336 /* use this channel group's 6Mbit clipping/saturation pwr,
1337 * but cap at regulatory scan power restriction (set during init
1338 * based on eeprom channel data) for this channel. */
1339 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1340
1341 /* further limit to user's max power preference.
1342 * FIXME: Other spectrum management power limitations do not
1343 * seem to apply?? */
1344 power = min(power, priv->tx_power_user_lmt);
1345 scan_power_info->requested_power = power;
1346
1347 /* find difference between new scan *power* and current "normal"
1348 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1349 * current "normal" temperature-compensated Tx power *index* for
1350 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1351 * *index*. */
1352 power_index = ch_info->power_info[rate_index].power_table_index
1353 - (power - ch_info->power_info
1354 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1355
1356 /* store reference index that we use when adjusting *all* scan
1357 * powers. So we can accommodate user (all channel) or spectrum
1358 * management (single channel) power changes "between" temperature
1359 * feedback compensation procedures.
1360 * don't force fit this reference index into gain table; it may be a
1361 * negative number. This will help avoid errors when we're at
1362 * the lower bounds (highest gains, for warmest temperatures)
1363 * of the table. */
1364
1365 /* don't exceed table bounds for "real" setting */
1366 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1367
1368 scan_power_info->power_table_index = power_index;
1369 scan_power_info->tpc.tx_gain =
1370 power_gain_table[band_index][power_index].tx_gain;
1371 scan_power_info->tpc.dsp_atten =
1372 power_gain_table[band_index][power_index].dsp_atten;
1373 }
1374
1375 /**
1376 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1377 *
1378 * Configures power settings for all rates for the current channel,
1379 * using values from channel info struct, and send to NIC
1380 */
1381 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1382 {
1383 int rate_idx, i;
1384 const struct iwl_channel_info *ch_info = NULL;
1385 struct iwl3945_txpowertable_cmd txpower = {
1386 .channel = priv->contexts[IWL_RXON_CTX_BSS].active.channel,
1387 };
1388 u16 chan;
1389
1390 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
1391 "TX Power requested while scanning!\n"))
1392 return -EAGAIN;
1393
1394 chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
1395
1396 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1397 ch_info = iwl_get_channel_info(priv, priv->band, chan);
1398 if (!ch_info) {
1399 IWL_ERR(priv,
1400 "Failed to get channel info for channel %d [%d]\n",
1401 chan, priv->band);
1402 return -EINVAL;
1403 }
1404
1405 if (!is_channel_valid(ch_info)) {
1406 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1407 "non-Tx channel.\n");
1408 return 0;
1409 }
1410
1411 /* fill cmd with power settings for all rates for current channel */
1412 /* Fill OFDM rate */
1413 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1414 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1415
1416 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1417 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1418
1419 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1420 le16_to_cpu(txpower.channel),
1421 txpower.band,
1422 txpower.power[i].tpc.tx_gain,
1423 txpower.power[i].tpc.dsp_atten,
1424 txpower.power[i].rate);
1425 }
1426 /* Fill CCK rates */
1427 for (rate_idx = IWL_FIRST_CCK_RATE;
1428 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1429 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1430 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1431
1432 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1433 le16_to_cpu(txpower.channel),
1434 txpower.band,
1435 txpower.power[i].tpc.tx_gain,
1436 txpower.power[i].tpc.dsp_atten,
1437 txpower.power[i].rate);
1438 }
1439
1440 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1441 sizeof(struct iwl3945_txpowertable_cmd),
1442 &txpower);
1443
1444 }
1445
1446 /**
1447 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1448 * @ch_info: Channel to update. Uses power_info.requested_power.
1449 *
1450 * Replace requested_power and base_power_index ch_info fields for
1451 * one channel.
1452 *
1453 * Called if user or spectrum management changes power preferences.
1454 * Takes into account h/w and modulation limitations (clip power).
1455 *
1456 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1457 *
1458 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1459 * properly fill out the scan powers, and actual h/w gain settings,
1460 * and send changes to NIC
1461 */
1462 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1463 struct iwl_channel_info *ch_info)
1464 {
1465 struct iwl3945_channel_power_info *power_info;
1466 int power_changed = 0;
1467 int i;
1468 const s8 *clip_pwrs;
1469 int power;
1470
1471 /* Get this chnlgrp's rate-to-max/clip-powers table */
1472 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1473
1474 /* Get this channel's rate-to-current-power settings table */
1475 power_info = ch_info->power_info;
1476
1477 /* update OFDM Txpower settings */
1478 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1479 i++, ++power_info) {
1480 int delta_idx;
1481
1482 /* limit new power to be no more than h/w capability */
1483 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1484 if (power == power_info->requested_power)
1485 continue;
1486
1487 /* find difference between old and new requested powers,
1488 * update base (non-temp-compensated) power index */
1489 delta_idx = (power - power_info->requested_power) * 2;
1490 power_info->base_power_index -= delta_idx;
1491
1492 /* save new requested power value */
1493 power_info->requested_power = power;
1494
1495 power_changed = 1;
1496 }
1497
1498 /* update CCK Txpower settings, based on OFDM 12M setting ...
1499 * ... all CCK power settings for a given channel are the *same*. */
1500 if (power_changed) {
1501 power =
1502 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1503 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1504
1505 /* do all CCK rates' iwl3945_channel_power_info structures */
1506 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1507 power_info->requested_power = power;
1508 power_info->base_power_index =
1509 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1510 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1511 ++power_info;
1512 }
1513 }
1514
1515 return 0;
1516 }
1517
1518 /**
1519 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1520 *
1521 * NOTE: Returned power limit may be less (but not more) than requested,
1522 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1523 * (no consideration for h/w clipping limitations).
1524 */
1525 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1526 {
1527 s8 max_power;
1528
1529 #if 0
1530 /* if we're using TGd limits, use lower of TGd or EEPROM */
1531 if (ch_info->tgd_data.max_power != 0)
1532 max_power = min(ch_info->tgd_data.max_power,
1533 ch_info->eeprom.max_power_avg);
1534
1535 /* else just use EEPROM limits */
1536 else
1537 #endif
1538 max_power = ch_info->eeprom.max_power_avg;
1539
1540 return min(max_power, ch_info->max_power_avg);
1541 }
1542
1543 /**
1544 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1545 *
1546 * Compensate txpower settings of *all* channels for temperature.
1547 * This only accounts for the difference between current temperature
1548 * and the factory calibration temperatures, and bases the new settings
1549 * on the channel's base_power_index.
1550 *
1551 * If RxOn is "associated", this sends the new Txpower to NIC!
1552 */
1553 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1554 {
1555 struct iwl_channel_info *ch_info = NULL;
1556 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1557 int delta_index;
1558 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1559 u8 a_band;
1560 u8 rate_index;
1561 u8 scan_tbl_index;
1562 u8 i;
1563 int ref_temp;
1564 int temperature = priv->temperature;
1565
1566 if (priv->disable_tx_power_cal ||
1567 test_bit(STATUS_SCANNING, &priv->status)) {
1568 /* do not perform tx power calibration */
1569 return 0;
1570 }
1571 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1572 for (i = 0; i < priv->channel_count; i++) {
1573 ch_info = &priv->channel_info[i];
1574 a_band = is_channel_a_band(ch_info);
1575
1576 /* Get this chnlgrp's factory calibration temperature */
1577 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1578 temperature;
1579
1580 /* get power index adjustment based on current and factory
1581 * temps */
1582 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1583 ref_temp);
1584
1585 /* set tx power value for all rates, OFDM and CCK */
1586 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1587 rate_index++) {
1588 int power_idx =
1589 ch_info->power_info[rate_index].base_power_index;
1590
1591 /* temperature compensate */
1592 power_idx += delta_index;
1593
1594 /* stay within table range */
1595 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1596 ch_info->power_info[rate_index].
1597 power_table_index = (u8) power_idx;
1598 ch_info->power_info[rate_index].tpc =
1599 power_gain_table[a_band][power_idx];
1600 }
1601
1602 /* Get this chnlgrp's rate-to-max/clip-powers table */
1603 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1604
1605 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1606 for (scan_tbl_index = 0;
1607 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1608 s32 actual_index = (scan_tbl_index == 0) ?
1609 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1610 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1611 actual_index, clip_pwrs,
1612 ch_info, a_band);
1613 }
1614 }
1615
1616 /* send Txpower command for current channel to ucode */
1617 return priv->cfg->ops->lib->send_tx_power(priv);
1618 }
1619
1620 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1621 {
1622 struct iwl_channel_info *ch_info;
1623 s8 max_power;
1624 u8 a_band;
1625 u8 i;
1626
1627 if (priv->tx_power_user_lmt == power) {
1628 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1629 "limit: %ddBm.\n", power);
1630 return 0;
1631 }
1632
1633 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1634 priv->tx_power_user_lmt = power;
1635
1636 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1637
1638 for (i = 0; i < priv->channel_count; i++) {
1639 ch_info = &priv->channel_info[i];
1640 a_band = is_channel_a_band(ch_info);
1641
1642 /* find minimum power of all user and regulatory constraints
1643 * (does not consider h/w clipping limitations) */
1644 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1645 max_power = min(power, max_power);
1646 if (max_power != ch_info->curr_txpow) {
1647 ch_info->curr_txpow = max_power;
1648
1649 /* this considers the h/w clipping limitations */
1650 iwl3945_hw_reg_set_new_power(priv, ch_info);
1651 }
1652 }
1653
1654 /* update txpower settings for all channels,
1655 * send to NIC if associated. */
1656 is_temp_calib_needed(priv);
1657 iwl3945_hw_reg_comp_txpower_temp(priv);
1658
1659 return 0;
1660 }
1661
1662 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv,
1663 struct iwl_rxon_context *ctx)
1664 {
1665 int rc = 0;
1666 struct iwl_rx_packet *pkt;
1667 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1668 struct iwl_host_cmd cmd = {
1669 .id = REPLY_RXON_ASSOC,
1670 .len = sizeof(rxon_assoc),
1671 .flags = CMD_WANT_SKB,
1672 .data = &rxon_assoc,
1673 };
1674 const struct iwl_rxon_cmd *rxon1 = &ctx->staging;
1675 const struct iwl_rxon_cmd *rxon2 = &ctx->active;
1676
1677 if ((rxon1->flags == rxon2->flags) &&
1678 (rxon1->filter_flags == rxon2->filter_flags) &&
1679 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1680 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1681 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1682 return 0;
1683 }
1684
1685 rxon_assoc.flags = ctx->staging.flags;
1686 rxon_assoc.filter_flags = ctx->staging.filter_flags;
1687 rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1688 rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1689 rxon_assoc.reserved = 0;
1690
1691 rc = iwl_send_cmd_sync(priv, &cmd);
1692 if (rc)
1693 return rc;
1694
1695 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1696 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1697 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1698 rc = -EIO;
1699 }
1700
1701 iwl_free_pages(priv, cmd.reply_page);
1702
1703 return rc;
1704 }
1705
1706 /**
1707 * iwl3945_commit_rxon - commit staging_rxon to hardware
1708 *
1709 * The RXON command in staging_rxon is committed to the hardware and
1710 * the active_rxon structure is updated with the new data. This
1711 * function correctly transitions out of the RXON_ASSOC_MSK state if
1712 * a HW tune is required based on the RXON structure changes.
1713 */
1714 int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1715 {
1716 /* cast away the const for active_rxon in this function */
1717 struct iwl3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1718 struct iwl3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1719 int rc = 0;
1720 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1721
1722 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1723 return -EINVAL;
1724
1725 if (!iwl_is_alive(priv))
1726 return -1;
1727
1728 /* always get timestamp with Rx frame */
1729 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1730
1731 /* select antenna */
1732 staging_rxon->flags &=
1733 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1734 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1735
1736 rc = iwl_check_rxon_cmd(priv, ctx);
1737 if (rc) {
1738 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1739 return -EINVAL;
1740 }
1741
1742 /* If we don't need to send a full RXON, we can use
1743 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1744 * and other flags for the current radio configuration. */
1745 if (!iwl_full_rxon_required(priv, &priv->contexts[IWL_RXON_CTX_BSS])) {
1746 rc = iwl_send_rxon_assoc(priv,
1747 &priv->contexts[IWL_RXON_CTX_BSS]);
1748 if (rc) {
1749 IWL_ERR(priv, "Error setting RXON_ASSOC "
1750 "configuration (%d).\n", rc);
1751 return rc;
1752 }
1753
1754 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1755
1756 return 0;
1757 }
1758
1759 /* If we are currently associated and the new config requires
1760 * an RXON_ASSOC and the new config wants the associated mask enabled,
1761 * we must clear the associated from the active configuration
1762 * before we apply the new config */
1763 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS) && new_assoc) {
1764 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1765 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1766
1767 /*
1768 * reserved4 and 5 could have been filled by the iwlcore code.
1769 * Let's clear them before pushing to the 3945.
1770 */
1771 active_rxon->reserved4 = 0;
1772 active_rxon->reserved5 = 0;
1773 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1774 sizeof(struct iwl3945_rxon_cmd),
1775 &priv->contexts[IWL_RXON_CTX_BSS].active);
1776
1777 /* If the mask clearing failed then we set
1778 * active_rxon back to what it was previously */
1779 if (rc) {
1780 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1781 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1782 "configuration (%d).\n", rc);
1783 return rc;
1784 }
1785 iwl_clear_ucode_stations(priv,
1786 &priv->contexts[IWL_RXON_CTX_BSS]);
1787 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1788 }
1789
1790 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1791 "* with%s RXON_FILTER_ASSOC_MSK\n"
1792 "* channel = %d\n"
1793 "* bssid = %pM\n",
1794 (new_assoc ? "" : "out"),
1795 le16_to_cpu(staging_rxon->channel),
1796 staging_rxon->bssid_addr);
1797
1798 /*
1799 * reserved4 and 5 could have been filled by the iwlcore code.
1800 * Let's clear them before pushing to the 3945.
1801 */
1802 staging_rxon->reserved4 = 0;
1803 staging_rxon->reserved5 = 0;
1804
1805 iwl_set_rxon_hwcrypto(priv, ctx, !iwl3945_mod_params.sw_crypto);
1806
1807 /* Apply the new configuration */
1808 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1809 sizeof(struct iwl3945_rxon_cmd),
1810 staging_rxon);
1811 if (rc) {
1812 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1813 return rc;
1814 }
1815
1816 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1817
1818 if (!new_assoc) {
1819 iwl_clear_ucode_stations(priv,
1820 &priv->contexts[IWL_RXON_CTX_BSS]);
1821 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1822 }
1823
1824 /* If we issue a new RXON command which required a tune then we must
1825 * send a new TXPOWER command or we won't be able to Tx any frames */
1826 rc = priv->cfg->ops->lib->send_tx_power(priv);
1827 if (rc) {
1828 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1829 return rc;
1830 }
1831
1832 /* Init the hardware's rate fallback order based on the band */
1833 rc = iwl3945_init_hw_rate_table(priv);
1834 if (rc) {
1835 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1836 return -EIO;
1837 }
1838
1839 return 0;
1840 }
1841
1842 /**
1843 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1844 *
1845 * -- reset periodic timer
1846 * -- see if temp has changed enough to warrant re-calibration ... if so:
1847 * -- correct coeffs for temp (can reset temp timer)
1848 * -- save this temp as "last",
1849 * -- send new set of gain settings to NIC
1850 * NOTE: This should continue working, even when we're not associated,
1851 * so we can keep our internal table of scan powers current. */
1852 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1853 {
1854 /* This will kick in the "brute force"
1855 * iwl3945_hw_reg_comp_txpower_temp() below */
1856 if (!is_temp_calib_needed(priv))
1857 goto reschedule;
1858
1859 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1860 * This is based *only* on current temperature,
1861 * ignoring any previous power measurements */
1862 iwl3945_hw_reg_comp_txpower_temp(priv);
1863
1864 reschedule:
1865 queue_delayed_work(priv->workqueue,
1866 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1867 }
1868
1869 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1870 {
1871 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1872 _3945.thermal_periodic.work);
1873
1874 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1875 return;
1876
1877 mutex_lock(&priv->mutex);
1878 iwl3945_reg_txpower_periodic(priv);
1879 mutex_unlock(&priv->mutex);
1880 }
1881
1882 /**
1883 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1884 * for the channel.
1885 *
1886 * This function is used when initializing channel-info structs.
1887 *
1888 * NOTE: These channel groups do *NOT* match the bands above!
1889 * These channel groups are based on factory-tested channels;
1890 * on A-band, EEPROM's "group frequency" entries represent the top
1891 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1892 */
1893 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1894 const struct iwl_channel_info *ch_info)
1895 {
1896 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1897 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1898 u8 group;
1899 u16 group_index = 0; /* based on factory calib frequencies */
1900 u8 grp_channel;
1901
1902 /* Find the group index for the channel ... don't use index 1(?) */
1903 if (is_channel_a_band(ch_info)) {
1904 for (group = 1; group < 5; group++) {
1905 grp_channel = ch_grp[group].group_channel;
1906 if (ch_info->channel <= grp_channel) {
1907 group_index = group;
1908 break;
1909 }
1910 }
1911 /* group 4 has a few channels *above* its factory cal freq */
1912 if (group == 5)
1913 group_index = 4;
1914 } else
1915 group_index = 0; /* 2.4 GHz, group 0 */
1916
1917 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1918 group_index);
1919 return group_index;
1920 }
1921
1922 /**
1923 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1924 *
1925 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1926 * into radio/DSP gain settings table for requested power.
1927 */
1928 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1929 s8 requested_power,
1930 s32 setting_index, s32 *new_index)
1931 {
1932 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1933 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1934 s32 index0, index1;
1935 s32 power = 2 * requested_power;
1936 s32 i;
1937 const struct iwl3945_eeprom_txpower_sample *samples;
1938 s32 gains0, gains1;
1939 s32 res;
1940 s32 denominator;
1941
1942 chnl_grp = &eeprom->groups[setting_index];
1943 samples = chnl_grp->samples;
1944 for (i = 0; i < 5; i++) {
1945 if (power == samples[i].power) {
1946 *new_index = samples[i].gain_index;
1947 return 0;
1948 }
1949 }
1950
1951 if (power > samples[1].power) {
1952 index0 = 0;
1953 index1 = 1;
1954 } else if (power > samples[2].power) {
1955 index0 = 1;
1956 index1 = 2;
1957 } else if (power > samples[3].power) {
1958 index0 = 2;
1959 index1 = 3;
1960 } else {
1961 index0 = 3;
1962 index1 = 4;
1963 }
1964
1965 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
1966 if (denominator == 0)
1967 return -EINVAL;
1968 gains0 = (s32) samples[index0].gain_index * (1 << 19);
1969 gains1 = (s32) samples[index1].gain_index * (1 << 19);
1970 res = gains0 + (gains1 - gains0) *
1971 ((s32) power - (s32) samples[index0].power) / denominator +
1972 (1 << 18);
1973 *new_index = res >> 19;
1974 return 0;
1975 }
1976
1977 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
1978 {
1979 u32 i;
1980 s32 rate_index;
1981 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1982 const struct iwl3945_eeprom_txpower_group *group;
1983
1984 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
1985
1986 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
1987 s8 *clip_pwrs; /* table of power levels for each rate */
1988 s8 satur_pwr; /* saturation power for each chnl group */
1989 group = &eeprom->groups[i];
1990
1991 /* sanity check on factory saturation power value */
1992 if (group->saturation_power < 40) {
1993 IWL_WARN(priv, "Error: saturation power is %d, "
1994 "less than minimum expected 40\n",
1995 group->saturation_power);
1996 return;
1997 }
1998
1999 /*
2000 * Derive requested power levels for each rate, based on
2001 * hardware capabilities (saturation power for band).
2002 * Basic value is 3dB down from saturation, with further
2003 * power reductions for highest 3 data rates. These
2004 * backoffs provide headroom for high rate modulation
2005 * power peaks, without too much distortion (clipping).
2006 */
2007 /* we'll fill in this array with h/w max power levels */
2008 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2009
2010 /* divide factory saturation power by 2 to find -3dB level */
2011 satur_pwr = (s8) (group->saturation_power >> 1);
2012
2013 /* fill in channel group's nominal powers for each rate */
2014 for (rate_index = 0;
2015 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2016 switch (rate_index) {
2017 case IWL_RATE_36M_INDEX_TABLE:
2018 if (i == 0) /* B/G */
2019 *clip_pwrs = satur_pwr;
2020 else /* A */
2021 *clip_pwrs = satur_pwr - 5;
2022 break;
2023 case IWL_RATE_48M_INDEX_TABLE:
2024 if (i == 0)
2025 *clip_pwrs = satur_pwr - 7;
2026 else
2027 *clip_pwrs = satur_pwr - 10;
2028 break;
2029 case IWL_RATE_54M_INDEX_TABLE:
2030 if (i == 0)
2031 *clip_pwrs = satur_pwr - 9;
2032 else
2033 *clip_pwrs = satur_pwr - 12;
2034 break;
2035 default:
2036 *clip_pwrs = satur_pwr;
2037 break;
2038 }
2039 }
2040 }
2041 }
2042
2043 /**
2044 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2045 *
2046 * Second pass (during init) to set up priv->channel_info
2047 *
2048 * Set up Tx-power settings in our channel info database for each VALID
2049 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2050 * and current temperature.
2051 *
2052 * Since this is based on current temperature (at init time), these values may
2053 * not be valid for very long, but it gives us a starting/default point,
2054 * and allows us to active (i.e. using Tx) scan.
2055 *
2056 * This does *not* write values to NIC, just sets up our internal table.
2057 */
2058 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2059 {
2060 struct iwl_channel_info *ch_info = NULL;
2061 struct iwl3945_channel_power_info *pwr_info;
2062 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2063 int delta_index;
2064 u8 rate_index;
2065 u8 scan_tbl_index;
2066 const s8 *clip_pwrs; /* array of power levels for each rate */
2067 u8 gain, dsp_atten;
2068 s8 power;
2069 u8 pwr_index, base_pwr_index, a_band;
2070 u8 i;
2071 int temperature;
2072
2073 /* save temperature reference,
2074 * so we can determine next time to calibrate */
2075 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2076 priv->last_temperature = temperature;
2077
2078 iwl3945_hw_reg_init_channel_groups(priv);
2079
2080 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2081 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2082 i++, ch_info++) {
2083 a_band = is_channel_a_band(ch_info);
2084 if (!is_channel_valid(ch_info))
2085 continue;
2086
2087 /* find this channel's channel group (*not* "band") index */
2088 ch_info->group_index =
2089 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2090
2091 /* Get this chnlgrp's rate->max/clip-powers table */
2092 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2093
2094 /* calculate power index *adjustment* value according to
2095 * diff between current temperature and factory temperature */
2096 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2097 eeprom->groups[ch_info->group_index].
2098 temperature);
2099
2100 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2101 ch_info->channel, delta_index, temperature +
2102 IWL_TEMP_CONVERT);
2103
2104 /* set tx power value for all OFDM rates */
2105 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2106 rate_index++) {
2107 s32 uninitialized_var(power_idx);
2108 int rc;
2109
2110 /* use channel group's clip-power table,
2111 * but don't exceed channel's max power */
2112 s8 pwr = min(ch_info->max_power_avg,
2113 clip_pwrs[rate_index]);
2114
2115 pwr_info = &ch_info->power_info[rate_index];
2116
2117 /* get base (i.e. at factory-measured temperature)
2118 * power table index for this rate's power */
2119 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2120 ch_info->group_index,
2121 &power_idx);
2122 if (rc) {
2123 IWL_ERR(priv, "Invalid power index\n");
2124 return rc;
2125 }
2126 pwr_info->base_power_index = (u8) power_idx;
2127
2128 /* temperature compensate */
2129 power_idx += delta_index;
2130
2131 /* stay within range of gain table */
2132 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2133
2134 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2135 pwr_info->requested_power = pwr;
2136 pwr_info->power_table_index = (u8) power_idx;
2137 pwr_info->tpc.tx_gain =
2138 power_gain_table[a_band][power_idx].tx_gain;
2139 pwr_info->tpc.dsp_atten =
2140 power_gain_table[a_band][power_idx].dsp_atten;
2141 }
2142
2143 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2144 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2145 power = pwr_info->requested_power +
2146 IWL_CCK_FROM_OFDM_POWER_DIFF;
2147 pwr_index = pwr_info->power_table_index +
2148 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2149 base_pwr_index = pwr_info->base_power_index +
2150 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2151
2152 /* stay within table range */
2153 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2154 gain = power_gain_table[a_band][pwr_index].tx_gain;
2155 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2156
2157 /* fill each CCK rate's iwl3945_channel_power_info structure
2158 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2159 * NOTE: CCK rates start at end of OFDM rates! */
2160 for (rate_index = 0;
2161 rate_index < IWL_CCK_RATES; rate_index++) {
2162 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2163 pwr_info->requested_power = power;
2164 pwr_info->power_table_index = pwr_index;
2165 pwr_info->base_power_index = base_pwr_index;
2166 pwr_info->tpc.tx_gain = gain;
2167 pwr_info->tpc.dsp_atten = dsp_atten;
2168 }
2169
2170 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2171 for (scan_tbl_index = 0;
2172 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2173 s32 actual_index = (scan_tbl_index == 0) ?
2174 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2175 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2176 actual_index, clip_pwrs, ch_info, a_band);
2177 }
2178 }
2179
2180 return 0;
2181 }
2182
2183 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2184 {
2185 int rc;
2186
2187 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2188 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2189 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2190 if (rc < 0)
2191 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2192
2193 return 0;
2194 }
2195
2196 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2197 {
2198 int txq_id = txq->q.id;
2199
2200 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2201
2202 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2203
2204 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2205 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2206
2207 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2208 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2209 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2210 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2211 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2212 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2213
2214 /* fake read to flush all prev. writes */
2215 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2216
2217 return 0;
2218 }
2219
2220 /*
2221 * HCMD utils
2222 */
2223 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2224 {
2225 switch (cmd_id) {
2226 case REPLY_RXON:
2227 return sizeof(struct iwl3945_rxon_cmd);
2228 case POWER_TABLE_CMD:
2229 return sizeof(struct iwl3945_powertable_cmd);
2230 default:
2231 return len;
2232 }
2233 }
2234
2235
2236 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2237 {
2238 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2239 addsta->mode = cmd->mode;
2240 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2241 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2242 addsta->station_flags = cmd->station_flags;
2243 addsta->station_flags_msk = cmd->station_flags_msk;
2244 addsta->tid_disable_tx = cpu_to_le16(0);
2245 addsta->rate_n_flags = cmd->rate_n_flags;
2246 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2247 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2248 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2249
2250 return (u16)sizeof(struct iwl3945_addsta_cmd);
2251 }
2252
2253 static int iwl3945_add_bssid_station(struct iwl_priv *priv,
2254 const u8 *addr, u8 *sta_id_r)
2255 {
2256 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2257 int ret;
2258 u8 sta_id;
2259 unsigned long flags;
2260
2261 if (sta_id_r)
2262 *sta_id_r = IWL_INVALID_STATION;
2263
2264 ret = iwl_add_station_common(priv, ctx, addr, 0, NULL, &sta_id);
2265 if (ret) {
2266 IWL_ERR(priv, "Unable to add station %pM\n", addr);
2267 return ret;
2268 }
2269
2270 if (sta_id_r)
2271 *sta_id_r = sta_id;
2272
2273 spin_lock_irqsave(&priv->sta_lock, flags);
2274 priv->stations[sta_id].used |= IWL_STA_LOCAL;
2275 spin_unlock_irqrestore(&priv->sta_lock, flags);
2276
2277 return 0;
2278 }
2279 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2280 struct ieee80211_vif *vif, bool add)
2281 {
2282 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2283 int ret;
2284
2285 if (add) {
2286 ret = iwl3945_add_bssid_station(priv, vif->bss_conf.bssid,
2287 &vif_priv->ibss_bssid_sta_id);
2288 if (ret)
2289 return ret;
2290
2291 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2292 (priv->band == IEEE80211_BAND_5GHZ) ?
2293 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2294 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2295
2296 return 0;
2297 }
2298
2299 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2300 vif->bss_conf.bssid);
2301 }
2302
2303 /**
2304 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2305 */
2306 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2307 {
2308 int rc, i, index, prev_index;
2309 struct iwl3945_rate_scaling_cmd rate_cmd = {
2310 .reserved = {0, 0, 0},
2311 };
2312 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2313
2314 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2315 index = iwl3945_rates[i].table_rs_index;
2316
2317 table[index].rate_n_flags =
2318 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2319 table[index].try_cnt = priv->retry_rate;
2320 prev_index = iwl3945_get_prev_ieee_rate(i);
2321 table[index].next_rate_index =
2322 iwl3945_rates[prev_index].table_rs_index;
2323 }
2324
2325 switch (priv->band) {
2326 case IEEE80211_BAND_5GHZ:
2327 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2328 /* If one of the following CCK rates is used,
2329 * have it fall back to the 6M OFDM rate */
2330 for (i = IWL_RATE_1M_INDEX_TABLE;
2331 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2332 table[i].next_rate_index =
2333 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2334
2335 /* Don't fall back to CCK rates */
2336 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2337 IWL_RATE_9M_INDEX_TABLE;
2338
2339 /* Don't drop out of OFDM rates */
2340 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2341 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2342 break;
2343
2344 case IEEE80211_BAND_2GHZ:
2345 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2346 /* If an OFDM rate is used, have it fall back to the
2347 * 1M CCK rates */
2348
2349 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2350 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
2351
2352 index = IWL_FIRST_CCK_RATE;
2353 for (i = IWL_RATE_6M_INDEX_TABLE;
2354 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2355 table[i].next_rate_index =
2356 iwl3945_rates[index].table_rs_index;
2357
2358 index = IWL_RATE_11M_INDEX_TABLE;
2359 /* CCK shouldn't fall back to OFDM... */
2360 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2361 }
2362 break;
2363
2364 default:
2365 WARN_ON(1);
2366 break;
2367 }
2368
2369 /* Update the rate scaling for control frame Tx */
2370 rate_cmd.table_id = 0;
2371 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2372 &rate_cmd);
2373 if (rc)
2374 return rc;
2375
2376 /* Update the rate scaling for data frame Tx */
2377 rate_cmd.table_id = 1;
2378 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2379 &rate_cmd);
2380 }
2381
2382 /* Called when initializing driver */
2383 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2384 {
2385 memset((void *)&priv->hw_params, 0,
2386 sizeof(struct iwl_hw_params));
2387
2388 priv->_3945.shared_virt =
2389 dma_alloc_coherent(&priv->pci_dev->dev,
2390 sizeof(struct iwl3945_shared),
2391 &priv->_3945.shared_phys, GFP_KERNEL);
2392 if (!priv->_3945.shared_virt) {
2393 IWL_ERR(priv, "failed to allocate pci memory\n");
2394 return -ENOMEM;
2395 }
2396
2397 /* Assign number of Usable TX queues */
2398 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
2399
2400 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2401 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2402 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2403 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2404 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2405 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL3945_BROADCAST_ID;
2406
2407 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2408
2409 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2410 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2411 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2412
2413 return 0;
2414 }
2415
2416 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2417 struct iwl3945_frame *frame, u8 rate)
2418 {
2419 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2420 unsigned int frame_size;
2421
2422 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2423 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2424
2425 tx_beacon_cmd->tx.sta_id =
2426 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2427 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2428
2429 frame_size = iwl3945_fill_beacon_frame(priv,
2430 tx_beacon_cmd->frame,
2431 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2432
2433 BUG_ON(frame_size > MAX_MPDU_SIZE);
2434 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2435
2436 tx_beacon_cmd->tx.rate = rate;
2437 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2438 TX_CMD_FLG_TSF_MSK);
2439
2440 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2441 tx_beacon_cmd->tx.supp_rates[0] =
2442 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2443
2444 tx_beacon_cmd->tx.supp_rates[1] =
2445 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2446
2447 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2448 }
2449
2450 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2451 {
2452 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2453 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2454 }
2455
2456 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2457 {
2458 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2459 iwl3945_bg_reg_txpower_periodic);
2460 }
2461
2462 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2463 {
2464 cancel_delayed_work(&priv->_3945.thermal_periodic);
2465 }
2466
2467 /* check contents of special bootstrap uCode SRAM */
2468 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2469 {
2470 __le32 *image = priv->ucode_boot.v_addr;
2471 u32 len = priv->ucode_boot.len;
2472 u32 reg;
2473 u32 val;
2474
2475 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2476
2477 /* verify BSM SRAM contents */
2478 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2479 for (reg = BSM_SRAM_LOWER_BOUND;
2480 reg < BSM_SRAM_LOWER_BOUND + len;
2481 reg += sizeof(u32), image++) {
2482 val = iwl_read_prph(priv, reg);
2483 if (val != le32_to_cpu(*image)) {
2484 IWL_ERR(priv, "BSM uCode verification failed at "
2485 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2486 BSM_SRAM_LOWER_BOUND,
2487 reg - BSM_SRAM_LOWER_BOUND, len,
2488 val, le32_to_cpu(*image));
2489 return -EIO;
2490 }
2491 }
2492
2493 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2494
2495 return 0;
2496 }
2497
2498
2499 /******************************************************************************
2500 *
2501 * EEPROM related functions
2502 *
2503 ******************************************************************************/
2504
2505 /*
2506 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2507 * embedded controller) as EEPROM reader; each read is a series of pulses
2508 * to/from the EEPROM chip, not a single event, so even reads could conflict
2509 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2510 * simply claims ownership, which should be safe when this function is called
2511 * (i.e. before loading uCode!).
2512 */
2513 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2514 {
2515 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2516 return 0;
2517 }
2518
2519
2520 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2521 {
2522 return;
2523 }
2524
2525 /**
2526 * iwl3945_load_bsm - Load bootstrap instructions
2527 *
2528 * BSM operation:
2529 *
2530 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2531 * in special SRAM that does not power down during RFKILL. When powering back
2532 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2533 * the bootstrap program into the on-board processor, and starts it.
2534 *
2535 * The bootstrap program loads (via DMA) instructions and data for a new
2536 * program from host DRAM locations indicated by the host driver in the
2537 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2538 * automatically.
2539 *
2540 * When initializing the NIC, the host driver points the BSM to the
2541 * "initialize" uCode image. This uCode sets up some internal data, then
2542 * notifies host via "initialize alive" that it is complete.
2543 *
2544 * The host then replaces the BSM_DRAM_* pointer values to point to the
2545 * normal runtime uCode instructions and a backup uCode data cache buffer
2546 * (filled initially with starting data values for the on-board processor),
2547 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2548 * which begins normal operation.
2549 *
2550 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2551 * the backup data cache in DRAM before SRAM is powered down.
2552 *
2553 * When powering back up, the BSM loads the bootstrap program. This reloads
2554 * the runtime uCode instructions and the backup data cache into SRAM,
2555 * and re-launches the runtime uCode from where it left off.
2556 */
2557 static int iwl3945_load_bsm(struct iwl_priv *priv)
2558 {
2559 __le32 *image = priv->ucode_boot.v_addr;
2560 u32 len = priv->ucode_boot.len;
2561 dma_addr_t pinst;
2562 dma_addr_t pdata;
2563 u32 inst_len;
2564 u32 data_len;
2565 int rc;
2566 int i;
2567 u32 done;
2568 u32 reg_offset;
2569
2570 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2571
2572 /* make sure bootstrap program is no larger than BSM's SRAM size */
2573 if (len > IWL39_MAX_BSM_SIZE)
2574 return -EINVAL;
2575
2576 /* Tell bootstrap uCode where to find the "Initialize" uCode
2577 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2578 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2579 * after the "initialize" uCode has run, to point to
2580 * runtime/protocol instructions and backup data cache. */
2581 pinst = priv->ucode_init.p_addr;
2582 pdata = priv->ucode_init_data.p_addr;
2583 inst_len = priv->ucode_init.len;
2584 data_len = priv->ucode_init_data.len;
2585
2586 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2587 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2588 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2589 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2590
2591 /* Fill BSM memory with bootstrap instructions */
2592 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2593 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2594 reg_offset += sizeof(u32), image++)
2595 _iwl_write_prph(priv, reg_offset,
2596 le32_to_cpu(*image));
2597
2598 rc = iwl3945_verify_bsm(priv);
2599 if (rc)
2600 return rc;
2601
2602 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2603 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2604 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2605 IWL39_RTC_INST_LOWER_BOUND);
2606 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2607
2608 /* Load bootstrap code into instruction SRAM now,
2609 * to prepare to load "initialize" uCode */
2610 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2611 BSM_WR_CTRL_REG_BIT_START);
2612
2613 /* Wait for load of bootstrap uCode to finish */
2614 for (i = 0; i < 100; i++) {
2615 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2616 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2617 break;
2618 udelay(10);
2619 }
2620 if (i < 100)
2621 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2622 else {
2623 IWL_ERR(priv, "BSM write did not complete!\n");
2624 return -EIO;
2625 }
2626
2627 /* Enable future boot loads whenever power management unit triggers it
2628 * (e.g. when powering back up after power-save shutdown) */
2629 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2630 BSM_WR_CTRL_REG_BIT_START_EN);
2631
2632 return 0;
2633 }
2634
2635 static struct iwl_hcmd_ops iwl3945_hcmd = {
2636 .rxon_assoc = iwl3945_send_rxon_assoc,
2637 .commit_rxon = iwl3945_commit_rxon,
2638 .send_bt_config = iwl_send_bt_config,
2639 };
2640
2641 static struct iwl_lib_ops iwl3945_lib = {
2642 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2643 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2644 .txq_init = iwl3945_hw_tx_queue_init,
2645 .load_ucode = iwl3945_load_bsm,
2646 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2647 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2648 .apm_ops = {
2649 .init = iwl3945_apm_init,
2650 .config = iwl3945_nic_config,
2651 },
2652 .eeprom_ops = {
2653 .regulatory_bands = {
2654 EEPROM_REGULATORY_BAND_1_CHANNELS,
2655 EEPROM_REGULATORY_BAND_2_CHANNELS,
2656 EEPROM_REGULATORY_BAND_3_CHANNELS,
2657 EEPROM_REGULATORY_BAND_4_CHANNELS,
2658 EEPROM_REGULATORY_BAND_5_CHANNELS,
2659 EEPROM_REGULATORY_BAND_NO_HT40,
2660 EEPROM_REGULATORY_BAND_NO_HT40,
2661 },
2662 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2663 .release_semaphore = iwl3945_eeprom_release_semaphore,
2664 .query_addr = iwlcore_eeprom_query_addr,
2665 },
2666 .send_tx_power = iwl3945_send_tx_power,
2667 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2668 .isr_ops = {
2669 .isr = iwl_isr_legacy,
2670 },
2671
2672 .debugfs_ops = {
2673 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2674 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2675 .general_stats_read = iwl3945_ucode_general_stats_read,
2676 },
2677 };
2678
2679 static const struct iwl_legacy_ops iwl3945_legacy_ops = {
2680 .post_associate = iwl3945_post_associate,
2681 .config_ap = iwl3945_config_ap,
2682 .manage_ibss_station = iwl3945_manage_ibss_station,
2683 };
2684
2685 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2686 .get_hcmd_size = iwl3945_get_hcmd_size,
2687 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2688 .tx_cmd_protection = iwl_legacy_tx_cmd_protection,
2689 .request_scan = iwl3945_request_scan,
2690 .post_scan = iwl3945_post_scan,
2691 };
2692
2693 static const struct iwl_ops iwl3945_ops = {
2694 .lib = &iwl3945_lib,
2695 .hcmd = &iwl3945_hcmd,
2696 .utils = &iwl3945_hcmd_utils,
2697 .led = &iwl3945_led_ops,
2698 .legacy = &iwl3945_legacy_ops,
2699 .ieee80211_ops = &iwl3945_hw_ops,
2700 };
2701
2702 static struct iwl_base_params iwl3945_base_params = {
2703 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2704 .num_of_queues = IWL39_NUM_QUEUES,
2705 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2706 .set_l0s = false,
2707 .use_bsm = true,
2708 .use_isr_legacy = true,
2709 .led_compensation = 64,
2710 .broken_powersave = true,
2711 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2712 .wd_timeout = IWL_DEF_WD_TIMEOUT,
2713 .max_event_log_size = 512,
2714 .tx_power_by_driver = true,
2715 };
2716
2717 static struct iwl_cfg iwl3945_bg_cfg = {
2718 .name = "3945BG",
2719 .fw_name_pre = IWL3945_FW_PRE,
2720 .ucode_api_max = IWL3945_UCODE_API_MAX,
2721 .ucode_api_min = IWL3945_UCODE_API_MIN,
2722 .sku = IWL_SKU_G,
2723 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2724 .ops = &iwl3945_ops,
2725 .mod_params = &iwl3945_mod_params,
2726 .base_params = &iwl3945_base_params,
2727 .led_mode = IWL_LED_BLINK,
2728 };
2729
2730 static struct iwl_cfg iwl3945_abg_cfg = {
2731 .name = "3945ABG",
2732 .fw_name_pre = IWL3945_FW_PRE,
2733 .ucode_api_max = IWL3945_UCODE_API_MAX,
2734 .ucode_api_min = IWL3945_UCODE_API_MIN,
2735 .sku = IWL_SKU_A|IWL_SKU_G,
2736 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2737 .ops = &iwl3945_ops,
2738 .mod_params = &iwl3945_mod_params,
2739 .base_params = &iwl3945_base_params,
2740 .led_mode = IWL_LED_BLINK,
2741 };
2742
2743 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2744 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2745 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2746 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2747 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2748 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2749 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2750 {0}
2751 };
2752
2753 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
The kernel tree for Tao Ma.