drivers/net/wireless/rtlwifi/rtl8192ce/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL92C_DEF_H__
  31 #define __RTL92C_DEF_H__
  32
  33 #define HAL_RETRY_LIMIT_INFRA                           48
  34 #define HAL_RETRY_LIMIT_AP_ADHOC                        7
  35
  36 #define PHY_RSSI_SLID_WIN_MAX                           100
  37 #define PHY_LINKQUALITY_SLID_WIN_MAX                    20
  38 #define PHY_BEACON_RSSI_SLID_WIN_MAX                    10
  39
  40 #define RESET_DELAY_8185                                20
  41
  42 #define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
  43 #define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
  44
  45 #define NUM_OF_FIRMWARE_QUEUE                           10
  46 #define NUM_OF_PAGES_IN_FW                              0x100
  47 #define NUM_OF_PAGE_IN_FW_QUEUE_BK                      0x07
  48 #define NUM_OF_PAGE_IN_FW_QUEUE_BE                      0x07
  49 #define NUM_OF_PAGE_IN_FW_QUEUE_VI                      0x07
  50 #define NUM_OF_PAGE_IN_FW_QUEUE_VO                      0x07
  51 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                    0x0
  52 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD                     0x0
  53 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                    0x02
  54 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                    0x02
  55 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN                     0x2
  56 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB                     0xA1
  57
  58 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                  0x026
  59 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                  0x048
  60 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                  0x048
  61 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                  0x026
  62 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                 0x00
  63
  64 #define MAX_LINES_HWCONFIG_TXT                          1000
  65 #define MAX_BYTES_LINE_HWCONFIG_TXT                     256
  66
  67 #define SW_THREE_WIRE                                   0
  68 #define HW_THREE_WIRE                                   2
  69
  70 #define BT_DEMO_BOARD                                   0
  71 #define BT_QA_BOARD                                     1
  72 #define BT_FPGA                                         2
  73
  74 #define RX_SMOOTH_FACTOR                                20
  75
  76 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                 0
  77 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
  78 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
  79
  80 #define MAX_H2C_QUEUE_NUM                               10
  81
  82 #define RX_MPDU_QUEUE                                   0
  83 #define RX_CMD_QUEUE                                    1
  84 #define RX_MAX_QUEUE                                    2
  85 #define AC2QUEUEID(_AC)                                 (_AC)
  86
  87 #define C2H_RX_CMD_HDR_LEN                              8
  88 #define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
  89         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
  90 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
  91         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
  92 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
  93         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
  94 #define GET_C2H_CMD_CONTINUE(__prxhdr)          \
  95         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
  96 #define GET_C2H_CMD_CONTENT(__prxhdr)           \
  97         ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
  98
  99 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
 100         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
 101 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)       \
 102         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
 103 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
 104         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
 105 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
 106         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
 107 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)     \
 108         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
 109 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 110         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 111 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)       \
 112         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 113 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)      \
 114         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 115 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)       \
 116         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 117
 118 #define CHIP_VER_B                      BIT(4)
 119 #define CHIP_92C_BITMASK                BIT(0)
 120 #define CHIP_92C_1T2R                   0x03
 121 #define CHIP_92C                        0x01
 122 #define CHIP_88C                        0x00
 123
 124 enum version_8192c {
 125         VERSION_A_CHIP_92C = 0x01,
 126         VERSION_A_CHIP_88C = 0x00,
 127         VERSION_B_CHIP_92C = 0x11,
 128         VERSION_B_CHIP_88C = 0x10,
 129         VERSION_UNKNOWN = 0x88,
 130 };
 131
 132 #define IS_CHIP_VER_B(version)  ((version & CHIP_VER_B) ? true : false)
 133 #define IS_92C_SERIAL(version)  ((version & CHIP_92C_BITMASK) ? true : false)
 134
 135 enum rtl819x_loopback_e {
 136         RTL819X_NO_LOOPBACK = 0,
 137         RTL819X_MAC_LOOPBACK = 1,
 138         RTL819X_DMA_LOOPBACK = 2,
 139         RTL819X_CCK_LOOPBACK = 3,
 140 };
 141
 142 enum rf_optype {
 143         RF_OP_BY_SW_3WIRE = 0,
 144         RF_OP_BY_FW,
 145         RF_OP_MAX
 146 };
 147
 148 enum rf_power_state {
 149         RF_ON,
 150         RF_OFF,
 151         RF_SLEEP,
 152         RF_SHUT_DOWN,
 153 };
 154
 155 enum power_save_mode {
 156         POWER_SAVE_MODE_ACTIVE,
 157         POWER_SAVE_MODE_SAVE,
 158 };
 159
 160 enum power_polocy_config {
 161         POWERCFG_MAX_POWER_SAVINGS,
 162         POWERCFG_GLOBAL_POWER_SAVINGS,
 163         POWERCFG_LOCAL_POWER_SAVINGS,
 164         POWERCFG_LENOVO,
 165 };
 166
 167 enum interface_select_pci {
 168         INTF_SEL1_MINICARD = 0,
 169         INTF_SEL0_PCIE = 1,
 170         INTF_SEL2_RSV = 2,
 171         INTF_SEL3_RSV = 3,
 172 };
 173
 174 enum hal_fw_c2h_cmd_id {
 175         HAL_FW_C2H_CMD_Read_MACREG = 0,
 176         HAL_FW_C2H_CMD_Read_BBREG = 1,
 177         HAL_FW_C2H_CMD_Read_RFREG = 2,
 178         HAL_FW_C2H_CMD_Read_EEPROM = 3,
 179         HAL_FW_C2H_CMD_Read_EFUSE = 4,
 180         HAL_FW_C2H_CMD_Read_CAM = 5,
 181         HAL_FW_C2H_CMD_Get_BasicRate = 6,
 182         HAL_FW_C2H_CMD_Get_DataRate = 7,
 183         HAL_FW_C2H_CMD_Survey = 8,
 184         HAL_FW_C2H_CMD_SurveyDone = 9,
 185         HAL_FW_C2H_CMD_JoinBss = 10,
 186         HAL_FW_C2H_CMD_AddSTA = 11,
 187         HAL_FW_C2H_CMD_DelSTA = 12,
 188         HAL_FW_C2H_CMD_AtimDone = 13,
 189         HAL_FW_C2H_CMD_TX_Report = 14,
 190         HAL_FW_C2H_CMD_CCX_Report = 15,
 191         HAL_FW_C2H_CMD_DTM_Report = 16,
 192         HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
 193         HAL_FW_C2H_CMD_C2HLBK = 18,
 194         HAL_FW_C2H_CMD_C2HDBG = 19,
 195         HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
 196         HAL_FW_C2H_CMD_MAX
 197 };
 198
 199 enum rtl_desc_qsel {
 200         QSLT_BK = 0x2,
 201         QSLT_BE = 0x0,
 202         QSLT_VI = 0x5,
 203         QSLT_VO = 0x7,
 204         QSLT_BEACON = 0x10,
 205         QSLT_HIGH = 0x11,
 206         QSLT_MGNT = 0x12,
 207         QSLT_CMD = 0x13,
 208 };
 209
 210 enum rtl_desc92c_rate {
 211         DESC92C_RATE1M = 0x00,
 212         DESC92C_RATE2M = 0x01,
 213         DESC92C_RATE5_5M = 0x02,
 214         DESC92C_RATE11M = 0x03,
 215
 216         DESC92C_RATE6M = 0x04,
 217         DESC92C_RATE9M = 0x05,
 218         DESC92C_RATE12M = 0x06,
 219         DESC92C_RATE18M = 0x07,
 220         DESC92C_RATE24M = 0x08,
 221         DESC92C_RATE36M = 0x09,
 222         DESC92C_RATE48M = 0x0a,
 223         DESC92C_RATE54M = 0x0b,
 224
 225         DESC92C_RATEMCS0 = 0x0c,
 226         DESC92C_RATEMCS1 = 0x0d,
 227         DESC92C_RATEMCS2 = 0x0e,
 228         DESC92C_RATEMCS3 = 0x0f,
 229         DESC92C_RATEMCS4 = 0x10,
 230         DESC92C_RATEMCS5 = 0x11,
 231         DESC92C_RATEMCS6 = 0x12,
 232         DESC92C_RATEMCS7 = 0x13,
 233         DESC92C_RATEMCS8 = 0x14,
 234         DESC92C_RATEMCS9 = 0x15,
 235         DESC92C_RATEMCS10 = 0x16,
 236         DESC92C_RATEMCS11 = 0x17,
 237         DESC92C_RATEMCS12 = 0x18,
 238         DESC92C_RATEMCS13 = 0x19,
 239         DESC92C_RATEMCS14 = 0x1a,
 240         DESC92C_RATEMCS15 = 0x1b,
 241         DESC92C_RATEMCS15_SG = 0x1c,
 242         DESC92C_RATEMCS32 = 0x20,
 243 };
 244
 245 struct phy_sts_cck_8192s_t {
 246         u8 adc_pwdb_X[4];
 247         u8 sq_rpt;
 248         u8 cck_agc_rpt;
 249 };
 250
 251 struct h2c_cmd_8192c {
 252         u8 element_id;
 253         u32 cmd_len;
 254         u8 *p_cmdbuffer;
 255 };
 256
 257 #endif