drivers/platform/x86/intel_pmic_gpio.c

   1 /* Moorestown PMIC GPIO (access through IPC) driver
   2  * Copyright (c) 2008 - 2009, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16  */
  17
  18 /* Supports:
  19  * Moorestown platform PMIC chip
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/stddef.h>
  27 #include <linux/slab.h>
  28 #include <linux/ioport.h>
  29 #include <linux/init.h>
  30 #include <linux/io.h>
  31 #include <linux/gpio.h>
  32 #include <asm/intel_scu_ipc.h>
  33 #include <linux/device.h>
  34 #include <linux/intel_pmic_gpio.h>
  35 #include <linux/platform_device.h>
  36
  37 #define DRIVER_NAME "pmic_gpio"
  38
  39 /* register offset that IPC driver should use
  40  * 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
  41  */
  42 enum pmic_gpio_register {
  43         GPIO0           = 0xE0,
  44         GPIO7           = 0xE7,
  45         GPIOINT         = 0xE8,
  46         GPOSWCTL0       = 0xEC,
  47         GPOSWCTL5       = 0xF1,
  48         GPO             = 0xF4,
  49 };
  50
  51 /* bits definition for GPIO & GPOSW */
  52 #define GPIO_DRV 0x01
  53 #define GPIO_DIR 0x02
  54 #define GPIO_DIN 0x04
  55 #define GPIO_DOU 0x08
  56 #define GPIO_INTCTL 0x30
  57 #define GPIO_DBC 0xc0
  58
  59 #define GPOSW_DRV 0x01
  60 #define GPOSW_DOU 0x08
  61 #define GPOSW_RDRV 0x30
  62
  63 #define GPIO_UPDATE_TYPE        0x80000000
  64
  65 #define NUM_GPIO 24
  66
  67 struct pmic_gpio {
  68         struct mutex            buslock;
  69         struct gpio_chip        chip;
  70         void                    *gpiointr;
  71         int                     irq;
  72         unsigned                irq_base;
  73         unsigned int            update_type;
  74         u32                     trigger_type;
  75 };
  76
  77 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  78 {
  79         if (offset > 8) {
  80                 printk(KERN_ERR
  81                         "%s: only pin 0-7 support input\n", __func__);
  82                 return -1;/* we only have 8 GPIO can use as input */
  83         }
  84         return intel_scu_ipc_update_register(GPIO0 + offset,
  85                                                         GPIO_DIR, GPIO_DIR);
  86 }
  87
  88 static int pmic_gpio_direction_output(struct gpio_chip *chip,
  89                         unsigned offset, int value)
  90 {
  91         int rc = 0;
  92
  93         if (offset < 8)/* it is GPIO */
  94                 rc = intel_scu_ipc_update_register(GPIO0 + offset,
  95                                 GPIO_DRV | (value ? GPIO_DOU : 0),
  96                                 GPIO_DRV | GPIO_DOU | GPIO_DIR);
  97         else if (offset < 16)/* it is GPOSW */
  98                 rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
  99                                 GPOSW_DRV | (value ? GPOSW_DOU : 0),
 100                                 GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
 101         else if (offset > 15 && offset < 24)/* it is GPO */
 102                 rc = intel_scu_ipc_update_register(GPO,
 103                                 value ? 1 << (offset - 16) : 0,
 104                                 1 << (offset - 16));
 105         else {
 106                 printk(KERN_ERR
 107                         "%s: invalid PMIC GPIO pin %d!\n", __func__, offset);
 108                 WARN_ON(1);
 109         }
 110
 111         return rc;
 112 }
 113
 114 static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
 115 {
 116         u8 r;
 117         int ret;
 118
 119         /* we only have 8 GPIO pins we can use as input */
 120         if (offset > 8)
 121                 return -EOPNOTSUPP;
 122         ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
 123         if (ret < 0)
 124                 return ret;
 125         return r & GPIO_DIN;
 126 }
 127
 128 static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 129 {
 130         if (offset < 8)/* it is GPIO */
 131                 intel_scu_ipc_update_register(GPIO0 + offset,
 132                         GPIO_DRV | (value ? GPIO_DOU : 0),
 133                         GPIO_DRV | GPIO_DOU);
 134         else if (offset < 16)/* it is GPOSW */
 135                 intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
 136                         GPOSW_DRV | (value ? GPOSW_DOU : 0),
 137                         GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
 138         else if (offset > 15 && offset < 24) /* it is GPO */
 139                 intel_scu_ipc_update_register(GPO,
 140                         value ? 1 << (offset - 16) : 0,
 141                         1 << (offset - 16));
 142 }
 143
 144 /*
 145  * This is called from genirq with pg->buslock locked and
 146  * irq_desc->lock held. We can not access the scu bus here, so we
 147  * store the change and update in the bus_sync_unlock() function below
 148  */
 149 static int pmic_irq_type(struct irq_data *data, unsigned type)
 150 {
 151         struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
 152         u32 gpio = data->irq - pg->irq_base;
 153
 154         if (gpio >= pg->chip.ngpio)
 155                 return -EINVAL;
 156
 157         pg->trigger_type = type;
 158         pg->update_type = gpio | GPIO_UPDATE_TYPE;
 159         return 0;
 160 }
 161
 162 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 163 {
 164         struct pmic_gpio *pg = container_of(chip, struct pmic_gpio, chip);
 165
 166         return pg->irq_base + offset;
 167 }
 168
 169 /* the gpiointr register is read-clear, so just do nothing. */
 170 static void pmic_irq_unmask(struct irq_data *data) { }
 171
 172 static void pmic_irq_mask(struct irq_data *data) { }
 173
 174 static struct irq_chip pmic_irqchip = {
 175         .name           = "PMIC-GPIO",
 176         .irq_mask       = pmic_irq_mask,
 177         .irq_unmask     = pmic_irq_unmask,
 178         .irq_set_type   = pmic_irq_type,
 179 };
 180
 181 static irqreturn_t pmic_irq_handler(int irq, void *data)
 182 {
 183         struct pmic_gpio *pg = data;
 184         u8 intsts = *((u8 *)pg->gpiointr + 4);
 185         int gpio;
 186         irqreturn_t ret = IRQ_NONE;
 187
 188         for (gpio = 0; gpio < 8; gpio++) {
 189                 if (intsts & (1 << gpio)) {
 190                         pr_debug("pmic pin %d triggered\n", gpio);
 191                         generic_handle_irq(pg->irq_base + gpio);
 192                         ret = IRQ_HANDLED;
 193                 }
 194         }
 195         return ret;
 196 }
 197
 198 static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
 199 {
 200         struct device *dev = &pdev->dev;
 201         int irq = platform_get_irq(pdev, 0);
 202         struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;
 203
 204         struct pmic_gpio *pg;
 205         int retval;
 206         int i;
 207
 208         if (irq < 0) {
 209                 dev_dbg(dev, "no IRQ line\n");
 210                 return -EINVAL;
 211         }
 212
 213         if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
 214                 dev_dbg(dev, "incorrect or missing platform data\n");
 215                 return -EINVAL;
 216         }
 217
 218         pg = kzalloc(sizeof(*pg), GFP_KERNEL);
 219         if (!pg)
 220                 return -ENOMEM;
 221
 222         dev_set_drvdata(dev, pg);
 223
 224         pg->irq = irq;
 225         /* setting up SRAM mapping for GPIOINT register */
 226         pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
 227         if (!pg->gpiointr) {
 228                 printk(KERN_ERR "%s: Can not map GPIOINT.\n", __func__);
 229                 retval = -EINVAL;
 230                 goto err2;
 231         }
 232         pg->irq_base = pdata->irq_base;
 233         pg->chip.label = "intel_pmic";
 234         pg->chip.direction_input = pmic_gpio_direction_input;
 235         pg->chip.direction_output = pmic_gpio_direction_output;
 236         pg->chip.get = pmic_gpio_get;
 237         pg->chip.set = pmic_gpio_set;
 238         pg->chip.to_irq = pmic_gpio_to_irq;
 239         pg->chip.base = pdata->gpio_base;
 240         pg->chip.ngpio = NUM_GPIO;
 241         pg->chip.can_sleep = 1;
 242         pg->chip.dev = dev;
 243
 244         mutex_init(&pg->buslock);
 245
 246         pg->chip.dev = dev;
 247         retval = gpiochip_add(&pg->chip);
 248         if (retval) {
 249                 printk(KERN_ERR "%s: Can not add pmic gpio chip.\n", __func__);
 250                 goto err;
 251         }
 252
 253         retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
 254         if (retval) {
 255                 printk(KERN_WARNING "pmic: Interrupt request failed\n");
 256                 goto err;
 257         }
 258
 259         for (i = 0; i < 8; i++) {
 260                 set_irq_chip_and_handler_name(i + pg->irq_base, &pmic_irqchip,
 261                                         handle_simple_irq, "demux");
 262                 set_irq_chip_data(i + pg->irq_base, pg);
 263         }
 264         return 0;
 265 err:
 266         iounmap(pg->gpiointr);
 267 err2:
 268         kfree(pg);
 269         return retval;
 270 }
 271
 272 /* at the same time, register a platform driver
 273  * this supports the sfi 0.81 fw */
 274 static struct platform_driver platform_pmic_gpio_driver = {
 275         .driver = {
 276                 .name           = DRIVER_NAME,
 277                 .owner          = THIS_MODULE,
 278         },
 279         .probe          = platform_pmic_gpio_probe,
 280 };
 281
 282 static int __init platform_pmic_gpio_init(void)
 283 {
 284         return platform_driver_register(&platform_pmic_gpio_driver);
 285 }
 286
 287 subsys_initcall(platform_pmic_gpio_init);
 288
 289 MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
 290 MODULE_DESCRIPTION("Intel Moorestown PMIC GPIO driver");
 291 MODULE_LICENSE("GPL v2");