?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ocfs2: Make the left masklogs compat.
[taoma-kernel.git] / drivers / spi / spi_s3c64xx.c
blob795828b90f45ebe4eef243d4abccfebee503f2f7
1 /* linux/drivers/spi/spi_s3c64xx.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/spi.h>
29
30 #include <mach/dma.h>
31 #include <plat/s3c64xx-spi.h>
32
33 /* Registers and bit-fields */
34
35 #define S3C64XX_SPI_CH_CFG 0x00
36 #define S3C64XX_SPI_CLK_CFG 0x04
37 #define S3C64XX_SPI_MODE_CFG 0x08
38 #define S3C64XX_SPI_SLAVE_SEL 0x0C
39 #define S3C64XX_SPI_INT_EN 0x10
40 #define S3C64XX_SPI_STATUS 0x14
41 #define S3C64XX_SPI_TX_DATA 0x18
42 #define S3C64XX_SPI_RX_DATA 0x1C
43 #define S3C64XX_SPI_PACKET_CNT 0x20
44 #define S3C64XX_SPI_PENDING_CLR 0x24
45 #define S3C64XX_SPI_SWAP_CFG 0x28
46 #define S3C64XX_SPI_FB_CLK 0x2C
47
48 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
49 #define S3C64XX_SPI_CH_SW_RST (1<<5)
50 #define S3C64XX_SPI_CH_SLAVE (1<<4)
51 #define S3C64XX_SPI_CPOL_L (1<<3)
52 #define S3C64XX_SPI_CPHA_B (1<<2)
53 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
54 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
55
56 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
57 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
58 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
59 #define S3C64XX_SPI_PSR_MASK 0xff
60
61 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
62 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
63 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
64 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
65 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
66 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
67 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
68 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
69 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
70 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
71 #define S3C64XX_SPI_MODE_4BURST (1<<0)
72
73 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
74 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
75
76 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
77
78 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
79 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
80
81 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
88
89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
95
96 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
97
98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
103
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
112
113 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
114
115 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
116 (((i)->fifo_lvl_mask + 1))) \
117 ? 1 : 0)
118
119 #define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \
120 (((i)->fifo_lvl_mask + 1) << 1)) \
121 ? 1 : 0)
122 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
123 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
124
125 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
126 #define S3C64XX_SPI_TRAILCNT_OFF 19
127
128 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
129
130 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
131
132 #define SUSPND (1<<0)
133 #define SPIBUSY (1<<1)
134 #define RXBUSY (1<<2)
135 #define TXBUSY (1<<3)
136
137 /**
138 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
139 * @clk: Pointer to the spi clock.
140 * @src_clk: Pointer to the clock used to generate SPI signals.
141 * @master: Pointer to the SPI Protocol master.
142 * @workqueue: Work queue for the SPI xfer requests.
143 * @cntrlr_info: Platform specific data for the controller this driver manages.
144 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
145 * @work: Work
146 * @queue: To log SPI xfer requests.
147 * @lock: Controller specific lock.
148 * @state: Set of FLAGS to indicate status.
149 * @rx_dmach: Controller's DMA channel for Rx.
150 * @tx_dmach: Controller's DMA channel for Tx.
151 * @sfr_start: BUS address of SPI controller regs.
152 * @regs: Pointer to ioremap'ed controller registers.
153 * @xfer_completion: To indicate completion of xfer task.
154 * @cur_mode: Stores the active configuration of the controller.
155 * @cur_bpw: Stores the active bits per word settings.
156 * @cur_speed: Stores the active xfer clock speed.
157 */
158 struct s3c64xx_spi_driver_data {
159 void __iomem *regs;
160 struct clk *clk;
161 struct clk *src_clk;
162 struct platform_device *pdev;
163 struct spi_master *master;
164 struct workqueue_struct *workqueue;
165 struct s3c64xx_spi_info *cntrlr_info;
166 struct spi_device *tgl_spi;
167 struct work_struct work;
168 struct list_head queue;
169 spinlock_t lock;
170 enum dma_ch rx_dmach;
171 enum dma_ch tx_dmach;
172 unsigned long sfr_start;
173 struct completion xfer_completion;
174 unsigned state;
175 unsigned cur_mode, cur_bpw;
176 unsigned cur_speed;
177 };
178
179 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
180 .name = "samsung-spi-dma",
181 };
182
183 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
184 {
185 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
186 void __iomem *regs = sdd->regs;
187 unsigned long loops;
188 u32 val;
189
190 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
191
192 val = readl(regs + S3C64XX_SPI_CH_CFG);
193 val |= S3C64XX_SPI_CH_SW_RST;
194 val &= ~S3C64XX_SPI_CH_HS_EN;
195 writel(val, regs + S3C64XX_SPI_CH_CFG);
196
197 /* Flush TxFIFO*/
198 loops = msecs_to_loops(1);
199 do {
200 val = readl(regs + S3C64XX_SPI_STATUS);
201 } while (TX_FIFO_LVL(val, sci) && loops--);
202
203 if (loops == 0)
204 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
205
206 /* Flush RxFIFO*/
207 loops = msecs_to_loops(1);
208 do {
209 val = readl(regs + S3C64XX_SPI_STATUS);
210 if (RX_FIFO_LVL(val, sci))
211 readl(regs + S3C64XX_SPI_RX_DATA);
212 else
213 break;
214 } while (loops--);
215
216 if (loops == 0)
217 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
218
219 val = readl(regs + S3C64XX_SPI_CH_CFG);
220 val &= ~S3C64XX_SPI_CH_SW_RST;
221 writel(val, regs + S3C64XX_SPI_CH_CFG);
222
223 val = readl(regs + S3C64XX_SPI_MODE_CFG);
224 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
225 writel(val, regs + S3C64XX_SPI_MODE_CFG);
226
227 val = readl(regs + S3C64XX_SPI_CH_CFG);
228 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
229 writel(val, regs + S3C64XX_SPI_CH_CFG);
230 }
231
232 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
233 struct spi_device *spi,
234 struct spi_transfer *xfer, int dma_mode)
235 {
236 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
237 void __iomem *regs = sdd->regs;
238 u32 modecfg, chcfg;
239
240 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
241 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
242
243 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
244 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
245
246 if (dma_mode) {
247 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
248 } else {
249 /* Always shift in data in FIFO, even if xfer is Tx only,
250 * this helps setting PCKT_CNT value for generating clocks
251 * as exactly needed.
252 */
253 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
254 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
255 | S3C64XX_SPI_PACKET_CNT_EN,
256 regs + S3C64XX_SPI_PACKET_CNT);
257 }
258
259 if (xfer->tx_buf != NULL) {
260 sdd->state |= TXBUSY;
261 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
262 if (dma_mode) {
263 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
264 s3c2410_dma_config(sdd->tx_dmach, sdd->cur_bpw / 8);
265 s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd,
266 xfer->tx_dma, xfer->len);
267 s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START);
268 } else {
269 switch (sdd->cur_bpw) {
270 case 32:
271 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
272 xfer->tx_buf, xfer->len / 4);
273 break;
274 case 16:
275 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
276 xfer->tx_buf, xfer->len / 2);
277 break;
278 default:
279 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
280 xfer->tx_buf, xfer->len);
281 break;
282 }
283 }
284 }
285
286 if (xfer->rx_buf != NULL) {
287 sdd->state |= RXBUSY;
288
289 if (sci->high_speed && sdd->cur_speed >= 30000000UL
290 && !(sdd->cur_mode & SPI_CPHA))
291 chcfg |= S3C64XX_SPI_CH_HS_EN;
292
293 if (dma_mode) {
294 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
295 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
296 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
297 | S3C64XX_SPI_PACKET_CNT_EN,
298 regs + S3C64XX_SPI_PACKET_CNT);
299 s3c2410_dma_config(sdd->rx_dmach, sdd->cur_bpw / 8);
300 s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd,
301 xfer->rx_dma, xfer->len);
302 s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START);
303 }
304 }
305
306 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
307 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
308 }
309
310 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
311 struct spi_device *spi)
312 {
313 struct s3c64xx_spi_csinfo *cs;
314
315 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
316 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
317 /* Deselect the last toggled device */
318 cs = sdd->tgl_spi->controller_data;
319 cs->set_level(cs->line,
320 spi->mode & SPI_CS_HIGH ? 0 : 1);
321 }
322 sdd->tgl_spi = NULL;
323 }
324
325 cs = spi->controller_data;
326 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
327 }
328
329 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
330 struct spi_transfer *xfer, int dma_mode)
331 {
332 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
333 void __iomem *regs = sdd->regs;
334 unsigned long val;
335 int ms;
336
337 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
338 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
339 ms += 10; /* some tolerance */
340
341 if (dma_mode) {
342 val = msecs_to_jiffies(ms) + 10;
343 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
344 } else {
345 u32 status;
346 val = msecs_to_loops(ms);
347 do {
348 status = readl(regs + S3C64XX_SPI_STATUS);
349 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
350 }
351
352 if (!val)
353 return -EIO;
354
355 if (dma_mode) {
356 u32 status;
357
358 /*
359 * DmaTx returns after simply writing data in the FIFO,
360 * w/o waiting for real transmission on the bus to finish.
361 * DmaRx returns only after Dma read data from FIFO which
362 * needs bus transmission to finish, so we don't worry if
363 * Xfer involved Rx(with or without Tx).
364 */
365 if (xfer->rx_buf == NULL) {
366 val = msecs_to_loops(10);
367 status = readl(regs + S3C64XX_SPI_STATUS);
368 while ((TX_FIFO_LVL(status, sci)
369 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
370 && --val) {
371 cpu_relax();
372 status = readl(regs + S3C64XX_SPI_STATUS);
373 }
374
375 if (!val)
376 return -EIO;
377 }
378 } else {
379 /* If it was only Tx */
380 if (xfer->rx_buf == NULL) {
381 sdd->state &= ~TXBUSY;
382 return 0;
383 }
384
385 switch (sdd->cur_bpw) {
386 case 32:
387 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
388 xfer->rx_buf, xfer->len / 4);
389 break;
390 case 16:
391 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
392 xfer->rx_buf, xfer->len / 2);
393 break;
394 default:
395 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
396 xfer->rx_buf, xfer->len);
397 break;
398 }
399 sdd->state &= ~RXBUSY;
400 }
401
402 return 0;
403 }
404
405 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
406 struct spi_device *spi)
407 {
408 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
409
410 if (sdd->tgl_spi == spi)
411 sdd->tgl_spi = NULL;
412
413 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
414 }
415
416 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
417 {
418 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
419 void __iomem *regs = sdd->regs;
420 u32 val;
421
422 /* Disable Clock */
423 if (sci->clk_from_cmu) {
424 clk_disable(sdd->src_clk);
425 } else {
426 val = readl(regs + S3C64XX_SPI_CLK_CFG);
427 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
428 writel(val, regs + S3C64XX_SPI_CLK_CFG);
429 }
430
431 /* Set Polarity and Phase */
432 val = readl(regs + S3C64XX_SPI_CH_CFG);
433 val &= ~(S3C64XX_SPI_CH_SLAVE |
434 S3C64XX_SPI_CPOL_L |
435 S3C64XX_SPI_CPHA_B);
436
437 if (sdd->cur_mode & SPI_CPOL)
438 val |= S3C64XX_SPI_CPOL_L;
439
440 if (sdd->cur_mode & SPI_CPHA)
441 val |= S3C64XX_SPI_CPHA_B;
442
443 writel(val, regs + S3C64XX_SPI_CH_CFG);
444
445 /* Set Channel & DMA Mode */
446 val = readl(regs + S3C64XX_SPI_MODE_CFG);
447 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
448 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
449
450 switch (sdd->cur_bpw) {
451 case 32:
452 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
453 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
454 break;
455 case 16:
456 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
457 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
458 break;
459 default:
460 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
461 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
462 break;
463 }
464
465 writel(val, regs + S3C64XX_SPI_MODE_CFG);
466
467 if (sci->clk_from_cmu) {
468 /* Configure Clock */
469 /* There is half-multiplier before the SPI */
470 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
471 /* Enable Clock */
472 clk_enable(sdd->src_clk);
473 } else {
474 /* Configure Clock */
475 val = readl(regs + S3C64XX_SPI_CLK_CFG);
476 val &= ~S3C64XX_SPI_PSR_MASK;
477 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
478 & S3C64XX_SPI_PSR_MASK);
479 writel(val, regs + S3C64XX_SPI_CLK_CFG);
480
481 /* Enable Clock */
482 val = readl(regs + S3C64XX_SPI_CLK_CFG);
483 val |= S3C64XX_SPI_ENCLK_ENABLE;
484 writel(val, regs + S3C64XX_SPI_CLK_CFG);
485 }
486 }
487
488 static void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id,
489 int size, enum s3c2410_dma_buffresult res)
490 {
491 struct s3c64xx_spi_driver_data *sdd = buf_id;
492 unsigned long flags;
493
494 spin_lock_irqsave(&sdd->lock, flags);
495
496 if (res == S3C2410_RES_OK)
497 sdd->state &= ~RXBUSY;
498 else
499 dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size);
500
501 /* If the other done */
502 if (!(sdd->state & TXBUSY))
503 complete(&sdd->xfer_completion);
504
505 spin_unlock_irqrestore(&sdd->lock, flags);
506 }
507
508 static void s3c64xx_spi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id,
509 int size, enum s3c2410_dma_buffresult res)
510 {
511 struct s3c64xx_spi_driver_data *sdd = buf_id;
512 unsigned long flags;
513
514 spin_lock_irqsave(&sdd->lock, flags);
515
516 if (res == S3C2410_RES_OK)
517 sdd->state &= ~TXBUSY;
518 else
519 dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size);
520
521 /* If the other done */
522 if (!(sdd->state & RXBUSY))
523 complete(&sdd->xfer_completion);
524
525 spin_unlock_irqrestore(&sdd->lock, flags);
526 }
527
528 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
529
530 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
531 struct spi_message *msg)
532 {
533 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
534 struct device *dev = &sdd->pdev->dev;
535 struct spi_transfer *xfer;
536
537 if (msg->is_dma_mapped)
538 return 0;
539
540 /* First mark all xfer unmapped */
541 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
542 xfer->rx_dma = XFER_DMAADDR_INVALID;
543 xfer->tx_dma = XFER_DMAADDR_INVALID;
544 }
545
546 /* Map until end or first fail */
547 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
548
549 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
550 continue;
551
552 if (xfer->tx_buf != NULL) {
553 xfer->tx_dma = dma_map_single(dev,
554 (void *)xfer->tx_buf, xfer->len,
555 DMA_TO_DEVICE);
556 if (dma_mapping_error(dev, xfer->tx_dma)) {
557 dev_err(dev, "dma_map_single Tx failed\n");
558 xfer->tx_dma = XFER_DMAADDR_INVALID;
559 return -ENOMEM;
560 }
561 }
562
563 if (xfer->rx_buf != NULL) {
564 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
565 xfer->len, DMA_FROM_DEVICE);
566 if (dma_mapping_error(dev, xfer->rx_dma)) {
567 dev_err(dev, "dma_map_single Rx failed\n");
568 dma_unmap_single(dev, xfer->tx_dma,
569 xfer->len, DMA_TO_DEVICE);
570 xfer->tx_dma = XFER_DMAADDR_INVALID;
571 xfer->rx_dma = XFER_DMAADDR_INVALID;
572 return -ENOMEM;
573 }
574 }
575 }
576
577 return 0;
578 }
579
580 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
581 struct spi_message *msg)
582 {
583 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
584 struct device *dev = &sdd->pdev->dev;
585 struct spi_transfer *xfer;
586
587 if (msg->is_dma_mapped)
588 return;
589
590 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
591
592 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
593 continue;
594
595 if (xfer->rx_buf != NULL
596 && xfer->rx_dma != XFER_DMAADDR_INVALID)
597 dma_unmap_single(dev, xfer->rx_dma,
598 xfer->len, DMA_FROM_DEVICE);
599
600 if (xfer->tx_buf != NULL
601 && xfer->tx_dma != XFER_DMAADDR_INVALID)
602 dma_unmap_single(dev, xfer->tx_dma,
603 xfer->len, DMA_TO_DEVICE);
604 }
605 }
606
607 static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
608 struct spi_message *msg)
609 {
610 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
611 struct spi_device *spi = msg->spi;
612 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
613 struct spi_transfer *xfer;
614 int status = 0, cs_toggle = 0;
615 u32 speed;
616 u8 bpw;
617
618 /* If Master's(controller) state differs from that needed by Slave */
619 if (sdd->cur_speed != spi->max_speed_hz
620 || sdd->cur_mode != spi->mode
621 || sdd->cur_bpw != spi->bits_per_word) {
622 sdd->cur_bpw = spi->bits_per_word;
623 sdd->cur_speed = spi->max_speed_hz;
624 sdd->cur_mode = spi->mode;
625 s3c64xx_spi_config(sdd);
626 }
627
628 /* Map all the transfers if needed */
629 if (s3c64xx_spi_map_mssg(sdd, msg)) {
630 dev_err(&spi->dev,
631 "Xfer: Unable to map message buffers!\n");
632 status = -ENOMEM;
633 goto out;
634 }
635
636 /* Configure feedback delay */
637 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
638
639 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
640
641 unsigned long flags;
642 int use_dma;
643
644 INIT_COMPLETION(sdd->xfer_completion);
645
646 /* Only BPW and Speed may change across transfers */
647 bpw = xfer->bits_per_word ? : spi->bits_per_word;
648 speed = xfer->speed_hz ? : spi->max_speed_hz;
649
650 if (xfer->len % (bpw / 8)) {
651 dev_err(&spi->dev,
652 "Xfer length(%u) not a multiple of word size(%u)\n",
653 xfer->len, bpw / 8);
654 status = -EIO;
655 goto out;
656 }
657
658 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
659 sdd->cur_bpw = bpw;
660 sdd->cur_speed = speed;
661 s3c64xx_spi_config(sdd);
662 }
663
664 /* Polling method for xfers not bigger than FIFO capacity */
665 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
666 use_dma = 0;
667 else
668 use_dma = 1;
669
670 spin_lock_irqsave(&sdd->lock, flags);
671
672 /* Pending only which is to be done */
673 sdd->state &= ~RXBUSY;
674 sdd->state &= ~TXBUSY;
675
676 enable_datapath(sdd, spi, xfer, use_dma);
677
678 /* Slave Select */
679 enable_cs(sdd, spi);
680
681 /* Start the signals */
682 S3C64XX_SPI_ACT(sdd);
683
684 spin_unlock_irqrestore(&sdd->lock, flags);
685
686 status = wait_for_xfer(sdd, xfer, use_dma);
687
688 /* Quiese the signals */
689 S3C64XX_SPI_DEACT(sdd);
690
691 if (status) {
692 dev_err(&spi->dev, "I/O Error: "
693 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
694 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
695 (sdd->state & RXBUSY) ? 'f' : 'p',
696 (sdd->state & TXBUSY) ? 'f' : 'p',
697 xfer->len);
698
699 if (use_dma) {
700 if (xfer->tx_buf != NULL
701 && (sdd->state & TXBUSY))
702 s3c2410_dma_ctrl(sdd->tx_dmach,
703 S3C2410_DMAOP_FLUSH);
704 if (xfer->rx_buf != NULL
705 && (sdd->state & RXBUSY))
706 s3c2410_dma_ctrl(sdd->rx_dmach,
707 S3C2410_DMAOP_FLUSH);
708 }
709
710 goto out;
711 }
712
713 if (xfer->delay_usecs)
714 udelay(xfer->delay_usecs);
715
716 if (xfer->cs_change) {
717 /* Hint that the next mssg is gonna be
718 for the same device */
719 if (list_is_last(&xfer->transfer_list,
720 &msg->transfers))
721 cs_toggle = 1;
722 else
723 disable_cs(sdd, spi);
724 }
725
726 msg->actual_length += xfer->len;
727
728 flush_fifo(sdd);
729 }
730
731 out:
732 if (!cs_toggle || status)
733 disable_cs(sdd, spi);
734 else
735 sdd->tgl_spi = spi;
736
737 s3c64xx_spi_unmap_mssg(sdd, msg);
738
739 msg->status = status;
740
741 if (msg->complete)
742 msg->complete(msg->context);
743 }
744
745 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
746 {
747 if (s3c2410_dma_request(sdd->rx_dmach,
748 &s3c64xx_spi_dma_client, NULL) < 0) {
749 dev_err(&sdd->pdev->dev, "cannot get RxDMA\n");
750 return 0;
751 }
752 s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb);
753 s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW,
754 sdd->sfr_start + S3C64XX_SPI_RX_DATA);
755
756 if (s3c2410_dma_request(sdd->tx_dmach,
757 &s3c64xx_spi_dma_client, NULL) < 0) {
758 dev_err(&sdd->pdev->dev, "cannot get TxDMA\n");
759 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
760 return 0;
761 }
762 s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb);
763 s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM,
764 sdd->sfr_start + S3C64XX_SPI_TX_DATA);
765
766 return 1;
767 }
768
769 static void s3c64xx_spi_work(struct work_struct *work)
770 {
771 struct s3c64xx_spi_driver_data *sdd = container_of(work,
772 struct s3c64xx_spi_driver_data, work);
773 unsigned long flags;
774
775 /* Acquire DMA channels */
776 while (!acquire_dma(sdd))
777 msleep(10);
778
779 spin_lock_irqsave(&sdd->lock, flags);
780
781 while (!list_empty(&sdd->queue)
782 && !(sdd->state & SUSPND)) {
783
784 struct spi_message *msg;
785
786 msg = container_of(sdd->queue.next, struct spi_message, queue);
787
788 list_del_init(&msg->queue);
789
790 /* Set Xfer busy flag */
791 sdd->state |= SPIBUSY;
792
793 spin_unlock_irqrestore(&sdd->lock, flags);
794
795 handle_msg(sdd, msg);
796
797 spin_lock_irqsave(&sdd->lock, flags);
798
799 sdd->state &= ~SPIBUSY;
800 }
801
802 spin_unlock_irqrestore(&sdd->lock, flags);
803
804 /* Free DMA channels */
805 s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client);
806 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
807 }
808
809 static int s3c64xx_spi_transfer(struct spi_device *spi,
810 struct spi_message *msg)
811 {
812 struct s3c64xx_spi_driver_data *sdd;
813 unsigned long flags;
814
815 sdd = spi_master_get_devdata(spi->master);
816
817 spin_lock_irqsave(&sdd->lock, flags);
818
819 if (sdd->state & SUSPND) {
820 spin_unlock_irqrestore(&sdd->lock, flags);
821 return -ESHUTDOWN;
822 }
823
824 msg->status = -EINPROGRESS;
825 msg->actual_length = 0;
826
827 list_add_tail(&msg->queue, &sdd->queue);
828
829 queue_work(sdd->workqueue, &sdd->work);
830
831 spin_unlock_irqrestore(&sdd->lock, flags);
832
833 return 0;
834 }
835
836 /*
837 * Here we only check the validity of requested configuration
838 * and save the configuration in a local data-structure.
839 * The controller is actually configured only just before we
840 * get a message to transfer.
841 */
842 static int s3c64xx_spi_setup(struct spi_device *spi)
843 {
844 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
845 struct s3c64xx_spi_driver_data *sdd;
846 struct s3c64xx_spi_info *sci;
847 struct spi_message *msg;
848 unsigned long flags;
849 int err = 0;
850
851 if (cs == NULL || cs->set_level == NULL) {
852 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
853 return -ENODEV;
854 }
855
856 sdd = spi_master_get_devdata(spi->master);
857 sci = sdd->cntrlr_info;
858
859 spin_lock_irqsave(&sdd->lock, flags);
860
861 list_for_each_entry(msg, &sdd->queue, queue) {
862 /* Is some mssg is already queued for this device */
863 if (msg->spi == spi) {
864 dev_err(&spi->dev,
865 "setup: attempt while mssg in queue!\n");
866 spin_unlock_irqrestore(&sdd->lock, flags);
867 return -EBUSY;
868 }
869 }
870
871 if (sdd->state & SUSPND) {
872 spin_unlock_irqrestore(&sdd->lock, flags);
873 dev_err(&spi->dev,
874 "setup: SPI-%d not active!\n", spi->master->bus_num);
875 return -ESHUTDOWN;
876 }
877
878 spin_unlock_irqrestore(&sdd->lock, flags);
879
880 if (spi->bits_per_word != 8
881 && spi->bits_per_word != 16
882 && spi->bits_per_word != 32) {
883 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
884 spi->bits_per_word);
885 err = -EINVAL;
886 goto setup_exit;
887 }
888
889 /* Check if we can provide the requested rate */
890 if (!sci->clk_from_cmu) {
891 u32 psr, speed;
892
893 /* Max possible */
894 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
895
896 if (spi->max_speed_hz > speed)
897 spi->max_speed_hz = speed;
898
899 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
900 psr &= S3C64XX_SPI_PSR_MASK;
901 if (psr == S3C64XX_SPI_PSR_MASK)
902 psr--;
903
904 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
905 if (spi->max_speed_hz < speed) {
906 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
907 psr++;
908 } else {
909 err = -EINVAL;
910 goto setup_exit;
911 }
912 }
913
914 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
915 if (spi->max_speed_hz >= speed)
916 spi->max_speed_hz = speed;
917 else
918 err = -EINVAL;
919 }
920
921 setup_exit:
922
923 /* setup() returns with device de-selected */
924 disable_cs(sdd, spi);
925
926 return err;
927 }
928
929 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
930 {
931 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
932 void __iomem *regs = sdd->regs;
933 unsigned int val;
934
935 sdd->cur_speed = 0;
936
937 S3C64XX_SPI_DEACT(sdd);
938
939 /* Disable Interrupts - we use Polling if not DMA mode */
940 writel(0, regs + S3C64XX_SPI_INT_EN);
941
942 if (!sci->clk_from_cmu)
943 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
944 regs + S3C64XX_SPI_CLK_CFG);
945 writel(0, regs + S3C64XX_SPI_MODE_CFG);
946 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
947
948 /* Clear any irq pending bits */
949 writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
950 regs + S3C64XX_SPI_PENDING_CLR);
951
952 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
953
954 val = readl(regs + S3C64XX_SPI_MODE_CFG);
955 val &= ~S3C64XX_SPI_MODE_4BURST;
956 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
957 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
958 writel(val, regs + S3C64XX_SPI_MODE_CFG);
959
960 flush_fifo(sdd);
961 }
962
963 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
964 {
965 struct resource *mem_res, *dmatx_res, *dmarx_res;
966 struct s3c64xx_spi_driver_data *sdd;
967 struct s3c64xx_spi_info *sci;
968 struct spi_master *master;
969 int ret;
970
971 if (pdev->id < 0) {
972 dev_err(&pdev->dev,
973 "Invalid platform device id-%d\n", pdev->id);
974 return -ENODEV;
975 }
976
977 if (pdev->dev.platform_data == NULL) {
978 dev_err(&pdev->dev, "platform_data missing!\n");
979 return -ENODEV;
980 }
981
982 sci = pdev->dev.platform_data;
983 if (!sci->src_clk_name) {
984 dev_err(&pdev->dev,
985 "Board init must call s3c64xx_spi_set_info()\n");
986 return -EINVAL;
987 }
988
989 /* Check for availability of necessary resource */
990
991 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
992 if (dmatx_res == NULL) {
993 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
994 return -ENXIO;
995 }
996
997 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
998 if (dmarx_res == NULL) {
999 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
1000 return -ENXIO;
1001 }
1002
1003 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004 if (mem_res == NULL) {
1005 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1006 return -ENXIO;
1007 }
1008
1009 master = spi_alloc_master(&pdev->dev,
1010 sizeof(struct s3c64xx_spi_driver_data));
1011 if (master == NULL) {
1012 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1013 return -ENOMEM;
1014 }
1015
1016 platform_set_drvdata(pdev, master);
1017
1018 sdd = spi_master_get_devdata(master);
1019 sdd->master = master;
1020 sdd->cntrlr_info = sci;
1021 sdd->pdev = pdev;
1022 sdd->sfr_start = mem_res->start;
1023 sdd->tx_dmach = dmatx_res->start;
1024 sdd->rx_dmach = dmarx_res->start;
1025
1026 sdd->cur_bpw = 8;
1027
1028 master->bus_num = pdev->id;
1029 master->setup = s3c64xx_spi_setup;
1030 master->transfer = s3c64xx_spi_transfer;
1031 master->num_chipselect = sci->num_cs;
1032 master->dma_alignment = 8;
1033 /* the spi->mode bits understood by this driver: */
1034 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1035
1036 if (request_mem_region(mem_res->start,
1037 resource_size(mem_res), pdev->name) == NULL) {
1038 dev_err(&pdev->dev, "Req mem region failed\n");
1039 ret = -ENXIO;
1040 goto err0;
1041 }
1042
1043 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1044 if (sdd->regs == NULL) {
1045 dev_err(&pdev->dev, "Unable to remap IO\n");
1046 ret = -ENXIO;
1047 goto err1;
1048 }
1049
1050 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
1051 dev_err(&pdev->dev, "Unable to config gpio\n");
1052 ret = -EBUSY;
1053 goto err2;
1054 }
1055
1056 /* Setup clocks */
1057 sdd->clk = clk_get(&pdev->dev, "spi");
1058 if (IS_ERR(sdd->clk)) {
1059 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1060 ret = PTR_ERR(sdd->clk);
1061 goto err3;
1062 }
1063
1064 if (clk_enable(sdd->clk)) {
1065 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1066 ret = -EBUSY;
1067 goto err4;
1068 }
1069
1070 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1071 if (IS_ERR(sdd->src_clk)) {
1072 dev_err(&pdev->dev,
1073 "Unable to acquire clock '%s'\n", sci->src_clk_name);
1074 ret = PTR_ERR(sdd->src_clk);
1075 goto err5;
1076 }
1077
1078 if (clk_enable(sdd->src_clk)) {
1079 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n",
1080 sci->src_clk_name);
1081 ret = -EBUSY;
1082 goto err6;
1083 }
1084
1085 sdd->workqueue = create_singlethread_workqueue(
1086 dev_name(master->dev.parent));
1087 if (sdd->workqueue == NULL) {
1088 dev_err(&pdev->dev, "Unable to create workqueue\n");
1089 ret = -ENOMEM;
1090 goto err7;
1091 }
1092
1093 /* Setup Deufult Mode */
1094 s3c64xx_spi_hwinit(sdd, pdev->id);
1095
1096 spin_lock_init(&sdd->lock);
1097 init_completion(&sdd->xfer_completion);
1098 INIT_WORK(&sdd->work, s3c64xx_spi_work);
1099 INIT_LIST_HEAD(&sdd->queue);
1100
1101 if (spi_register_master(master)) {
1102 dev_err(&pdev->dev, "cannot register SPI master\n");
1103 ret = -EBUSY;
1104 goto err8;
1105 }
1106
1107 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1108 "with %d Slaves attached\n",
1109 pdev->id, master->num_chipselect);
1110 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1111 mem_res->end, mem_res->start,
1112 sdd->rx_dmach, sdd->tx_dmach);
1113
1114 return 0;
1115
1116 err8:
1117 destroy_workqueue(sdd->workqueue);
1118 err7:
1119 clk_disable(sdd->src_clk);
1120 err6:
1121 clk_put(sdd->src_clk);
1122 err5:
1123 clk_disable(sdd->clk);
1124 err4:
1125 clk_put(sdd->clk);
1126 err3:
1127 err2:
1128 iounmap((void *) sdd->regs);
1129 err1:
1130 release_mem_region(mem_res->start, resource_size(mem_res));
1131 err0:
1132 platform_set_drvdata(pdev, NULL);
1133 spi_master_put(master);
1134
1135 return ret;
1136 }
1137
1138 static int s3c64xx_spi_remove(struct platform_device *pdev)
1139 {
1140 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1141 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1142 struct resource *mem_res;
1143 unsigned long flags;
1144
1145 spin_lock_irqsave(&sdd->lock, flags);
1146 sdd->state |= SUSPND;
1147 spin_unlock_irqrestore(&sdd->lock, flags);
1148
1149 while (sdd->state & SPIBUSY)
1150 msleep(10);
1151
1152 spi_unregister_master(master);
1153
1154 destroy_workqueue(sdd->workqueue);
1155
1156 clk_disable(sdd->src_clk);
1157 clk_put(sdd->src_clk);
1158
1159 clk_disable(sdd->clk);
1160 clk_put(sdd->clk);
1161
1162 iounmap((void *) sdd->regs);
1163
1164 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1165 if (mem_res != NULL)
1166 release_mem_region(mem_res->start, resource_size(mem_res));
1167
1168 platform_set_drvdata(pdev, NULL);
1169 spi_master_put(master);
1170
1171 return 0;
1172 }
1173
1174 #ifdef CONFIG_PM
1175 static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1176 {
1177 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1178 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1179 unsigned long flags;
1180
1181 spin_lock_irqsave(&sdd->lock, flags);
1182 sdd->state |= SUSPND;
1183 spin_unlock_irqrestore(&sdd->lock, flags);
1184
1185 while (sdd->state & SPIBUSY)
1186 msleep(10);
1187
1188 /* Disable the clock */
1189 clk_disable(sdd->src_clk);
1190 clk_disable(sdd->clk);
1191
1192 sdd->cur_speed = 0; /* Output Clock is stopped */
1193
1194 return 0;
1195 }
1196
1197 static int s3c64xx_spi_resume(struct platform_device *pdev)
1198 {
1199 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1200 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1201 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1202 unsigned long flags;
1203
1204 sci->cfg_gpio(pdev);
1205
1206 /* Enable the clock */
1207 clk_enable(sdd->src_clk);
1208 clk_enable(sdd->clk);
1209
1210 s3c64xx_spi_hwinit(sdd, pdev->id);
1211
1212 spin_lock_irqsave(&sdd->lock, flags);
1213 sdd->state &= ~SUSPND;
1214 spin_unlock_irqrestore(&sdd->lock, flags);
1215
1216 return 0;
1217 }
1218 #else
1219 #define s3c64xx_spi_suspend NULL
1220 #define s3c64xx_spi_resume NULL
1221 #endif /* CONFIG_PM */
1222
1223 static struct platform_driver s3c64xx_spi_driver = {
1224 .driver = {
1225 .name = "s3c64xx-spi",
1226 .owner = THIS_MODULE,
1227 },
1228 .remove = s3c64xx_spi_remove,
1229 .suspend = s3c64xx_spi_suspend,
1230 .resume = s3c64xx_spi_resume,
1231 };
1232 MODULE_ALIAS("platform:s3c64xx-spi");
1233
1234 static int __init s3c64xx_spi_init(void)
1235 {
1236 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1237 }
1238 subsys_initcall(s3c64xx_spi_init);
1239
1240 static void __exit s3c64xx_spi_exit(void)
1241 {
1242 platform_driver_unregister(&s3c64xx_spi_driver);
1243 }
1244 module_exit(s3c64xx_spi_exit);
1245
1246 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1247 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1248 MODULE_LICENSE("GPL");
The kernel tree for Tao Ma.