drivers/staging/octeon/cvmx-spi.c

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 /*
  29  *
  30  * Support library for the SPI
  31  */
  32 #include <asm/octeon/octeon.h>
  33
  34 #include "cvmx-config.h"
  35
  36 #include "cvmx-pko.h"
  37 #include "cvmx-spi.h"
  38
  39 #include "cvmx-spxx-defs.h"
  40 #include "cvmx-stxx-defs.h"
  41 #include "cvmx-srxx-defs.h"
  42
  43 #define INVOKE_CB(function_p, args...)          \
  44         do {                                    \
  45                 if (function_p) {               \
  46                         res = function_p(args); \
  47                         if (res)                \
  48                                 return res;     \
  49                 }                               \
  50         } while (0)
  51
  52 #if CVMX_ENABLE_DEBUG_PRINTS
  53 static const char *modes[] =
  54     { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" };
  55 #endif
  56
  57 /* Default callbacks, can be overridden
  58  *  using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks
  59  */
  60 static cvmx_spi_callbacks_t cvmx_spi_callbacks = {
  61         .reset_cb = cvmx_spi_reset_cb,
  62         .calendar_setup_cb = cvmx_spi_calendar_setup_cb,
  63         .clock_detect_cb = cvmx_spi_clock_detect_cb,
  64         .training_cb = cvmx_spi_training_cb,
  65         .calendar_sync_cb = cvmx_spi_calendar_sync_cb,
  66         .interface_up_cb = cvmx_spi_interface_up_cb
  67 };
  68
  69 /**
  70  * Get current SPI4 initialization callbacks
  71  *
  72  * @callbacks:  Pointer to the callbacks structure.to fill
  73  *
  74  * Returns Pointer to cvmx_spi_callbacks_t structure.
  75  */
  76 void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks)
  77 {
  78         memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks));
  79 }
  80
  81 /**
  82  * Set new SPI4 initialization callbacks
  83  *
  84  * @new_callbacks:  Pointer to an updated callbacks structure.
  85  */
  86 void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks)
  87 {
  88         memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks));
  89 }
  90
  91 /**
  92  * Initialize and start the SPI interface.
  93  *
  94  * @interface: The identifier of the packet interface to configure and
  95  *                  use as a SPI interface.
  96  * @mode:      The operating mode for the SPI interface. The interface
  97  *                  can operate as a full duplex (both Tx and Rx data paths
  98  *                  active) or as a halfplex (either the Tx data path is
  99  *                  active or the Rx data path is active, but not both).
 100  * @timeout:   Timeout to wait for clock synchronization in seconds
 101  * @num_ports: Number of SPI ports to configure
 102  *
 103  * Returns Zero on success, negative of failure.
 104  */
 105 int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout,
 106                              int num_ports)
 107 {
 108         int res = -1;
 109
 110         if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
 111                 return res;
 112
 113         /* Callback to perform SPI4 reset */
 114         INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
 115
 116         /* Callback to perform calendar setup */
 117         INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode,
 118                   num_ports);
 119
 120         /* Callback to perform clock detection */
 121         INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
 122
 123         /* Callback to perform SPI4 link training */
 124         INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
 125
 126         /* Callback to perform calendar sync */
 127         INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
 128                   timeout);
 129
 130         /* Callback to handle interface coming up */
 131         INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
 132
 133         return res;
 134 }
 135
 136 /**
 137  * This routine restarts the SPI interface after it has lost synchronization
 138  * with its correspondent system.
 139  *
 140  * @interface: The identifier of the packet interface to configure and
 141  *                  use as a SPI interface.
 142  * @mode:      The operating mode for the SPI interface. The interface
 143  *                  can operate as a full duplex (both Tx and Rx data paths
 144  *                  active) or as a halfplex (either the Tx data path is
 145  *                  active or the Rx data path is active, but not both).
 146  * @timeout:   Timeout to wait for clock synchronization in seconds
 147  *
 148  * Returns Zero on success, negative of failure.
 149  */
 150 int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
 151 {
 152         int res = -1;
 153
 154         if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
 155                 return res;
 156
 157         cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]);
 158
 159         /* Callback to perform SPI4 reset */
 160         INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
 161
 162         /* NOTE: Calendar setup is not performed during restart */
 163         /*       Refer to cvmx_spi_start_interface() for the full sequence */
 164
 165         /* Callback to perform clock detection */
 166         INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
 167
 168         /* Callback to perform SPI4 link training */
 169         INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
 170
 171         /* Callback to perform calendar sync */
 172         INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
 173                   timeout);
 174
 175         /* Callback to handle interface coming up */
 176         INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
 177
 178         return res;
 179 }
 180
 181 /**
 182  * Callback to perform SPI4 reset
 183  *
 184  * @interface: The identifier of the packet interface to configure and
 185  *                  use as a SPI interface.
 186  * @mode:      The operating mode for the SPI interface. The interface
 187  *                  can operate as a full duplex (both Tx and Rx data paths
 188  *                  active) or as a halfplex (either the Tx data path is
 189  *                  active or the Rx data path is active, but not both).
 190  *
 191  * Returns Zero on success, non-zero error code on failure (will cause
 192  * SPI initialization to abort)
 193  */
 194 int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
 195 {
 196         union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl;
 197         union cvmx_spxx_clk_ctl spxx_clk_ctl;
 198         union cvmx_spxx_bist_stat spxx_bist_stat;
 199         union cvmx_spxx_int_msk spxx_int_msk;
 200         union cvmx_stxx_int_msk stxx_int_msk;
 201         union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
 202         int index;
 203         uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
 204
 205         /* Disable SPI error events while we run BIST */
 206         spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
 207         cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
 208         stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
 209         cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
 210
 211         /* Run BIST in the SPI interface */
 212         cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0);
 213         cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0);
 214         spxx_clk_ctl.u64 = 0;
 215         spxx_clk_ctl.s.runbist = 1;
 216         cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
 217         cvmx_wait(10 * MS);
 218         spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
 219         if (spxx_bist_stat.s.stat0)
 220                 cvmx_dprintf
 221                     ("ERROR SPI%d: BIST failed on receive datapath FIFO\n",
 222                      interface);
 223         if (spxx_bist_stat.s.stat1)
 224                 cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n",
 225                              interface);
 226         if (spxx_bist_stat.s.stat2)
 227                 cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n",
 228                              interface);
 229
 230         /* Clear the calendar table after BIST to fix parity errors */
 231         for (index = 0; index < 32; index++) {
 232                 union cvmx_srxx_spi4_calx srxx_spi4_calx;
 233                 union cvmx_stxx_spi4_calx stxx_spi4_calx;
 234
 235                 srxx_spi4_calx.u64 = 0;
 236                 srxx_spi4_calx.s.oddpar = 1;
 237                 cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
 238                                srxx_spi4_calx.u64);
 239
 240                 stxx_spi4_calx.u64 = 0;
 241                 stxx_spi4_calx.s.oddpar = 1;
 242                 cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
 243                                stxx_spi4_calx.u64);
 244         }
 245
 246         /* Re enable reporting of error interrupts */
 247         cvmx_write_csr(CVMX_SPXX_INT_REG(interface),
 248                        cvmx_read_csr(CVMX_SPXX_INT_REG(interface)));
 249         cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
 250         cvmx_write_csr(CVMX_STXX_INT_REG(interface),
 251                        cvmx_read_csr(CVMX_STXX_INT_REG(interface)));
 252         cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
 253
 254         /* Setup the CLKDLY right in the middle */
 255         spxx_clk_ctl.u64 = 0;
 256         spxx_clk_ctl.s.seetrn = 0;
 257         spxx_clk_ctl.s.clkdly = 0x10;
 258         spxx_clk_ctl.s.runbist = 0;
 259         spxx_clk_ctl.s.statdrv = 0;
 260         /* This should always be on the opposite edge as statdrv */
 261         spxx_clk_ctl.s.statrcv = 1;
 262         spxx_clk_ctl.s.sndtrn = 0;
 263         spxx_clk_ctl.s.drptrn = 0;
 264         spxx_clk_ctl.s.rcvtrn = 0;
 265         spxx_clk_ctl.s.srxdlck = 0;
 266         cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
 267         cvmx_wait(100 * MS);
 268
 269         /* Reset SRX0 DLL */
 270         spxx_clk_ctl.s.srxdlck = 1;
 271         cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
 272
 273         /* Waiting for Inf0 Spi4 RX DLL to lock */
 274         cvmx_wait(100 * MS);
 275
 276         /* Enable dynamic alignment */
 277         spxx_trn4_ctl.s.trntest = 0;
 278         spxx_trn4_ctl.s.jitter = 1;
 279         spxx_trn4_ctl.s.clr_boot = 1;
 280         spxx_trn4_ctl.s.set_boot = 0;
 281         if (OCTEON_IS_MODEL(OCTEON_CN58XX))
 282                 spxx_trn4_ctl.s.maxdist = 3;
 283         else
 284                 spxx_trn4_ctl.s.maxdist = 8;
 285         spxx_trn4_ctl.s.macro_en = 1;
 286         spxx_trn4_ctl.s.mux_en = 1;
 287         cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
 288
 289         spxx_dbg_deskew_ctl.u64 = 0;
 290         cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface),
 291                        spxx_dbg_deskew_ctl.u64);
 292
 293         return 0;
 294 }
 295
 296 /**
 297  * Callback to setup calendar and miscellaneous settings before clock detection
 298  *
 299  * @interface: The identifier of the packet interface to configure and
 300  *                  use as a SPI interface.
 301  * @mode:      The operating mode for the SPI interface. The interface
 302  *                  can operate as a full duplex (both Tx and Rx data paths
 303  *                  active) or as a halfplex (either the Tx data path is
 304  *                  active or the Rx data path is active, but not both).
 305  * @num_ports: Number of ports to configure on SPI
 306  *
 307  * Returns Zero on success, non-zero error code on failure (will cause
 308  * SPI initialization to abort)
 309  */
 310 int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
 311                                int num_ports)
 312 {
 313         int port;
 314         int index;
 315         if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
 316                 union cvmx_srxx_com_ctl srxx_com_ctl;
 317                 union cvmx_srxx_spi4_stat srxx_spi4_stat;
 318
 319                 /* SRX0 number of Ports */
 320                 srxx_com_ctl.u64 = 0;
 321                 srxx_com_ctl.s.prts = num_ports - 1;
 322                 srxx_com_ctl.s.st_en = 0;
 323                 srxx_com_ctl.s.inf_en = 0;
 324                 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
 325
 326                 /* SRX0 Calendar Table. This round robbins through all ports */
 327                 port = 0;
 328                 index = 0;
 329                 while (port < num_ports) {
 330                         union cvmx_srxx_spi4_calx srxx_spi4_calx;
 331                         srxx_spi4_calx.u64 = 0;
 332                         srxx_spi4_calx.s.prt0 = port++;
 333                         srxx_spi4_calx.s.prt1 = port++;
 334                         srxx_spi4_calx.s.prt2 = port++;
 335                         srxx_spi4_calx.s.prt3 = port++;
 336                         srxx_spi4_calx.s.oddpar =
 337                             ~(cvmx_dpop(srxx_spi4_calx.u64) & 1);
 338                         cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
 339                                        srxx_spi4_calx.u64);
 340                         index++;
 341                 }
 342                 srxx_spi4_stat.u64 = 0;
 343                 srxx_spi4_stat.s.len = num_ports;
 344                 srxx_spi4_stat.s.m = 1;
 345                 cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface),
 346                                srxx_spi4_stat.u64);
 347         }
 348
 349         if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
 350                 union cvmx_stxx_arb_ctl stxx_arb_ctl;
 351                 union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max;
 352                 union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh;
 353                 union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl;
 354                 union cvmx_stxx_spi4_stat stxx_spi4_stat;
 355                 union cvmx_stxx_spi4_dat stxx_spi4_dat;
 356
 357                 /* STX0 Config */
 358                 stxx_arb_ctl.u64 = 0;
 359                 stxx_arb_ctl.s.igntpa = 0;
 360                 stxx_arb_ctl.s.mintrn = 0;
 361                 cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64);
 362
 363                 gmxx_tx_spi_max.u64 = 0;
 364                 gmxx_tx_spi_max.s.max1 = 8;
 365                 gmxx_tx_spi_max.s.max2 = 4;
 366                 gmxx_tx_spi_max.s.slice = 0;
 367                 cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface),
 368                                gmxx_tx_spi_max.u64);
 369
 370                 gmxx_tx_spi_thresh.u64 = 0;
 371                 gmxx_tx_spi_thresh.s.thresh = 4;
 372                 cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface),
 373                                gmxx_tx_spi_thresh.u64);
 374
 375                 gmxx_tx_spi_ctl.u64 = 0;
 376                 gmxx_tx_spi_ctl.s.tpa_clr = 0;
 377                 gmxx_tx_spi_ctl.s.cont_pkt = 0;
 378                 cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface),
 379                                gmxx_tx_spi_ctl.u64);
 380
 381                 /* STX0 Training Control */
 382                 stxx_spi4_dat.u64 = 0;
 383                 /*Minimum needed by dynamic alignment */
 384                 stxx_spi4_dat.s.alpha = 32;
 385                 stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */
 386                 cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),
 387                                stxx_spi4_dat.u64);
 388
 389                 /* STX0 Calendar Table. This round robbins through all ports */
 390                 port = 0;
 391                 index = 0;
 392                 while (port < num_ports) {
 393                         union cvmx_stxx_spi4_calx stxx_spi4_calx;
 394                         stxx_spi4_calx.u64 = 0;
 395                         stxx_spi4_calx.s.prt0 = port++;
 396                         stxx_spi4_calx.s.prt1 = port++;
 397                         stxx_spi4_calx.s.prt2 = port++;
 398                         stxx_spi4_calx.s.prt3 = port++;
 399                         stxx_spi4_calx.s.oddpar =
 400                             ~(cvmx_dpop(stxx_spi4_calx.u64) & 1);
 401                         cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
 402                                        stxx_spi4_calx.u64);
 403                         index++;
 404                 }
 405                 stxx_spi4_stat.u64 = 0;
 406                 stxx_spi4_stat.s.len = num_ports;
 407                 stxx_spi4_stat.s.m = 1;
 408                 cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface),
 409                                stxx_spi4_stat.u64);
 410         }
 411
 412         return 0;
 413 }
 414
 415 /**
 416  * Callback to perform clock detection
 417  *
 418  * @interface: The identifier of the packet interface to configure and
 419  *                  use as a SPI interface.
 420  * @mode:      The operating mode for the SPI interface. The interface
 421  *                  can operate as a full duplex (both Tx and Rx data paths
 422  *                  active) or as a halfplex (either the Tx data path is
 423  *                  active or the Rx data path is active, but not both).
 424  * @timeout:   Timeout to wait for clock synchronization in seconds
 425  *
 426  * Returns Zero on success, non-zero error code on failure (will cause
 427  * SPI initialization to abort)
 428  */
 429 int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
 430 {
 431         int clock_transitions;
 432         union cvmx_spxx_clk_stat stat;
 433         uint64_t timeout_time;
 434         uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
 435
 436         /*
 437          * Regardless of operating mode, both Tx and Rx clocks must be
 438          * present for the SPI interface to operate.
 439          */
 440         cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface);
 441         timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
 442         /*
 443          * Require 100 clock transitions in order to avoid any noise
 444          * in the beginning.
 445          */
 446         clock_transitions = 100;
 447         do {
 448                 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
 449                 if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) {
 450                         /*
 451                          * We've seen a clock transition, so decrement
 452                          * the number we still need.
 453                          */
 454                         clock_transitions--;
 455                         cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
 456                         stat.s.s4clk0 = 0;
 457                         stat.s.s4clk1 = 0;
 458                 }
 459                 if (cvmx_get_cycle() > timeout_time) {
 460                         cvmx_dprintf("SPI%d: Timeout\n", interface);
 461                         return -1;
 462                 }
 463         } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0);
 464
 465         cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface);
 466         timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
 467         /*
 468          * Require 100 clock transitions in order to avoid any noise in the
 469          * beginning.
 470          */
 471         clock_transitions = 100;
 472         do {
 473                 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
 474                 if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) {
 475                         /*
 476                          * We've seen a clock transition, so decrement
 477                          * the number we still need
 478                          */
 479                         clock_transitions--;
 480                         cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
 481                         stat.s.d4clk0 = 0;
 482                         stat.s.d4clk1 = 0;
 483                 }
 484                 if (cvmx_get_cycle() > timeout_time) {
 485                         cvmx_dprintf("SPI%d: Timeout\n", interface);
 486                         return -1;
 487                 }
 488         } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0);
 489
 490         return 0;
 491 }
 492
 493 /**
 494  * Callback to perform link training
 495  *
 496  * @interface: The identifier of the packet interface to configure and
 497  *                  use as a SPI interface.
 498  * @mode:      The operating mode for the SPI interface. The interface
 499  *                  can operate as a full duplex (both Tx and Rx data paths
 500  *                  active) or as a halfplex (either the Tx data path is
 501  *                  active or the Rx data path is active, but not both).
 502  * @timeout:   Timeout to wait for link to be trained (in seconds)
 503  *
 504  * Returns Zero on success, non-zero error code on failure (will cause
 505  * SPI initialization to abort)
 506  */
 507 int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
 508 {
 509         union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
 510         union cvmx_spxx_clk_stat stat;
 511         uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
 512         uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
 513         int rx_training_needed;
 514
 515         /* SRX0 & STX0 Inf0 Links are configured - begin training */
 516         union cvmx_spxx_clk_ctl spxx_clk_ctl;
 517         spxx_clk_ctl.u64 = 0;
 518         spxx_clk_ctl.s.seetrn = 0;
 519         spxx_clk_ctl.s.clkdly = 0x10;
 520         spxx_clk_ctl.s.runbist = 0;
 521         spxx_clk_ctl.s.statdrv = 0;
 522         /* This should always be on the opposite edge as statdrv */
 523         spxx_clk_ctl.s.statrcv = 1;
 524         spxx_clk_ctl.s.sndtrn = 1;
 525         spxx_clk_ctl.s.drptrn = 1;
 526         spxx_clk_ctl.s.rcvtrn = 1;
 527         spxx_clk_ctl.s.srxdlck = 1;
 528         cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
 529         cvmx_wait(1000 * MS);
 530
 531         /* SRX0 clear the boot bit */
 532         spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
 533         spxx_trn4_ctl.s.clr_boot = 1;
 534         cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
 535
 536         /* Wait for the training sequence to complete */
 537         cvmx_dprintf("SPI%d: Waiting for training\n", interface);
 538         cvmx_wait(1000 * MS);
 539         /* Wait a really long time here */
 540         timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
 541         /*
 542          * The HRM says we must wait for 34 + 16 * MAXDIST training sequences.
 543          * We'll be pessimistic and wait for a lot more.
 544          */
 545         rx_training_needed = 500;
 546         do {
 547                 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
 548                 if (stat.s.srxtrn && rx_training_needed) {
 549                         rx_training_needed--;
 550                         cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
 551                         stat.s.srxtrn = 0;
 552                 }
 553                 if (cvmx_get_cycle() > timeout_time) {
 554                         cvmx_dprintf("SPI%d: Timeout\n", interface);
 555                         return -1;
 556                 }
 557         } while (stat.s.srxtrn == 0);
 558
 559         return 0;
 560 }
 561
 562 /**
 563  * Callback to perform calendar data synchronization
 564  *
 565  * @interface: The identifier of the packet interface to configure and
 566  *                  use as a SPI interface.
 567  * @mode:      The operating mode for the SPI interface. The interface
 568  *                  can operate as a full duplex (both Tx and Rx data paths
 569  *                  active) or as a halfplex (either the Tx data path is
 570  *                  active or the Rx data path is active, but not both).
 571  * @timeout:   Timeout to wait for calendar data in seconds
 572  *
 573  * Returns Zero on success, non-zero error code on failure (will cause
 574  * SPI initialization to abort)
 575  */
 576 int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
 577 {
 578         uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
 579         if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
 580                 /* SRX0 interface should be good, send calendar data */
 581                 union cvmx_srxx_com_ctl srxx_com_ctl;
 582                 cvmx_dprintf
 583                     ("SPI%d: Rx is synchronized, start sending calendar data\n",
 584                      interface);
 585                 srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
 586                 srxx_com_ctl.s.inf_en = 1;
 587                 srxx_com_ctl.s.st_en = 1;
 588                 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
 589         }
 590
 591         if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
 592                 /* STX0 has achieved sync */
 593                 /* The corespondant board should be sending calendar data */
 594                 /* Enable the STX0 STAT receiver. */
 595                 union cvmx_spxx_clk_stat stat;
 596                 uint64_t timeout_time;
 597                 union cvmx_stxx_com_ctl stxx_com_ctl;
 598                 stxx_com_ctl.u64 = 0;
 599                 stxx_com_ctl.s.st_en = 1;
 600                 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
 601
 602                 /* Waiting for calendar sync on STX0 STAT */
 603                 cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n",
 604                              interface, interface);
 605                 timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
 606                 /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */
 607                 do {
 608                         stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
 609                         if (cvmx_get_cycle() > timeout_time) {
 610                                 cvmx_dprintf("SPI%d: Timeout\n", interface);
 611                                 return -1;
 612                         }
 613                 } while (stat.s.stxcal == 0);
 614         }
 615
 616         return 0;
 617 }
 618
 619 /**
 620  * Callback to handle interface up
 621  *
 622  * @interface: The identifier of the packet interface to configure and
 623  *                  use as a SPI interface.
 624  * @mode:      The operating mode for the SPI interface. The interface
 625  *                  can operate as a full duplex (both Tx and Rx data paths
 626  *                  active) or as a halfplex (either the Tx data path is
 627  *                  active or the Rx data path is active, but not both).
 628  *
 629  * Returns Zero on success, non-zero error code on failure (will cause
 630  * SPI initialization to abort)
 631  */
 632 int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode)
 633 {
 634         union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min;
 635         union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max;
 636         union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber;
 637
 638         if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
 639                 union cvmx_srxx_com_ctl srxx_com_ctl;
 640                 srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
 641                 srxx_com_ctl.s.inf_en = 1;
 642                 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
 643                 cvmx_dprintf("SPI%d: Rx is now up\n", interface);
 644         }
 645
 646         if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
 647                 union cvmx_stxx_com_ctl stxx_com_ctl;
 648                 stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface));
 649                 stxx_com_ctl.s.inf_en = 1;
 650                 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
 651                 cvmx_dprintf("SPI%d: Tx is now up\n", interface);
 652         }
 653
 654         gmxx_rxx_frm_min.u64 = 0;
 655         gmxx_rxx_frm_min.s.len = 64;
 656         cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface),
 657                        gmxx_rxx_frm_min.u64);
 658         gmxx_rxx_frm_max.u64 = 0;
 659         gmxx_rxx_frm_max.s.len = 64 * 1024 - 4;
 660         cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface),
 661                        gmxx_rxx_frm_max.u64);
 662         gmxx_rxx_jabber.u64 = 0;
 663         gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4;
 664         cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64);
 665
 666         return 0;
 667 }