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ocfs2: Make the left masklogs compat.
[taoma-kernel.git] / drivers / usb / gadget / ci13xxx_udc.c
bloba1c67ae1572a2b8abf57ed9688d0a917a413aab7
1 /*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
25 *
26 * Compile Options
27 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
28 * - STALL_IN: non-empty bulk-in pipes cannot be halted
29 * if defined mass storage compliance succeeds but with warnings
30 * => case 4: Hi > Dn
31 * => case 5: Hi > Di
32 * => case 8: Hi <> Do
33 * if undefined usbtest 13 fails
34 * - TRACE: enable function tracing (depends on DEBUG)
35 *
36 * Main Features
37 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
38 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
39 * - Normal & LPM support
40 *
41 * USBTEST Report
42 * - OK: 0-12, 13 (STALL_IN defined) & 14
43 * - Not Supported: 15 & 16 (ISO)
44 *
45 * TODO List
46 * - OTG
47 * - Isochronous & Interrupt Traffic
48 * - Handle requests which spawns into several TDs
49 * - GET_STATUS(device) - always reports 0
50 * - Gadget API (majority of optional features)
51 * - Suspend & Remote Wakeup
52 */
53 #include <linux/delay.h>
54 #include <linux/device.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/init.h>
58 #include <linux/interrupt.h>
59 #include <linux/io.h>
60 #include <linux/irq.h>
61 #include <linux/kernel.h>
62 #include <linux/slab.h>
63 #include <linux/pm_runtime.h>
64 #include <linux/usb/ch9.h>
65 #include <linux/usb/gadget.h>
66 #include <linux/usb/otg.h>
67
68 #include "ci13xxx_udc.h"
69
70
71 /******************************************************************************
72 * DEFINE
73 *****************************************************************************/
74 /* ctrl register bank access */
75 static DEFINE_SPINLOCK(udc_lock);
76
77 /* control endpoint description */
78 static const struct usb_endpoint_descriptor
79 ctrl_endpt_out_desc = {
80 .bLength = USB_DT_ENDPOINT_SIZE,
81 .bDescriptorType = USB_DT_ENDPOINT,
82
83 .bEndpointAddress = USB_DIR_OUT,
84 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
85 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
86 };
87
88 static const struct usb_endpoint_descriptor
89 ctrl_endpt_in_desc = {
90 .bLength = USB_DT_ENDPOINT_SIZE,
91 .bDescriptorType = USB_DT_ENDPOINT,
92
93 .bEndpointAddress = USB_DIR_IN,
94 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
95 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
96 };
97
98 /* UDC descriptor */
99 static struct ci13xxx *_udc;
100
101 /* Interrupt statistics */
102 #define ISR_MASK 0x1F
103 static struct {
104 u32 test;
105 u32 ui;
106 u32 uei;
107 u32 pci;
108 u32 uri;
109 u32 sli;
110 u32 none;
111 struct {
112 u32 cnt;
113 u32 buf[ISR_MASK+1];
114 u32 idx;
115 } hndl;
116 } isr_statistics;
117
118 /**
119 * ffs_nr: find first (least significant) bit set
120 * @x: the word to search
121 *
122 * This function returns bit number (instead of position)
123 */
124 static int ffs_nr(u32 x)
125 {
126 int n = ffs(x);
127
128 return n ? n-1 : 32;
129 }
130
131 /******************************************************************************
132 * HW block
133 *****************************************************************************/
134 /* register bank descriptor */
135 static struct {
136 unsigned lpm; /* is LPM? */
137 void __iomem *abs; /* bus map offset */
138 void __iomem *cap; /* bus map offset + CAP offset + CAP data */
139 size_t size; /* bank size */
140 } hw_bank;
141
142 /* MSM specific */
143 #define ABS_AHBBURST (0x0090UL)
144 #define ABS_AHBMODE (0x0098UL)
145 /* UDC register map */
146 #define ABS_CAPLENGTH (0x100UL)
147 #define ABS_HCCPARAMS (0x108UL)
148 #define ABS_DCCPARAMS (0x124UL)
149 #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
150 /* offset to CAPLENTGH (addr + data) */
151 #define CAP_USBCMD (0x000UL)
152 #define CAP_USBSTS (0x004UL)
153 #define CAP_USBINTR (0x008UL)
154 #define CAP_DEVICEADDR (0x014UL)
155 #define CAP_ENDPTLISTADDR (0x018UL)
156 #define CAP_PORTSC (0x044UL)
157 #define CAP_DEVLC (0x084UL)
158 #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
159 #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
160 #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
161 #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
162 #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
163 #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
164 #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
165 #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
166
167 /* maximum number of enpoints: valid only after hw_device_reset() */
168 static unsigned hw_ep_max;
169
170 /**
171 * hw_ep_bit: calculates the bit number
172 * @num: endpoint number
173 * @dir: endpoint direction
174 *
175 * This function returns bit number
176 */
177 static inline int hw_ep_bit(int num, int dir)
178 {
179 return num + (dir ? 16 : 0);
180 }
181
182 /**
183 * hw_aread: reads from register bitfield
184 * @addr: address relative to bus map
185 * @mask: bitfield mask
186 *
187 * This function returns register bitfield data
188 */
189 static u32 hw_aread(u32 addr, u32 mask)
190 {
191 return ioread32(addr + hw_bank.abs) & mask;
192 }
193
194 /**
195 * hw_awrite: writes to register bitfield
196 * @addr: address relative to bus map
197 * @mask: bitfield mask
198 * @data: new data
199 */
200 static void hw_awrite(u32 addr, u32 mask, u32 data)
201 {
202 iowrite32(hw_aread(addr, ~mask) | (data & mask),
203 addr + hw_bank.abs);
204 }
205
206 /**
207 * hw_cread: reads from register bitfield
208 * @addr: address relative to CAP offset plus content
209 * @mask: bitfield mask
210 *
211 * This function returns register bitfield data
212 */
213 static u32 hw_cread(u32 addr, u32 mask)
214 {
215 return ioread32(addr + hw_bank.cap) & mask;
216 }
217
218 /**
219 * hw_cwrite: writes to register bitfield
220 * @addr: address relative to CAP offset plus content
221 * @mask: bitfield mask
222 * @data: new data
223 */
224 static void hw_cwrite(u32 addr, u32 mask, u32 data)
225 {
226 iowrite32(hw_cread(addr, ~mask) | (data & mask),
227 addr + hw_bank.cap);
228 }
229
230 /**
231 * hw_ctest_and_clear: tests & clears register bitfield
232 * @addr: address relative to CAP offset plus content
233 * @mask: bitfield mask
234 *
235 * This function returns register bitfield data
236 */
237 static u32 hw_ctest_and_clear(u32 addr, u32 mask)
238 {
239 u32 reg = hw_cread(addr, mask);
240
241 iowrite32(reg, addr + hw_bank.cap);
242 return reg;
243 }
244
245 /**
246 * hw_ctest_and_write: tests & writes register bitfield
247 * @addr: address relative to CAP offset plus content
248 * @mask: bitfield mask
249 * @data: new data
250 *
251 * This function returns register bitfield data
252 */
253 static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
254 {
255 u32 reg = hw_cread(addr, ~0);
256
257 iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
258 return (reg & mask) >> ffs_nr(mask);
259 }
260
261 static int hw_device_init(void __iomem *base)
262 {
263 u32 reg;
264
265 /* bank is a module variable */
266 hw_bank.abs = base;
267
268 hw_bank.cap = hw_bank.abs;
269 hw_bank.cap += ABS_CAPLENGTH;
270 hw_bank.cap += ioread8(hw_bank.cap);
271
272 reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
273 hw_bank.lpm = reg;
274 hw_bank.size = hw_bank.cap - hw_bank.abs;
275 hw_bank.size += CAP_LAST;
276 hw_bank.size /= sizeof(u32);
277
278 reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
279 hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
280
281 if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
282 return -ENODEV;
283
284 /* setup lock mode ? */
285
286 /* ENDPTSETUPSTAT is '0' by default */
287
288 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
289
290 return 0;
291 }
292 /**
293 * hw_device_reset: resets chip (execute without interruption)
294 * @base: register base address
295 *
296 * This function returns an error code
297 */
298 static int hw_device_reset(struct ci13xxx *udc)
299 {
300 /* should flush & stop before reset */
301 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
302 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
303
304 hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
305 while (hw_cread(CAP_USBCMD, USBCMD_RST))
306 udelay(10); /* not RTOS friendly */
307
308
309 if (udc->udc_driver->notify_event)
310 udc->udc_driver->notify_event(udc,
311 CI13XXX_CONTROLLER_RESET_EVENT);
312
313 if (udc->udc_driver->flags && CI13XXX_DISABLE_STREAMING)
314 hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
315
316 /* USBMODE should be configured step by step */
317 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
318 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
319 hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
320
321 if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
322 pr_err("cannot enter in device mode");
323 pr_err("lpm = %i", hw_bank.lpm);
324 return -ENODEV;
325 }
326
327 return 0;
328 }
329
330 /**
331 * hw_device_state: enables/disables interrupts & starts/stops device (execute
332 * without interruption)
333 * @dma: 0 => disable, !0 => enable and set dma engine
334 *
335 * This function returns an error code
336 */
337 static int hw_device_state(u32 dma)
338 {
339 if (dma) {
340 hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
341 /* interrupt, error, port change, reset, sleep/suspend */
342 hw_cwrite(CAP_USBINTR, ~0,
343 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
344 hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
345 } else {
346 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
347 hw_cwrite(CAP_USBINTR, ~0, 0);
348 }
349 return 0;
350 }
351
352 /**
353 * hw_ep_flush: flush endpoint fifo (execute without interruption)
354 * @num: endpoint number
355 * @dir: endpoint direction
356 *
357 * This function returns an error code
358 */
359 static int hw_ep_flush(int num, int dir)
360 {
361 int n = hw_ep_bit(num, dir);
362
363 do {
364 /* flush any pending transfer */
365 hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
366 while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
367 cpu_relax();
368 } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
369
370 return 0;
371 }
372
373 /**
374 * hw_ep_disable: disables endpoint (execute without interruption)
375 * @num: endpoint number
376 * @dir: endpoint direction
377 *
378 * This function returns an error code
379 */
380 static int hw_ep_disable(int num, int dir)
381 {
382 hw_ep_flush(num, dir);
383 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
384 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
385 return 0;
386 }
387
388 /**
389 * hw_ep_enable: enables endpoint (execute without interruption)
390 * @num: endpoint number
391 * @dir: endpoint direction
392 * @type: endpoint type
393 *
394 * This function returns an error code
395 */
396 static int hw_ep_enable(int num, int dir, int type)
397 {
398 u32 mask, data;
399
400 if (dir) {
401 mask = ENDPTCTRL_TXT; /* type */
402 data = type << ffs_nr(mask);
403
404 mask |= ENDPTCTRL_TXS; /* unstall */
405 mask |= ENDPTCTRL_TXR; /* reset data toggle */
406 data |= ENDPTCTRL_TXR;
407 mask |= ENDPTCTRL_TXE; /* enable */
408 data |= ENDPTCTRL_TXE;
409 } else {
410 mask = ENDPTCTRL_RXT; /* type */
411 data = type << ffs_nr(mask);
412
413 mask |= ENDPTCTRL_RXS; /* unstall */
414 mask |= ENDPTCTRL_RXR; /* reset data toggle */
415 data |= ENDPTCTRL_RXR;
416 mask |= ENDPTCTRL_RXE; /* enable */
417 data |= ENDPTCTRL_RXE;
418 }
419 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
420 return 0;
421 }
422
423 /**
424 * hw_ep_get_halt: return endpoint halt status
425 * @num: endpoint number
426 * @dir: endpoint direction
427 *
428 * This function returns 1 if endpoint halted
429 */
430 static int hw_ep_get_halt(int num, int dir)
431 {
432 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
433
434 return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
435 }
436
437 /**
438 * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
439 * @num: endpoint number
440 * @dir: endpoint direction
441 *
442 * This function returns true if endpoint primed
443 */
444 static int hw_ep_is_primed(int num, int dir)
445 {
446 u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
447
448 return test_bit(hw_ep_bit(num, dir), (void *)&reg);
449 }
450
451 /**
452 * hw_test_and_clear_setup_status: test & clear setup status (execute without
453 * interruption)
454 * @n: bit number (endpoint)
455 *
456 * This function returns setup status
457 */
458 static int hw_test_and_clear_setup_status(int n)
459 {
460 return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
461 }
462
463 /**
464 * hw_ep_prime: primes endpoint (execute without interruption)
465 * @num: endpoint number
466 * @dir: endpoint direction
467 * @is_ctrl: true if control endpoint
468 *
469 * This function returns an error code
470 */
471 static int hw_ep_prime(int num, int dir, int is_ctrl)
472 {
473 int n = hw_ep_bit(num, dir);
474
475 /* the caller should flush first */
476 if (hw_ep_is_primed(num, dir))
477 return -EBUSY;
478
479 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
480 return -EAGAIN;
481
482 hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
483
484 while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
485 cpu_relax();
486 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
487 return -EAGAIN;
488
489 /* status shoult be tested according with manual but it doesn't work */
490 return 0;
491 }
492
493 /**
494 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
495 * without interruption)
496 * @num: endpoint number
497 * @dir: endpoint direction
498 * @value: true => stall, false => unstall
499 *
500 * This function returns an error code
501 */
502 static int hw_ep_set_halt(int num, int dir, int value)
503 {
504 if (value != 0 && value != 1)
505 return -EINVAL;
506
507 do {
508 u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
509 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
510 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
511
512 /* data toggle - reserved for EP0 but it's in ESS */
513 hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
514
515 } while (value != hw_ep_get_halt(num, dir));
516
517 return 0;
518 }
519
520 /**
521 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
522 * interruption)
523 * @n: interrupt bit
524 *
525 * This function returns an error code
526 */
527 static int hw_intr_clear(int n)
528 {
529 if (n >= REG_BITS)
530 return -EINVAL;
531
532 hw_cwrite(CAP_USBINTR, BIT(n), 0);
533 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
534 return 0;
535 }
536
537 /**
538 * hw_intr_force: enables interrupt & forces interrupt status (execute without
539 * interruption)
540 * @n: interrupt bit
541 *
542 * This function returns an error code
543 */
544 static int hw_intr_force(int n)
545 {
546 if (n >= REG_BITS)
547 return -EINVAL;
548
549 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
550 hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
551 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
552 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
553 return 0;
554 }
555
556 /**
557 * hw_is_port_high_speed: test if port is high speed
558 *
559 * This function returns true if high speed port
560 */
561 static int hw_port_is_high_speed(void)
562 {
563 return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
564 hw_cread(CAP_PORTSC, PORTSC_HSP);
565 }
566
567 /**
568 * hw_port_test_get: reads port test mode value
569 *
570 * This function returns port test mode value
571 */
572 static u8 hw_port_test_get(void)
573 {
574 return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
575 }
576
577 /**
578 * hw_port_test_set: writes port test mode (execute without interruption)
579 * @mode: new value
580 *
581 * This function returns an error code
582 */
583 static int hw_port_test_set(u8 mode)
584 {
585 const u8 TEST_MODE_MAX = 7;
586
587 if (mode > TEST_MODE_MAX)
588 return -EINVAL;
589
590 hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
591 return 0;
592 }
593
594 /**
595 * hw_read_intr_enable: returns interrupt enable register
596 *
597 * This function returns register data
598 */
599 static u32 hw_read_intr_enable(void)
600 {
601 return hw_cread(CAP_USBINTR, ~0);
602 }
603
604 /**
605 * hw_read_intr_status: returns interrupt status register
606 *
607 * This function returns register data
608 */
609 static u32 hw_read_intr_status(void)
610 {
611 return hw_cread(CAP_USBSTS, ~0);
612 }
613
614 /**
615 * hw_register_read: reads all device registers (execute without interruption)
616 * @buf: destination buffer
617 * @size: buffer size
618 *
619 * This function returns number of registers read
620 */
621 static size_t hw_register_read(u32 *buf, size_t size)
622 {
623 unsigned i;
624
625 if (size > hw_bank.size)
626 size = hw_bank.size;
627
628 for (i = 0; i < size; i++)
629 buf[i] = hw_aread(i * sizeof(u32), ~0);
630
631 return size;
632 }
633
634 /**
635 * hw_register_write: writes to register
636 * @addr: register address
637 * @data: register value
638 *
639 * This function returns an error code
640 */
641 static int hw_register_write(u16 addr, u32 data)
642 {
643 /* align */
644 addr /= sizeof(u32);
645
646 if (addr >= hw_bank.size)
647 return -EINVAL;
648
649 /* align */
650 addr *= sizeof(u32);
651
652 hw_awrite(addr, ~0, data);
653 return 0;
654 }
655
656 /**
657 * hw_test_and_clear_complete: test & clear complete status (execute without
658 * interruption)
659 * @n: bit number (endpoint)
660 *
661 * This function returns complete status
662 */
663 static int hw_test_and_clear_complete(int n)
664 {
665 return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
666 }
667
668 /**
669 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
670 * without interruption)
671 *
672 * This function returns active interrutps
673 */
674 static u32 hw_test_and_clear_intr_active(void)
675 {
676 u32 reg = hw_read_intr_status() & hw_read_intr_enable();
677
678 hw_cwrite(CAP_USBSTS, ~0, reg);
679 return reg;
680 }
681
682 /**
683 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
684 * interruption)
685 *
686 * This function returns guard value
687 */
688 static int hw_test_and_clear_setup_guard(void)
689 {
690 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
691 }
692
693 /**
694 * hw_test_and_set_setup_guard: test & set setup guard (execute without
695 * interruption)
696 *
697 * This function returns guard value
698 */
699 static int hw_test_and_set_setup_guard(void)
700 {
701 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
702 }
703
704 /**
705 * hw_usb_set_address: configures USB address (execute without interruption)
706 * @value: new USB address
707 *
708 * This function returns an error code
709 */
710 static int hw_usb_set_address(u8 value)
711 {
712 /* advance */
713 hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
714 value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
715 return 0;
716 }
717
718 /**
719 * hw_usb_reset: restart device after a bus reset (execute without
720 * interruption)
721 *
722 * This function returns an error code
723 */
724 static int hw_usb_reset(void)
725 {
726 hw_usb_set_address(0);
727
728 /* ESS flushes only at end?!? */
729 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
730
731 /* clear setup token semaphores */
732 hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
733
734 /* clear complete status */
735 hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
736
737 /* wait until all bits cleared */
738 while (hw_cread(CAP_ENDPTPRIME, ~0))
739 udelay(10); /* not RTOS friendly */
740
741 /* reset all endpoints ? */
742
743 /* reset internal status and wait for further instructions
744 no need to verify the port reset status (ESS does it) */
745
746 return 0;
747 }
748
749 /******************************************************************************
750 * DBG block
751 *****************************************************************************/
752 /**
753 * show_device: prints information about device capabilities and status
754 *
755 * Check "device.h" for details
756 */
757 static ssize_t show_device(struct device *dev, struct device_attribute *attr,
758 char *buf)
759 {
760 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
761 struct usb_gadget *gadget = &udc->gadget;
762 int n = 0;
763
764 dbg_trace("[%s] %p\n", __func__, buf);
765 if (attr == NULL || buf == NULL) {
766 dev_err(dev, "[%s] EINVAL\n", __func__);
767 return 0;
768 }
769
770 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
771 gadget->speed);
772 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
773 gadget->is_dualspeed);
774 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
775 gadget->is_otg);
776 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
777 gadget->is_a_peripheral);
778 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
779 gadget->b_hnp_enable);
780 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
781 gadget->a_hnp_support);
782 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
783 gadget->a_alt_hnp_support);
784 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
785 (gadget->name ? gadget->name : ""));
786
787 return n;
788 }
789 static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
790
791 /**
792 * show_driver: prints information about attached gadget (if any)
793 *
794 * Check "device.h" for details
795 */
796 static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
797 char *buf)
798 {
799 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
800 struct usb_gadget_driver *driver = udc->driver;
801 int n = 0;
802
803 dbg_trace("[%s] %p\n", __func__, buf);
804 if (attr == NULL || buf == NULL) {
805 dev_err(dev, "[%s] EINVAL\n", __func__);
806 return 0;
807 }
808
809 if (driver == NULL)
810 return scnprintf(buf, PAGE_SIZE,
811 "There is no gadget attached!\n");
812
813 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
814 (driver->function ? driver->function : ""));
815 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
816 driver->speed);
817
818 return n;
819 }
820 static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
821
822 /* Maximum event message length */
823 #define DBG_DATA_MSG 64UL
824
825 /* Maximum event messages */
826 #define DBG_DATA_MAX 128UL
827
828 /* Event buffer descriptor */
829 static struct {
830 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
831 unsigned idx; /* index */
832 unsigned tty; /* print to console? */
833 rwlock_t lck; /* lock */
834 } dbg_data = {
835 .idx = 0,
836 .tty = 0,
837 .lck = __RW_LOCK_UNLOCKED(lck)
838 };
839
840 /**
841 * dbg_dec: decrements debug event index
842 * @idx: buffer index
843 */
844 static void dbg_dec(unsigned *idx)
845 {
846 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
847 }
848
849 /**
850 * dbg_inc: increments debug event index
851 * @idx: buffer index
852 */
853 static void dbg_inc(unsigned *idx)
854 {
855 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
856 }
857
858 /**
859 * dbg_print: prints the common part of the event
860 * @addr: endpoint address
861 * @name: event name
862 * @status: status
863 * @extra: extra information
864 */
865 static void dbg_print(u8 addr, const char *name, int status, const char *extra)
866 {
867 struct timeval tval;
868 unsigned int stamp;
869 unsigned long flags;
870
871 write_lock_irqsave(&dbg_data.lck, flags);
872
873 do_gettimeofday(&tval);
874 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
875 stamp = stamp * 1000000 + tval.tv_usec;
876
877 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
878 "%04X\t» %02X %-7.7s %4i «\t%s\n",
879 stamp, addr, name, status, extra);
880
881 dbg_inc(&dbg_data.idx);
882
883 write_unlock_irqrestore(&dbg_data.lck, flags);
884
885 if (dbg_data.tty != 0)
886 pr_notice("%04X\t» %02X %-7.7s %4i «\t%s\n",
887 stamp, addr, name, status, extra);
888 }
889
890 /**
891 * dbg_done: prints a DONE event
892 * @addr: endpoint address
893 * @td: transfer descriptor
894 * @status: status
895 */
896 static void dbg_done(u8 addr, const u32 token, int status)
897 {
898 char msg[DBG_DATA_MSG];
899
900 scnprintf(msg, sizeof(msg), "%d %02X",
901 (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
902 (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
903 dbg_print(addr, "DONE", status, msg);
904 }
905
906 /**
907 * dbg_event: prints a generic event
908 * @addr: endpoint address
909 * @name: event name
910 * @status: status
911 */
912 static void dbg_event(u8 addr, const char *name, int status)
913 {
914 if (name != NULL)
915 dbg_print(addr, name, status, "");
916 }
917
918 /*
919 * dbg_queue: prints a QUEUE event
920 * @addr: endpoint address
921 * @req: USB request
922 * @status: status
923 */
924 static void dbg_queue(u8 addr, const struct usb_request *req, int status)
925 {
926 char msg[DBG_DATA_MSG];
927
928 if (req != NULL) {
929 scnprintf(msg, sizeof(msg),
930 "%d %d", !req->no_interrupt, req->length);
931 dbg_print(addr, "QUEUE", status, msg);
932 }
933 }
934
935 /**
936 * dbg_setup: prints a SETUP event
937 * @addr: endpoint address
938 * @req: setup request
939 */
940 static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
941 {
942 char msg[DBG_DATA_MSG];
943
944 if (req != NULL) {
945 scnprintf(msg, sizeof(msg),
946 "%02X %02X %04X %04X %d", req->bRequestType,
947 req->bRequest, le16_to_cpu(req->wValue),
948 le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
949 dbg_print(addr, "SETUP", 0, msg);
950 }
951 }
952
953 /**
954 * show_events: displays the event buffer
955 *
956 * Check "device.h" for details
957 */
958 static ssize_t show_events(struct device *dev, struct device_attribute *attr,
959 char *buf)
960 {
961 unsigned long flags;
962 unsigned i, j, n = 0;
963
964 dbg_trace("[%s] %p\n", __func__, buf);
965 if (attr == NULL || buf == NULL) {
966 dev_err(dev, "[%s] EINVAL\n", __func__);
967 return 0;
968 }
969
970 read_lock_irqsave(&dbg_data.lck, flags);
971
972 i = dbg_data.idx;
973 for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
974 n += strlen(dbg_data.buf[i]);
975 if (n >= PAGE_SIZE) {
976 n -= strlen(dbg_data.buf[i]);
977 break;
978 }
979 }
980 for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
981 j += scnprintf(buf + j, PAGE_SIZE - j,
982 "%s", dbg_data.buf[i]);
983
984 read_unlock_irqrestore(&dbg_data.lck, flags);
985
986 return n;
987 }
988
989 /**
990 * store_events: configure if events are going to be also printed to console
991 *
992 * Check "device.h" for details
993 */
994 static ssize_t store_events(struct device *dev, struct device_attribute *attr,
995 const char *buf, size_t count)
996 {
997 unsigned tty;
998
999 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1000 if (attr == NULL || buf == NULL) {
1001 dev_err(dev, "[%s] EINVAL\n", __func__);
1002 goto done;
1003 }
1004
1005 if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
1006 dev_err(dev, "<1|0>: enable|disable console log\n");
1007 goto done;
1008 }
1009
1010 dbg_data.tty = tty;
1011 dev_info(dev, "tty = %u", dbg_data.tty);
1012
1013 done:
1014 return count;
1015 }
1016 static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
1017
1018 /**
1019 * show_inters: interrupt status, enable status and historic
1020 *
1021 * Check "device.h" for details
1022 */
1023 static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
1024 char *buf)
1025 {
1026 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1027 unsigned long flags;
1028 u32 intr;
1029 unsigned i, j, n = 0;
1030
1031 dbg_trace("[%s] %p\n", __func__, buf);
1032 if (attr == NULL || buf == NULL) {
1033 dev_err(dev, "[%s] EINVAL\n", __func__);
1034 return 0;
1035 }
1036
1037 spin_lock_irqsave(udc->lock, flags);
1038
1039 n += scnprintf(buf + n, PAGE_SIZE - n,
1040 "status = %08x\n", hw_read_intr_status());
1041 n += scnprintf(buf + n, PAGE_SIZE - n,
1042 "enable = %08x\n", hw_read_intr_enable());
1043
1044 n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
1045 isr_statistics.test);
1046 n += scnprintf(buf + n, PAGE_SIZE - n, "» ui = %d\n",
1047 isr_statistics.ui);
1048 n += scnprintf(buf + n, PAGE_SIZE - n, "» uei = %d\n",
1049 isr_statistics.uei);
1050 n += scnprintf(buf + n, PAGE_SIZE - n, "» pci = %d\n",
1051 isr_statistics.pci);
1052 n += scnprintf(buf + n, PAGE_SIZE - n, "» uri = %d\n",
1053 isr_statistics.uri);
1054 n += scnprintf(buf + n, PAGE_SIZE - n, "» sli = %d\n",
1055 isr_statistics.sli);
1056 n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
1057 isr_statistics.none);
1058 n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
1059 isr_statistics.hndl.cnt);
1060
1061 for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
1062 i &= ISR_MASK;
1063 intr = isr_statistics.hndl.buf[i];
1064
1065 if (USBi_UI & intr)
1066 n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
1067 intr &= ~USBi_UI;
1068 if (USBi_UEI & intr)
1069 n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
1070 intr &= ~USBi_UEI;
1071 if (USBi_PCI & intr)
1072 n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
1073 intr &= ~USBi_PCI;
1074 if (USBi_URI & intr)
1075 n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
1076 intr &= ~USBi_URI;
1077 if (USBi_SLI & intr)
1078 n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
1079 intr &= ~USBi_SLI;
1080 if (intr)
1081 n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
1082 if (isr_statistics.hndl.buf[i])
1083 n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
1084 }
1085
1086 spin_unlock_irqrestore(udc->lock, flags);
1087
1088 return n;
1089 }
1090
1091 /**
1092 * store_inters: enable & force or disable an individual interrutps
1093 * (to be used for test purposes only)
1094 *
1095 * Check "device.h" for details
1096 */
1097 static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
1098 const char *buf, size_t count)
1099 {
1100 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1101 unsigned long flags;
1102 unsigned en, bit;
1103
1104 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1105 if (attr == NULL || buf == NULL) {
1106 dev_err(dev, "[%s] EINVAL\n", __func__);
1107 goto done;
1108 }
1109
1110 if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
1111 dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
1112 goto done;
1113 }
1114
1115 spin_lock_irqsave(udc->lock, flags);
1116 if (en) {
1117 if (hw_intr_force(bit))
1118 dev_err(dev, "invalid bit number\n");
1119 else
1120 isr_statistics.test++;
1121 } else {
1122 if (hw_intr_clear(bit))
1123 dev_err(dev, "invalid bit number\n");
1124 }
1125 spin_unlock_irqrestore(udc->lock, flags);
1126
1127 done:
1128 return count;
1129 }
1130 static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
1131
1132 /**
1133 * show_port_test: reads port test mode
1134 *
1135 * Check "device.h" for details
1136 */
1137 static ssize_t show_port_test(struct device *dev,
1138 struct device_attribute *attr, char *buf)
1139 {
1140 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1141 unsigned long flags;
1142 unsigned mode;
1143
1144 dbg_trace("[%s] %p\n", __func__, buf);
1145 if (attr == NULL || buf == NULL) {
1146 dev_err(dev, "[%s] EINVAL\n", __func__);
1147 return 0;
1148 }
1149
1150 spin_lock_irqsave(udc->lock, flags);
1151 mode = hw_port_test_get();
1152 spin_unlock_irqrestore(udc->lock, flags);
1153
1154 return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
1155 }
1156
1157 /**
1158 * store_port_test: writes port test mode
1159 *
1160 * Check "device.h" for details
1161 */
1162 static ssize_t store_port_test(struct device *dev,
1163 struct device_attribute *attr,
1164 const char *buf, size_t count)
1165 {
1166 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1167 unsigned long flags;
1168 unsigned mode;
1169
1170 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1171 if (attr == NULL || buf == NULL) {
1172 dev_err(dev, "[%s] EINVAL\n", __func__);
1173 goto done;
1174 }
1175
1176 if (sscanf(buf, "%u", &mode) != 1) {
1177 dev_err(dev, "<mode>: set port test mode");
1178 goto done;
1179 }
1180
1181 spin_lock_irqsave(udc->lock, flags);
1182 if (hw_port_test_set(mode))
1183 dev_err(dev, "invalid mode\n");
1184 spin_unlock_irqrestore(udc->lock, flags);
1185
1186 done:
1187 return count;
1188 }
1189 static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
1190 show_port_test, store_port_test);
1191
1192 /**
1193 * show_qheads: DMA contents of all queue heads
1194 *
1195 * Check "device.h" for details
1196 */
1197 static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
1198 char *buf)
1199 {
1200 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1201 unsigned long flags;
1202 unsigned i, j, n = 0;
1203
1204 dbg_trace("[%s] %p\n", __func__, buf);
1205 if (attr == NULL || buf == NULL) {
1206 dev_err(dev, "[%s] EINVAL\n", __func__);
1207 return 0;
1208 }
1209
1210 spin_lock_irqsave(udc->lock, flags);
1211 for (i = 0; i < hw_ep_max/2; i++) {
1212 struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
1213 struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
1214 n += scnprintf(buf + n, PAGE_SIZE - n,
1215 "EP=%02i: RX=%08X TX=%08X\n",
1216 i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
1217 for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
1218 n += scnprintf(buf + n, PAGE_SIZE - n,
1219 " %04X: %08X %08X\n", j,
1220 *((u32 *)mEpRx->qh.ptr + j),
1221 *((u32 *)mEpTx->qh.ptr + j));
1222 }
1223 }
1224 spin_unlock_irqrestore(udc->lock, flags);
1225
1226 return n;
1227 }
1228 static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
1229
1230 /**
1231 * show_registers: dumps all registers
1232 *
1233 * Check "device.h" for details
1234 */
1235 static ssize_t show_registers(struct device *dev,
1236 struct device_attribute *attr, char *buf)
1237 {
1238 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1239 unsigned long flags;
1240 u32 dump[512];
1241 unsigned i, k, n = 0;
1242
1243 dbg_trace("[%s] %p\n", __func__, buf);
1244 if (attr == NULL || buf == NULL) {
1245 dev_err(dev, "[%s] EINVAL\n", __func__);
1246 return 0;
1247 }
1248
1249 spin_lock_irqsave(udc->lock, flags);
1250 k = hw_register_read(dump, sizeof(dump)/sizeof(u32));
1251 spin_unlock_irqrestore(udc->lock, flags);
1252
1253 for (i = 0; i < k; i++) {
1254 n += scnprintf(buf + n, PAGE_SIZE - n,
1255 "reg[0x%04X] = 0x%08X\n",
1256 i * (unsigned)sizeof(u32), dump[i]);
1257 }
1258
1259 return n;
1260 }
1261
1262 /**
1263 * store_registers: writes value to register address
1264 *
1265 * Check "device.h" for details
1266 */
1267 static ssize_t store_registers(struct device *dev,
1268 struct device_attribute *attr,
1269 const char *buf, size_t count)
1270 {
1271 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1272 unsigned long addr, data, flags;
1273
1274 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1275 if (attr == NULL || buf == NULL) {
1276 dev_err(dev, "[%s] EINVAL\n", __func__);
1277 goto done;
1278 }
1279
1280 if (sscanf(buf, "%li %li", &addr, &data) != 2) {
1281 dev_err(dev, "<addr> <data>: write data to register address");
1282 goto done;
1283 }
1284
1285 spin_lock_irqsave(udc->lock, flags);
1286 if (hw_register_write(addr, data))
1287 dev_err(dev, "invalid address range\n");
1288 spin_unlock_irqrestore(udc->lock, flags);
1289
1290 done:
1291 return count;
1292 }
1293 static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
1294 show_registers, store_registers);
1295
1296 /**
1297 * show_requests: DMA contents of all requests currently queued (all endpts)
1298 *
1299 * Check "device.h" for details
1300 */
1301 static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
1302 char *buf)
1303 {
1304 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1305 unsigned long flags;
1306 struct list_head *ptr = NULL;
1307 struct ci13xxx_req *req = NULL;
1308 unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
1309
1310 dbg_trace("[%s] %p\n", __func__, buf);
1311 if (attr == NULL || buf == NULL) {
1312 dev_err(dev, "[%s] EINVAL\n", __func__);
1313 return 0;
1314 }
1315
1316 spin_lock_irqsave(udc->lock, flags);
1317 for (i = 0; i < hw_ep_max; i++)
1318 list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
1319 {
1320 req = list_entry(ptr, struct ci13xxx_req, queue);
1321
1322 n += scnprintf(buf + n, PAGE_SIZE - n,
1323 "EP=%02i: TD=%08X %s\n",
1324 i % hw_ep_max/2, (u32)req->dma,
1325 ((i < hw_ep_max/2) ? "RX" : "TX"));
1326
1327 for (j = 0; j < qSize; j++)
1328 n += scnprintf(buf + n, PAGE_SIZE - n,
1329 " %04X: %08X\n", j,
1330 *((u32 *)req->ptr + j));
1331 }
1332 spin_unlock_irqrestore(udc->lock, flags);
1333
1334 return n;
1335 }
1336 static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
1337
1338 /**
1339 * dbg_create_files: initializes the attribute interface
1340 * @dev: device
1341 *
1342 * This function returns an error code
1343 */
1344 __maybe_unused static int dbg_create_files(struct device *dev)
1345 {
1346 int retval = 0;
1347
1348 if (dev == NULL)
1349 return -EINVAL;
1350 retval = device_create_file(dev, &dev_attr_device);
1351 if (retval)
1352 goto done;
1353 retval = device_create_file(dev, &dev_attr_driver);
1354 if (retval)
1355 goto rm_device;
1356 retval = device_create_file(dev, &dev_attr_events);
1357 if (retval)
1358 goto rm_driver;
1359 retval = device_create_file(dev, &dev_attr_inters);
1360 if (retval)
1361 goto rm_events;
1362 retval = device_create_file(dev, &dev_attr_port_test);
1363 if (retval)
1364 goto rm_inters;
1365 retval = device_create_file(dev, &dev_attr_qheads);
1366 if (retval)
1367 goto rm_port_test;
1368 retval = device_create_file(dev, &dev_attr_registers);
1369 if (retval)
1370 goto rm_qheads;
1371 retval = device_create_file(dev, &dev_attr_requests);
1372 if (retval)
1373 goto rm_registers;
1374 return 0;
1375
1376 rm_registers:
1377 device_remove_file(dev, &dev_attr_registers);
1378 rm_qheads:
1379 device_remove_file(dev, &dev_attr_qheads);
1380 rm_port_test:
1381 device_remove_file(dev, &dev_attr_port_test);
1382 rm_inters:
1383 device_remove_file(dev, &dev_attr_inters);
1384 rm_events:
1385 device_remove_file(dev, &dev_attr_events);
1386 rm_driver:
1387 device_remove_file(dev, &dev_attr_driver);
1388 rm_device:
1389 device_remove_file(dev, &dev_attr_device);
1390 done:
1391 return retval;
1392 }
1393
1394 /**
1395 * dbg_remove_files: destroys the attribute interface
1396 * @dev: device
1397 *
1398 * This function returns an error code
1399 */
1400 __maybe_unused static int dbg_remove_files(struct device *dev)
1401 {
1402 if (dev == NULL)
1403 return -EINVAL;
1404 device_remove_file(dev, &dev_attr_requests);
1405 device_remove_file(dev, &dev_attr_registers);
1406 device_remove_file(dev, &dev_attr_qheads);
1407 device_remove_file(dev, &dev_attr_port_test);
1408 device_remove_file(dev, &dev_attr_inters);
1409 device_remove_file(dev, &dev_attr_events);
1410 device_remove_file(dev, &dev_attr_driver);
1411 device_remove_file(dev, &dev_attr_device);
1412 return 0;
1413 }
1414
1415 /******************************************************************************
1416 * UTIL block
1417 *****************************************************************************/
1418 /**
1419 * _usb_addr: calculates endpoint address from direction & number
1420 * @ep: endpoint
1421 */
1422 static inline u8 _usb_addr(struct ci13xxx_ep *ep)
1423 {
1424 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
1425 }
1426
1427 /**
1428 * _hardware_queue: configures a request at hardware level
1429 * @gadget: gadget
1430 * @mEp: endpoint
1431 *
1432 * This function returns an error code
1433 */
1434 static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1435 {
1436 unsigned i;
1437
1438 trace("%p, %p", mEp, mReq);
1439
1440 /* don't queue twice */
1441 if (mReq->req.status == -EALREADY)
1442 return -EALREADY;
1443
1444 if (hw_ep_is_primed(mEp->num, mEp->dir))
1445 return -EBUSY;
1446
1447 mReq->req.status = -EALREADY;
1448
1449 if (mReq->req.length && !mReq->req.dma) {
1450 mReq->req.dma = \
1451 dma_map_single(mEp->device, mReq->req.buf,
1452 mReq->req.length, mEp->dir ?
1453 DMA_TO_DEVICE : DMA_FROM_DEVICE);
1454 if (mReq->req.dma == 0)
1455 return -ENOMEM;
1456
1457 mReq->map = 1;
1458 }
1459
1460 /*
1461 * TD configuration
1462 * TODO - handle requests which spawns into several TDs
1463 */
1464 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
1465 mReq->ptr->next |= TD_TERMINATE;
1466 mReq->ptr->token = mReq->req.length << ffs_nr(TD_TOTAL_BYTES);
1467 mReq->ptr->token &= TD_TOTAL_BYTES;
1468 mReq->ptr->token |= TD_IOC;
1469 mReq->ptr->token |= TD_STATUS_ACTIVE;
1470 mReq->ptr->page[0] = mReq->req.dma;
1471 for (i = 1; i < 5; i++)
1472 mReq->ptr->page[i] =
1473 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
1474
1475 /*
1476 * QH configuration
1477 * At this point it's guaranteed exclusive access to qhead
1478 * (endpt is not primed) so it's no need to use tripwire
1479 */
1480 mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
1481 mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
1482 if (mReq->req.zero == 0)
1483 mEp->qh.ptr->cap |= QH_ZLT;
1484 else
1485 mEp->qh.ptr->cap &= ~QH_ZLT;
1486
1487 wmb(); /* synchronize before ep prime */
1488
1489 return hw_ep_prime(mEp->num, mEp->dir,
1490 mEp->type == USB_ENDPOINT_XFER_CONTROL);
1491 }
1492
1493 /**
1494 * _hardware_dequeue: handles a request at hardware level
1495 * @gadget: gadget
1496 * @mEp: endpoint
1497 *
1498 * This function returns an error code
1499 */
1500 static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1501 {
1502 trace("%p, %p", mEp, mReq);
1503
1504 if (mReq->req.status != -EALREADY)
1505 return -EINVAL;
1506
1507 if (hw_ep_is_primed(mEp->num, mEp->dir))
1508 hw_ep_flush(mEp->num, mEp->dir);
1509
1510 mReq->req.status = 0;
1511
1512 if (mReq->map) {
1513 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
1514 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1515 mReq->req.dma = 0;
1516 mReq->map = 0;
1517 }
1518
1519 mReq->req.status = mReq->ptr->token & TD_STATUS;
1520 if ((TD_STATUS_ACTIVE & mReq->req.status) != 0)
1521 mReq->req.status = -ECONNRESET;
1522 else if ((TD_STATUS_HALTED & mReq->req.status) != 0)
1523 mReq->req.status = -1;
1524 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
1525 mReq->req.status = -1;
1526 else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
1527 mReq->req.status = -1;
1528
1529 mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
1530 mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
1531 mReq->req.actual = mReq->req.length - mReq->req.actual;
1532 mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
1533
1534 return mReq->req.actual;
1535 }
1536
1537 /**
1538 * _ep_nuke: dequeues all endpoint requests
1539 * @mEp: endpoint
1540 *
1541 * This function returns an error code
1542 * Caller must hold lock
1543 */
1544 static int _ep_nuke(struct ci13xxx_ep *mEp)
1545 __releases(mEp->lock)
1546 __acquires(mEp->lock)
1547 {
1548 trace("%p", mEp);
1549
1550 if (mEp == NULL)
1551 return -EINVAL;
1552
1553 hw_ep_flush(mEp->num, mEp->dir);
1554
1555 while (!list_empty(&mEp->qh.queue)) {
1556
1557 /* pop oldest request */
1558 struct ci13xxx_req *mReq = \
1559 list_entry(mEp->qh.queue.next,
1560 struct ci13xxx_req, queue);
1561 list_del_init(&mReq->queue);
1562 mReq->req.status = -ESHUTDOWN;
1563
1564 if (mReq->req.complete != NULL) {
1565 spin_unlock(mEp->lock);
1566 mReq->req.complete(&mEp->ep, &mReq->req);
1567 spin_lock(mEp->lock);
1568 }
1569 }
1570 return 0;
1571 }
1572
1573 /**
1574 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
1575 * @gadget: gadget
1576 *
1577 * This function returns an error code
1578 * Caller must hold lock
1579 */
1580 static int _gadget_stop_activity(struct usb_gadget *gadget)
1581 {
1582 struct usb_ep *ep;
1583 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
1584
1585 trace("%p", gadget);
1586
1587 if (gadget == NULL)
1588 return -EINVAL;
1589
1590 /* flush all endpoints */
1591 gadget_for_each_ep(ep, gadget) {
1592 usb_ep_fifo_flush(ep);
1593 }
1594 usb_ep_fifo_flush(&udc->ep0out.ep);
1595 usb_ep_fifo_flush(&udc->ep0in.ep);
1596
1597 udc->driver->disconnect(gadget);
1598
1599 /* make sure to disable all endpoints */
1600 gadget_for_each_ep(ep, gadget) {
1601 usb_ep_disable(ep);
1602 }
1603 usb_ep_disable(&udc->ep0out.ep);
1604 usb_ep_disable(&udc->ep0in.ep);
1605
1606 if (udc->status != NULL) {
1607 usb_ep_free_request(&udc->ep0in.ep, udc->status);
1608 udc->status = NULL;
1609 }
1610
1611 return 0;
1612 }
1613
1614 /******************************************************************************
1615 * ISR block
1616 *****************************************************************************/
1617 /**
1618 * isr_reset_handler: USB reset interrupt handler
1619 * @udc: UDC device
1620 *
1621 * This function resets USB engine after a bus reset occurred
1622 */
1623 static void isr_reset_handler(struct ci13xxx *udc)
1624 __releases(udc->lock)
1625 __acquires(udc->lock)
1626 {
1627 int retval;
1628
1629 trace("%p", udc);
1630
1631 if (udc == NULL) {
1632 err("EINVAL");
1633 return;
1634 }
1635
1636 dbg_event(0xFF, "BUS RST", 0);
1637
1638 spin_unlock(udc->lock);
1639 retval = _gadget_stop_activity(&udc->gadget);
1640 if (retval)
1641 goto done;
1642
1643 retval = hw_usb_reset();
1644 if (retval)
1645 goto done;
1646
1647 retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
1648 if (retval)
1649 goto done;
1650
1651 retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
1652 if (!retval) {
1653 udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
1654 if (udc->status == NULL) {
1655 usb_ep_disable(&udc->ep0out.ep);
1656 retval = -ENOMEM;
1657 }
1658 }
1659 spin_lock(udc->lock);
1660
1661 done:
1662 if (retval)
1663 err("error: %i", retval);
1664 }
1665
1666 /**
1667 * isr_get_status_complete: get_status request complete function
1668 * @ep: endpoint
1669 * @req: request handled
1670 *
1671 * Caller must release lock
1672 */
1673 static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
1674 {
1675 trace("%p, %p", ep, req);
1676
1677 if (ep == NULL || req == NULL) {
1678 err("EINVAL");
1679 return;
1680 }
1681
1682 kfree(req->buf);
1683 usb_ep_free_request(ep, req);
1684 }
1685
1686 /**
1687 * isr_get_status_response: get_status request response
1688 * @udc: udc struct
1689 * @setup: setup request packet
1690 *
1691 * This function returns an error code
1692 */
1693 static int isr_get_status_response(struct ci13xxx *udc,
1694 struct usb_ctrlrequest *setup)
1695 __releases(mEp->lock)
1696 __acquires(mEp->lock)
1697 {
1698 struct ci13xxx_ep *mEp = &udc->ep0in;
1699 struct usb_request *req = NULL;
1700 gfp_t gfp_flags = GFP_ATOMIC;
1701 int dir, num, retval;
1702
1703 trace("%p, %p", mEp, setup);
1704
1705 if (mEp == NULL || setup == NULL)
1706 return -EINVAL;
1707
1708 spin_unlock(mEp->lock);
1709 req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
1710 spin_lock(mEp->lock);
1711 if (req == NULL)
1712 return -ENOMEM;
1713
1714 req->complete = isr_get_status_complete;
1715 req->length = 2;
1716 req->buf = kzalloc(req->length, gfp_flags);
1717 if (req->buf == NULL) {
1718 retval = -ENOMEM;
1719 goto err_free_req;
1720 }
1721
1722 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1723 /* TODO: D1 - Remote Wakeup; D0 - Self Powered */
1724 retval = 0;
1725 } else if ((setup->bRequestType & USB_RECIP_MASK) \
1726 == USB_RECIP_ENDPOINT) {
1727 dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
1728 TX : RX;
1729 num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
1730 *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
1731 }
1732 /* else do nothing; reserved for future use */
1733
1734 spin_unlock(mEp->lock);
1735 retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
1736 spin_lock(mEp->lock);
1737 if (retval)
1738 goto err_free_buf;
1739
1740 return 0;
1741
1742 err_free_buf:
1743 kfree(req->buf);
1744 err_free_req:
1745 spin_unlock(mEp->lock);
1746 usb_ep_free_request(&mEp->ep, req);
1747 spin_lock(mEp->lock);
1748 return retval;
1749 }
1750
1751 /**
1752 * isr_setup_status_phase: queues the status phase of a setup transation
1753 * @udc: udc struct
1754 *
1755 * This function returns an error code
1756 */
1757 static int isr_setup_status_phase(struct ci13xxx *udc)
1758 __releases(mEp->lock)
1759 __acquires(mEp->lock)
1760 {
1761 int retval;
1762 struct ci13xxx_ep *mEp;
1763
1764 trace("%p", udc);
1765
1766 mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
1767
1768 spin_unlock(mEp->lock);
1769 retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
1770 spin_lock(mEp->lock);
1771
1772 return retval;
1773 }
1774
1775 /**
1776 * isr_tr_complete_low: transaction complete low level handler
1777 * @mEp: endpoint
1778 *
1779 * This function returns an error code
1780 * Caller must hold lock
1781 */
1782 static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
1783 __releases(mEp->lock)
1784 __acquires(mEp->lock)
1785 {
1786 struct ci13xxx_req *mReq;
1787 int retval;
1788
1789 trace("%p", mEp);
1790
1791 if (list_empty(&mEp->qh.queue))
1792 return -EINVAL;
1793
1794 /* pop oldest request */
1795 mReq = list_entry(mEp->qh.queue.next,
1796 struct ci13xxx_req, queue);
1797 list_del_init(&mReq->queue);
1798
1799 retval = _hardware_dequeue(mEp, mReq);
1800 if (retval < 0) {
1801 dbg_event(_usb_addr(mEp), "DONE", retval);
1802 goto done;
1803 }
1804
1805 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
1806
1807 if (!list_empty(&mEp->qh.queue)) {
1808 struct ci13xxx_req* mReqEnq;
1809
1810 mReqEnq = list_entry(mEp->qh.queue.next,
1811 struct ci13xxx_req, queue);
1812 _hardware_enqueue(mEp, mReqEnq);
1813 }
1814
1815 if (mReq->req.complete != NULL) {
1816 spin_unlock(mEp->lock);
1817 mReq->req.complete(&mEp->ep, &mReq->req);
1818 spin_lock(mEp->lock);
1819 }
1820
1821 done:
1822 return retval;
1823 }
1824
1825 /**
1826 * isr_tr_complete_handler: transaction complete interrupt handler
1827 * @udc: UDC descriptor
1828 *
1829 * This function handles traffic events
1830 */
1831 static void isr_tr_complete_handler(struct ci13xxx *udc)
1832 __releases(udc->lock)
1833 __acquires(udc->lock)
1834 {
1835 unsigned i;
1836
1837 trace("%p", udc);
1838
1839 if (udc == NULL) {
1840 err("EINVAL");
1841 return;
1842 }
1843
1844 for (i = 0; i < hw_ep_max; i++) {
1845 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1846 int type, num, err = -EINVAL;
1847 struct usb_ctrlrequest req;
1848
1849 if (mEp->desc == NULL)
1850 continue; /* not configured */
1851
1852 if (hw_test_and_clear_complete(i)) {
1853 err = isr_tr_complete_low(mEp);
1854 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
1855 if (err > 0) /* needs status phase */
1856 err = isr_setup_status_phase(udc);
1857 if (err < 0) {
1858 dbg_event(_usb_addr(mEp),
1859 "ERROR", err);
1860 spin_unlock(udc->lock);
1861 if (usb_ep_set_halt(&mEp->ep))
1862 err("error: ep_set_halt");
1863 spin_lock(udc->lock);
1864 }
1865 }
1866 }
1867
1868 if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
1869 !hw_test_and_clear_setup_status(i))
1870 continue;
1871
1872 if (i != 0) {
1873 warn("ctrl traffic received at endpoint");
1874 continue;
1875 }
1876
1877 /*
1878 * Flush data and handshake transactions of previous
1879 * setup packet.
1880 */
1881 _ep_nuke(&udc->ep0out);
1882 _ep_nuke(&udc->ep0in);
1883
1884 /* read_setup_packet */
1885 do {
1886 hw_test_and_set_setup_guard();
1887 memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
1888 } while (!hw_test_and_clear_setup_guard());
1889
1890 type = req.bRequestType;
1891
1892 udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
1893
1894 dbg_setup(_usb_addr(mEp), &req);
1895
1896 switch (req.bRequest) {
1897 case USB_REQ_CLEAR_FEATURE:
1898 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1899 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
1900 goto delegate;
1901 if (req.wLength != 0)
1902 break;
1903 num = le16_to_cpu(req.wIndex);
1904 num &= USB_ENDPOINT_NUMBER_MASK;
1905 if (!udc->ci13xxx_ep[num].wedge) {
1906 spin_unlock(udc->lock);
1907 err = usb_ep_clear_halt(
1908 &udc->ci13xxx_ep[num].ep);
1909 spin_lock(udc->lock);
1910 if (err)
1911 break;
1912 }
1913 err = isr_setup_status_phase(udc);
1914 break;
1915 case USB_REQ_GET_STATUS:
1916 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
1917 type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
1918 type != (USB_DIR_IN|USB_RECIP_INTERFACE))
1919 goto delegate;
1920 if (le16_to_cpu(req.wLength) != 2 ||
1921 le16_to_cpu(req.wValue) != 0)
1922 break;
1923 err = isr_get_status_response(udc, &req);
1924 break;
1925 case USB_REQ_SET_ADDRESS:
1926 if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
1927 goto delegate;
1928 if (le16_to_cpu(req.wLength) != 0 ||
1929 le16_to_cpu(req.wIndex) != 0)
1930 break;
1931 err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
1932 if (err)
1933 break;
1934 err = isr_setup_status_phase(udc);
1935 break;
1936 case USB_REQ_SET_FEATURE:
1937 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1938 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
1939 goto delegate;
1940 if (req.wLength != 0)
1941 break;
1942 num = le16_to_cpu(req.wIndex);
1943 num &= USB_ENDPOINT_NUMBER_MASK;
1944
1945 spin_unlock(udc->lock);
1946 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
1947 spin_lock(udc->lock);
1948 if (err)
1949 break;
1950 err = isr_setup_status_phase(udc);
1951 break;
1952 default:
1953 delegate:
1954 if (req.wLength == 0) /* no data phase */
1955 udc->ep0_dir = TX;
1956
1957 spin_unlock(udc->lock);
1958 err = udc->driver->setup(&udc->gadget, &req);
1959 spin_lock(udc->lock);
1960 break;
1961 }
1962
1963 if (err < 0) {
1964 dbg_event(_usb_addr(mEp), "ERROR", err);
1965
1966 spin_unlock(udc->lock);
1967 if (usb_ep_set_halt(&mEp->ep))
1968 err("error: ep_set_halt");
1969 spin_lock(udc->lock);
1970 }
1971 }
1972 }
1973
1974 /******************************************************************************
1975 * ENDPT block
1976 *****************************************************************************/
1977 /**
1978 * ep_enable: configure endpoint, making it usable
1979 *
1980 * Check usb_ep_enable() at "usb_gadget.h" for details
1981 */
1982 static int ep_enable(struct usb_ep *ep,
1983 const struct usb_endpoint_descriptor *desc)
1984 {
1985 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1986 int retval = 0;
1987 unsigned long flags;
1988
1989 trace("%p, %p", ep, desc);
1990
1991 if (ep == NULL || desc == NULL)
1992 return -EINVAL;
1993
1994 spin_lock_irqsave(mEp->lock, flags);
1995
1996 /* only internal SW should enable ctrl endpts */
1997
1998 mEp->desc = desc;
1999
2000 if (!list_empty(&mEp->qh.queue))
2001 warn("enabling a non-empty endpoint!");
2002
2003 mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
2004 mEp->num = usb_endpoint_num(desc);
2005 mEp->type = usb_endpoint_type(desc);
2006
2007 mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
2008
2009 dbg_event(_usb_addr(mEp), "ENABLE", 0);
2010
2011 mEp->qh.ptr->cap = 0;
2012
2013 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2014 mEp->qh.ptr->cap |= QH_IOS;
2015 else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
2016 mEp->qh.ptr->cap &= ~QH_MULT;
2017 else
2018 mEp->qh.ptr->cap &= ~QH_ZLT;
2019
2020 mEp->qh.ptr->cap |=
2021 (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
2022 mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
2023
2024 retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
2025
2026 spin_unlock_irqrestore(mEp->lock, flags);
2027 return retval;
2028 }
2029
2030 /**
2031 * ep_disable: endpoint is no longer usable
2032 *
2033 * Check usb_ep_disable() at "usb_gadget.h" for details
2034 */
2035 static int ep_disable(struct usb_ep *ep)
2036 {
2037 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2038 int direction, retval = 0;
2039 unsigned long flags;
2040
2041 trace("%p", ep);
2042
2043 if (ep == NULL)
2044 return -EINVAL;
2045 else if (mEp->desc == NULL)
2046 return -EBUSY;
2047
2048 spin_lock_irqsave(mEp->lock, flags);
2049
2050 /* only internal SW should disable ctrl endpts */
2051
2052 direction = mEp->dir;
2053 do {
2054 dbg_event(_usb_addr(mEp), "DISABLE", 0);
2055
2056 retval |= _ep_nuke(mEp);
2057 retval |= hw_ep_disable(mEp->num, mEp->dir);
2058
2059 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2060 mEp->dir = (mEp->dir == TX) ? RX : TX;
2061
2062 } while (mEp->dir != direction);
2063
2064 mEp->desc = NULL;
2065
2066 spin_unlock_irqrestore(mEp->lock, flags);
2067 return retval;
2068 }
2069
2070 /**
2071 * ep_alloc_request: allocate a request object to use with this endpoint
2072 *
2073 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
2074 */
2075 static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
2076 {
2077 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2078 struct ci13xxx_req *mReq = NULL;
2079
2080 trace("%p, %i", ep, gfp_flags);
2081
2082 if (ep == NULL) {
2083 err("EINVAL");
2084 return NULL;
2085 }
2086
2087 mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
2088 if (mReq != NULL) {
2089 INIT_LIST_HEAD(&mReq->queue);
2090
2091 mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
2092 &mReq->dma);
2093 if (mReq->ptr == NULL) {
2094 kfree(mReq);
2095 mReq = NULL;
2096 }
2097 }
2098
2099 dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
2100
2101 return (mReq == NULL) ? NULL : &mReq->req;
2102 }
2103
2104 /**
2105 * ep_free_request: frees a request object
2106 *
2107 * Check usb_ep_free_request() at "usb_gadget.h" for details
2108 */
2109 static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
2110 {
2111 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2112 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2113 unsigned long flags;
2114
2115 trace("%p, %p", ep, req);
2116
2117 if (ep == NULL || req == NULL) {
2118 err("EINVAL");
2119 return;
2120 } else if (!list_empty(&mReq->queue)) {
2121 err("EBUSY");
2122 return;
2123 }
2124
2125 spin_lock_irqsave(mEp->lock, flags);
2126
2127 if (mReq->ptr)
2128 dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
2129 kfree(mReq);
2130
2131 dbg_event(_usb_addr(mEp), "FREE", 0);
2132
2133 spin_unlock_irqrestore(mEp->lock, flags);
2134 }
2135
2136 /**
2137 * ep_queue: queues (submits) an I/O request to an endpoint
2138 *
2139 * Check usb_ep_queue()* at usb_gadget.h" for details
2140 */
2141 static int ep_queue(struct usb_ep *ep, struct usb_request *req,
2142 gfp_t __maybe_unused gfp_flags)
2143 {
2144 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2145 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2146 int retval = 0;
2147 unsigned long flags;
2148
2149 trace("%p, %p, %X", ep, req, gfp_flags);
2150
2151 if (ep == NULL || req == NULL || mEp->desc == NULL)
2152 return -EINVAL;
2153
2154 spin_lock_irqsave(mEp->lock, flags);
2155
2156 if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
2157 !list_empty(&mEp->qh.queue)) {
2158 _ep_nuke(mEp);
2159 retval = -EOVERFLOW;
2160 warn("endpoint ctrl %X nuked", _usb_addr(mEp));
2161 }
2162
2163 /* first nuke then test link, e.g. previous status has not sent */
2164 if (!list_empty(&mReq->queue)) {
2165 retval = -EBUSY;
2166 err("request already in queue");
2167 goto done;
2168 }
2169
2170 if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
2171 req->length = (4 * CI13XXX_PAGE_SIZE);
2172 retval = -EMSGSIZE;
2173 warn("request length truncated");
2174 }
2175
2176 dbg_queue(_usb_addr(mEp), req, retval);
2177
2178 /* push request */
2179 mReq->req.status = -EINPROGRESS;
2180 mReq->req.actual = 0;
2181 list_add_tail(&mReq->queue, &mEp->qh.queue);
2182
2183 if (list_is_singular(&mEp->qh.queue))
2184 retval = _hardware_enqueue(mEp, mReq);
2185
2186 if (retval == -EALREADY) {
2187 dbg_event(_usb_addr(mEp), "QUEUE", retval);
2188 retval = 0;
2189 }
2190
2191 done:
2192 spin_unlock_irqrestore(mEp->lock, flags);
2193 return retval;
2194 }
2195
2196 /**
2197 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
2198 *
2199 * Check usb_ep_dequeue() at "usb_gadget.h" for details
2200 */
2201 static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2202 {
2203 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2204 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2205 unsigned long flags;
2206
2207 trace("%p, %p", ep, req);
2208
2209 if (ep == NULL || req == NULL || mEp->desc == NULL ||
2210 list_empty(&mReq->queue) || list_empty(&mEp->qh.queue))
2211 return -EINVAL;
2212
2213 spin_lock_irqsave(mEp->lock, flags);
2214
2215 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
2216
2217 if (mReq->req.status == -EALREADY)
2218 _hardware_dequeue(mEp, mReq);
2219
2220 /* pop request */
2221 list_del_init(&mReq->queue);
2222 req->status = -ECONNRESET;
2223
2224 if (mReq->req.complete != NULL) {
2225 spin_unlock(mEp->lock);
2226 mReq->req.complete(&mEp->ep, &mReq->req);
2227 spin_lock(mEp->lock);
2228 }
2229
2230 spin_unlock_irqrestore(mEp->lock, flags);
2231 return 0;
2232 }
2233
2234 /**
2235 * ep_set_halt: sets the endpoint halt feature
2236 *
2237 * Check usb_ep_set_halt() at "usb_gadget.h" for details
2238 */
2239 static int ep_set_halt(struct usb_ep *ep, int value)
2240 {
2241 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2242 int direction, retval = 0;
2243 unsigned long flags;
2244
2245 trace("%p, %i", ep, value);
2246
2247 if (ep == NULL || mEp->desc == NULL)
2248 return -EINVAL;
2249
2250 spin_lock_irqsave(mEp->lock, flags);
2251
2252 #ifndef STALL_IN
2253 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
2254 if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
2255 !list_empty(&mEp->qh.queue)) {
2256 spin_unlock_irqrestore(mEp->lock, flags);
2257 return -EAGAIN;
2258 }
2259 #endif
2260
2261 direction = mEp->dir;
2262 do {
2263 dbg_event(_usb_addr(mEp), "HALT", value);
2264 retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
2265
2266 if (!value)
2267 mEp->wedge = 0;
2268
2269 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2270 mEp->dir = (mEp->dir == TX) ? RX : TX;
2271
2272 } while (mEp->dir != direction);
2273
2274 spin_unlock_irqrestore(mEp->lock, flags);
2275 return retval;
2276 }
2277
2278 /**
2279 * ep_set_wedge: sets the halt feature and ignores clear requests
2280 *
2281 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
2282 */
2283 static int ep_set_wedge(struct usb_ep *ep)
2284 {
2285 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2286 unsigned long flags;
2287
2288 trace("%p", ep);
2289
2290 if (ep == NULL || mEp->desc == NULL)
2291 return -EINVAL;
2292
2293 spin_lock_irqsave(mEp->lock, flags);
2294
2295 dbg_event(_usb_addr(mEp), "WEDGE", 0);
2296 mEp->wedge = 1;
2297
2298 spin_unlock_irqrestore(mEp->lock, flags);
2299
2300 return usb_ep_set_halt(ep);
2301 }
2302
2303 /**
2304 * ep_fifo_flush: flushes contents of a fifo
2305 *
2306 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
2307 */
2308 static void ep_fifo_flush(struct usb_ep *ep)
2309 {
2310 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2311 unsigned long flags;
2312
2313 trace("%p", ep);
2314
2315 if (ep == NULL) {
2316 err("%02X: -EINVAL", _usb_addr(mEp));
2317 return;
2318 }
2319
2320 spin_lock_irqsave(mEp->lock, flags);
2321
2322 dbg_event(_usb_addr(mEp), "FFLUSH", 0);
2323 hw_ep_flush(mEp->num, mEp->dir);
2324
2325 spin_unlock_irqrestore(mEp->lock, flags);
2326 }
2327
2328 /**
2329 * Endpoint-specific part of the API to the USB controller hardware
2330 * Check "usb_gadget.h" for details
2331 */
2332 static const struct usb_ep_ops usb_ep_ops = {
2333 .enable = ep_enable,
2334 .disable = ep_disable,
2335 .alloc_request = ep_alloc_request,
2336 .free_request = ep_free_request,
2337 .queue = ep_queue,
2338 .dequeue = ep_dequeue,
2339 .set_halt = ep_set_halt,
2340 .set_wedge = ep_set_wedge,
2341 .fifo_flush = ep_fifo_flush,
2342 };
2343
2344 /******************************************************************************
2345 * GADGET block
2346 *****************************************************************************/
2347 static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
2348 {
2349 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2350 unsigned long flags;
2351 int gadget_ready = 0;
2352
2353 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
2354 return -EOPNOTSUPP;
2355
2356 spin_lock_irqsave(udc->lock, flags);
2357 udc->vbus_active = is_active;
2358 if (udc->driver)
2359 gadget_ready = 1;
2360 spin_unlock_irqrestore(udc->lock, flags);
2361
2362 if (gadget_ready) {
2363 if (is_active) {
2364 pm_runtime_get_sync(&_gadget->dev);
2365 hw_device_reset(udc);
2366 hw_device_state(udc->ep0out.qh.dma);
2367 } else {
2368 hw_device_state(0);
2369 if (udc->udc_driver->notify_event)
2370 udc->udc_driver->notify_event(udc,
2371 CI13XXX_CONTROLLER_STOPPED_EVENT);
2372 _gadget_stop_activity(&udc->gadget);
2373 pm_runtime_put_sync(&_gadget->dev);
2374 }
2375 }
2376
2377 return 0;
2378 }
2379
2380 /**
2381 * Device operations part of the API to the USB controller hardware,
2382 * which don't involve endpoints (or i/o)
2383 * Check "usb_gadget.h" for details
2384 */
2385 static const struct usb_gadget_ops usb_gadget_ops = {
2386 .vbus_session = ci13xxx_vbus_session,
2387 };
2388
2389 /**
2390 * usb_gadget_probe_driver: register a gadget driver
2391 * @driver: the driver being registered
2392 * @bind: the driver's bind callback
2393 *
2394 * Check usb_gadget_probe_driver() at <linux/usb/gadget.h> for details.
2395 * Interrupts are enabled here.
2396 */
2397 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
2398 int (*bind)(struct usb_gadget *))
2399 {
2400 struct ci13xxx *udc = _udc;
2401 unsigned long flags;
2402 int i, j;
2403 int retval = -ENOMEM;
2404
2405 trace("%p", driver);
2406
2407 if (driver == NULL ||
2408 bind == NULL ||
2409 driver->setup == NULL ||
2410 driver->disconnect == NULL ||
2411 driver->suspend == NULL ||
2412 driver->resume == NULL)
2413 return -EINVAL;
2414 else if (udc == NULL)
2415 return -ENODEV;
2416 else if (udc->driver != NULL)
2417 return -EBUSY;
2418
2419 /* alloc resources */
2420 udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
2421 sizeof(struct ci13xxx_qh),
2422 64, CI13XXX_PAGE_SIZE);
2423 if (udc->qh_pool == NULL)
2424 return -ENOMEM;
2425
2426 udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
2427 sizeof(struct ci13xxx_td),
2428 64, CI13XXX_PAGE_SIZE);
2429 if (udc->td_pool == NULL) {
2430 dma_pool_destroy(udc->qh_pool);
2431 udc->qh_pool = NULL;
2432 return -ENOMEM;
2433 }
2434
2435 spin_lock_irqsave(udc->lock, flags);
2436
2437 info("hw_ep_max = %d", hw_ep_max);
2438
2439 udc->gadget.dev.driver = NULL;
2440
2441 retval = 0;
2442 for (i = 0; i < hw_ep_max/2; i++) {
2443 for (j = RX; j <= TX; j++) {
2444 int k = i + j * hw_ep_max/2;
2445 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
2446
2447 scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
2448 (j == TX) ? "in" : "out");
2449
2450 mEp->lock = udc->lock;
2451 mEp->device = &udc->gadget.dev;
2452 mEp->td_pool = udc->td_pool;
2453
2454 mEp->ep.name = mEp->name;
2455 mEp->ep.ops = &usb_ep_ops;
2456 mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
2457
2458 INIT_LIST_HEAD(&mEp->qh.queue);
2459 spin_unlock_irqrestore(udc->lock, flags);
2460 mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
2461 &mEp->qh.dma);
2462 spin_lock_irqsave(udc->lock, flags);
2463 if (mEp->qh.ptr == NULL)
2464 retval = -ENOMEM;
2465 else
2466 memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
2467
2468 /* skip ep0 out and in endpoints */
2469 if (i == 0)
2470 continue;
2471
2472 list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
2473 }
2474 }
2475 if (retval)
2476 goto done;
2477
2478 udc->gadget.ep0 = &udc->ep0in.ep;
2479 /* bind gadget */
2480 driver->driver.bus = NULL;
2481 udc->gadget.dev.driver = &driver->driver;
2482
2483 spin_unlock_irqrestore(udc->lock, flags);
2484 retval = bind(&udc->gadget); /* MAY SLEEP */
2485 spin_lock_irqsave(udc->lock, flags);
2486
2487 if (retval) {
2488 udc->gadget.dev.driver = NULL;
2489 goto done;
2490 }
2491
2492 udc->driver = driver;
2493 pm_runtime_get_sync(&udc->gadget.dev);
2494 if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
2495 if (udc->vbus_active) {
2496 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
2497 hw_device_reset(udc);
2498 } else {
2499 pm_runtime_put_sync(&udc->gadget.dev);
2500 goto done;
2501 }
2502 }
2503
2504 retval = hw_device_state(udc->ep0out.qh.dma);
2505 if (retval)
2506 pm_runtime_put_sync(&udc->gadget.dev);
2507
2508 done:
2509 spin_unlock_irqrestore(udc->lock, flags);
2510 return retval;
2511 }
2512 EXPORT_SYMBOL(usb_gadget_probe_driver);
2513
2514 /**
2515 * usb_gadget_unregister_driver: unregister a gadget driver
2516 *
2517 * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
2518 */
2519 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2520 {
2521 struct ci13xxx *udc = _udc;
2522 unsigned long i, flags;
2523
2524 trace("%p", driver);
2525
2526 if (driver == NULL ||
2527 driver->unbind == NULL ||
2528 driver->setup == NULL ||
2529 driver->disconnect == NULL ||
2530 driver->suspend == NULL ||
2531 driver->resume == NULL ||
2532 driver != udc->driver)
2533 return -EINVAL;
2534
2535 spin_lock_irqsave(udc->lock, flags);
2536
2537 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
2538 udc->vbus_active) {
2539 hw_device_state(0);
2540 if (udc->udc_driver->notify_event)
2541 udc->udc_driver->notify_event(udc,
2542 CI13XXX_CONTROLLER_STOPPED_EVENT);
2543 _gadget_stop_activity(&udc->gadget);
2544 pm_runtime_put(&udc->gadget.dev);
2545 }
2546
2547 /* unbind gadget */
2548 spin_unlock_irqrestore(udc->lock, flags);
2549 driver->unbind(&udc->gadget); /* MAY SLEEP */
2550 spin_lock_irqsave(udc->lock, flags);
2551
2552 udc->gadget.dev.driver = NULL;
2553
2554 /* free resources */
2555 for (i = 0; i < hw_ep_max; i++) {
2556 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
2557
2558 if (!list_empty(&mEp->ep.ep_list))
2559 list_del_init(&mEp->ep.ep_list);
2560
2561 if (mEp->qh.ptr != NULL)
2562 dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
2563 }
2564
2565 udc->gadget.ep0 = NULL;
2566 udc->driver = NULL;
2567
2568 spin_unlock_irqrestore(udc->lock, flags);
2569
2570 if (udc->td_pool != NULL) {
2571 dma_pool_destroy(udc->td_pool);
2572 udc->td_pool = NULL;
2573 }
2574 if (udc->qh_pool != NULL) {
2575 dma_pool_destroy(udc->qh_pool);
2576 udc->qh_pool = NULL;
2577 }
2578
2579 return 0;
2580 }
2581 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2582
2583 /******************************************************************************
2584 * BUS block
2585 *****************************************************************************/
2586 /**
2587 * udc_irq: global interrupt handler
2588 *
2589 * This function returns IRQ_HANDLED if the IRQ has been handled
2590 * It locks access to registers
2591 */
2592 static irqreturn_t udc_irq(void)
2593 {
2594 struct ci13xxx *udc = _udc;
2595 irqreturn_t retval;
2596 u32 intr;
2597
2598 trace();
2599
2600 if (udc == NULL) {
2601 err("ENODEV");
2602 return IRQ_HANDLED;
2603 }
2604
2605 spin_lock(udc->lock);
2606
2607 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
2608 if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
2609 USBMODE_CM_DEVICE) {
2610 spin_unlock(udc->lock);
2611 return IRQ_NONE;
2612 }
2613 }
2614 intr = hw_test_and_clear_intr_active();
2615 if (intr) {
2616 isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
2617 isr_statistics.hndl.idx &= ISR_MASK;
2618 isr_statistics.hndl.cnt++;
2619
2620 /* order defines priority - do NOT change it */
2621 if (USBi_URI & intr) {
2622 isr_statistics.uri++;
2623 isr_reset_handler(udc);
2624 }
2625 if (USBi_PCI & intr) {
2626 isr_statistics.pci++;
2627 udc->gadget.speed = hw_port_is_high_speed() ?
2628 USB_SPEED_HIGH : USB_SPEED_FULL;
2629 }
2630 if (USBi_UEI & intr)
2631 isr_statistics.uei++;
2632 if (USBi_UI & intr) {
2633 isr_statistics.ui++;
2634 isr_tr_complete_handler(udc);
2635 }
2636 if (USBi_SLI & intr)
2637 isr_statistics.sli++;
2638 retval = IRQ_HANDLED;
2639 } else {
2640 isr_statistics.none++;
2641 retval = IRQ_NONE;
2642 }
2643 spin_unlock(udc->lock);
2644
2645 return retval;
2646 }
2647
2648 /**
2649 * udc_release: driver release function
2650 * @dev: device
2651 *
2652 * Currently does nothing
2653 */
2654 static void udc_release(struct device *dev)
2655 {
2656 trace("%p", dev);
2657
2658 if (dev == NULL)
2659 err("EINVAL");
2660 }
2661
2662 /**
2663 * udc_probe: parent probe must call this to initialize UDC
2664 * @dev: parent device
2665 * @regs: registers base address
2666 * @name: driver name
2667 *
2668 * This function returns an error code
2669 * No interrupts active, the IRQ has not been requested yet
2670 * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
2671 */
2672 static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
2673 void __iomem *regs)
2674 {
2675 struct ci13xxx *udc;
2676 int retval = 0;
2677
2678 trace("%p, %p, %p", dev, regs, name);
2679
2680 if (dev == NULL || regs == NULL || driver == NULL ||
2681 driver->name == NULL)
2682 return -EINVAL;
2683
2684 udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
2685 if (udc == NULL)
2686 return -ENOMEM;
2687
2688 udc->lock = &udc_lock;
2689 udc->regs = regs;
2690 udc->udc_driver = driver;
2691
2692 udc->gadget.ops = &usb_gadget_ops;
2693 udc->gadget.speed = USB_SPEED_UNKNOWN;
2694 udc->gadget.is_dualspeed = 1;
2695 udc->gadget.is_otg = 0;
2696 udc->gadget.name = driver->name;
2697
2698 INIT_LIST_HEAD(&udc->gadget.ep_list);
2699 udc->gadget.ep0 = NULL;
2700
2701 dev_set_name(&udc->gadget.dev, "gadget");
2702 udc->gadget.dev.dma_mask = dev->dma_mask;
2703 udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
2704 udc->gadget.dev.parent = dev;
2705 udc->gadget.dev.release = udc_release;
2706
2707 retval = hw_device_init(regs);
2708 if (retval < 0)
2709 goto free_udc;
2710
2711 udc->transceiver = otg_get_transceiver();
2712
2713 if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
2714 if (udc->transceiver == NULL) {
2715 retval = -ENODEV;
2716 goto free_udc;
2717 }
2718 }
2719
2720 if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
2721 retval = hw_device_reset(udc);
2722 if (retval)
2723 goto put_transceiver;
2724 }
2725
2726 retval = device_register(&udc->gadget.dev);
2727 if (retval) {
2728 put_device(&udc->gadget.dev);
2729 goto put_transceiver;
2730 }
2731
2732 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2733 retval = dbg_create_files(&udc->gadget.dev);
2734 #endif
2735 if (retval)
2736 goto unreg_device;
2737
2738 if (udc->transceiver) {
2739 retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
2740 if (retval)
2741 goto remove_dbg;
2742 }
2743 pm_runtime_no_callbacks(&udc->gadget.dev);
2744 pm_runtime_enable(&udc->gadget.dev);
2745
2746 _udc = udc;
2747 return retval;
2748
2749 err("error = %i", retval);
2750 remove_dbg:
2751 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2752 dbg_remove_files(&udc->gadget.dev);
2753 #endif
2754 unreg_device:
2755 device_unregister(&udc->gadget.dev);
2756 put_transceiver:
2757 if (udc->transceiver)
2758 otg_put_transceiver(udc->transceiver);
2759 free_udc:
2760 kfree(udc);
2761 _udc = NULL;
2762 return retval;
2763 }
2764
2765 /**
2766 * udc_remove: parent remove must call this to remove UDC
2767 *
2768 * No interrupts active, the IRQ has been released
2769 */
2770 static void udc_remove(void)
2771 {
2772 struct ci13xxx *udc = _udc;
2773
2774 if (udc == NULL) {
2775 err("EINVAL");
2776 return;
2777 }
2778
2779 if (udc->transceiver) {
2780 otg_set_peripheral(udc->transceiver, &udc->gadget);
2781 otg_put_transceiver(udc->transceiver);
2782 }
2783 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2784 dbg_remove_files(&udc->gadget.dev);
2785 #endif
2786 device_unregister(&udc->gadget.dev);
2787
2788 kfree(udc);
2789 _udc = NULL;
2790 }
The kernel tree for Tao Ma.