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ocfs2: Make the left masklogs compat.
[taoma-kernel.git] / drivers / video / sh_mobile_hdmi.c
blob2b9e56a6bde4780933d444b1f7e29aada38274eb
1 /*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28
29 #include <video/sh_mobile_hdmi.h>
30 #include <video/sh_mobile_lcdc.h>
31
32 #include "sh_mobile_lcdcfb.h"
33
34 #define HDMI_SYSTEM_CTRL 0x00 /* System control */
35 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
36 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
38 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
39 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
40 bits 19..16 of Internal CTS */
41 #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
42 #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
43 #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
44 #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
45 #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
46 #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
47 #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
48 #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
49 #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
50 #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
51 #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
52 #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
53 #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
54 #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
55 #define HDMI_CATEGORY_CODE 0x13 /* Category code */
56 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
57 #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
58 #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
59 #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
60
61 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
62 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
63
64 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
65 #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
66 #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
67 #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
68 #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
69 #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
70 #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
71 #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
72 #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
73 #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
74 #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
75 #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
76 #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
77 #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
78 #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
79 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
80 #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
81 #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
82 #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
83 #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
84 #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
85 #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
86 #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
87 #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
88 #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
97 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
98 #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
129 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
130 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
132 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
133 #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
134 #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
135 #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
136 #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
137 #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
138 #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
139 #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
140 #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
141 #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
142 #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
143 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
144 #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
145 #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
146 #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
147 #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
148 #define HDMI_SHA0 0xB9 /* sha0 */
149 #define HDMI_SHA1 0xBA /* sha1 */
150 #define HDMI_SHA2 0xBB /* sha2 */
151 #define HDMI_SHA3 0xBC /* sha3 */
152 #define HDMI_SHA4 0xBD /* sha4 */
153 #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
154 #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
155 #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
156 #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
157 #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
158 #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
159 #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
160 #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
161 #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
162 #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
163 #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
164 #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
165 #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
166 #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
167 #define HDMI_AN_SEED 0xCC /* An seed */
168 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
170 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
171 #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
172 #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
173 #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
174 #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
175 #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
176 #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
177 #define HDMI_PJ 0xD7 /* Pj */
178 #define HDMI_SHA_RD 0xD8 /* sha_rd */
179 #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
180 #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
181 #define HDMI_PJ_SAVED 0xDB /* Pj saved */
182 #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
183 #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
184 #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
185 #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
186 #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
187 #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
188 #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
189 #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
190 #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
191 #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
192 #define HDMI_AN_7_0 0xE8 /* An[7:0] */
193 #define HDMI_AN_15_8 0xE9 /* An [15:8] */
194 #define HDMI_AN_23_16 0xEA /* An [23:16] */
195 #define HDMI_AN_31_24 0xEB /* An [31:24] */
196 #define HDMI_AN_39_32 0xEC /* An [39:32] */
197 #define HDMI_AN_47_40 0xED /* An [47:40] */
198 #define HDMI_AN_55_48 0xEE /* An [55:48] */
199 #define HDMI_AN_63_56 0xEF /* An [63:56] */
200 #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
201 #define HDMI_REVISION_ID 0xF1 /* Revision ID */
202 #define HDMI_TEST_MODE 0xFE /* Test mode */
203
204 enum hotplug_state {
205 HDMI_HOTPLUG_DISCONNECTED,
206 HDMI_HOTPLUG_CONNECTED,
207 HDMI_HOTPLUG_EDID_DONE,
208 };
209
210 struct sh_hdmi {
211 void __iomem *base;
212 enum hotplug_state hp_state; /* hot-plug status */
213 u8 preprogrammed_vic; /* use a pre-programmed VIC or
214 the external mode */
215 u8 edid_block_addr;
216 u8 edid_segment_nr;
217 u8 edid_blocks;
218 struct clk *hdmi_clk;
219 struct device *dev;
220 struct fb_info *info;
221 struct mutex mutex; /* Protect the info pointer */
222 struct delayed_work edid_work;
223 struct fb_var_screeninfo var;
224 struct fb_monspecs monspec;
225 struct notifier_block notifier;
226 };
227
228 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
229 {
230 iowrite8(data, hdmi->base + reg);
231 }
232
233 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
234 {
235 return ioread8(hdmi->base + reg);
236 }
237
238 /*
239 * HDMI sound
240 */
241 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
242 unsigned int reg)
243 {
244 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
245
246 return hdmi_read(hdmi, reg);
247 }
248
249 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
250 unsigned int reg,
251 unsigned int value)
252 {
253 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
254
255 hdmi_write(hdmi, value, reg);
256 return 0;
257 }
258
259 static struct snd_soc_dai_driver sh_hdmi_dai = {
260 .name = "sh_mobile_hdmi-hifi",
261 .playback = {
262 .stream_name = "Playback",
263 .channels_min = 2,
264 .channels_max = 8,
265 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
266 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
267 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
268 SNDRV_PCM_RATE_192000,
269 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
270 },
271 };
272
273 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
274 {
275 dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
276
277 return 0;
278 }
279
280 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
281 .probe = sh_hdmi_snd_probe,
282 .read = sh_hdmi_snd_read,
283 .write = sh_hdmi_snd_write,
284 };
285
286 /*
287 * HDMI video
288 */
289
290 /* External video parameter settings */
291 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
292 {
293 struct fb_var_screeninfo *var = &hdmi->var;
294 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
295 u8 sync = 0;
296
297 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
298
299 hdelay = var->hsync_len + var->left_margin;
300 hblank = var->right_margin + hdelay;
301
302 /*
303 * Vertical timing looks a bit different in Figure 18,
304 * but let's try the same first by setting offset = 0
305 */
306 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
307
308 vdelay = var->vsync_len + var->upper_margin;
309 vblank = var->lower_margin + vdelay;
310 voffset = min(var->upper_margin / 2, 6U);
311
312 /*
313 * [3]: VSYNC polarity: Positive
314 * [2]: HSYNC polarity: Positive
315 * [1]: Interlace/Progressive: Progressive
316 * [0]: External video settings enable: used.
317 */
318 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
319 sync |= 4;
320 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
321 sync |= 8;
322
323 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
324 htotal, hblank, hdelay, var->hsync_len,
325 vtotal, vblank, vdelay, var->vsync_len, sync);
326
327 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
328
329 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
330 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
331
332 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
333 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
334
335 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
336 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
337
338 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
339 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
340
341 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
342 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
343
344 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
345
346 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
347
348 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
349
350 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
351 if (!hdmi->preprogrammed_vic)
352 hdmi_write(hdmi, sync | 1 | (voffset << 4),
353 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
354 }
355
356 /**
357 * sh_hdmi_video_config()
358 */
359 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
360 {
361 /*
362 * [7:4]: Audio sampling frequency: 48kHz
363 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
364 * [0]: Internal/External DE select: internal
365 */
366 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
367
368 /*
369 * [7:6]: Video output format: RGB 4:4:4
370 * [5:4]: Input video data width: 8 bit
371 * [3:1]: EAV/SAV location: channel 1
372 * [0]: Video input color space: RGB
373 */
374 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
375
376 /*
377 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
378 * left at 0 by default, this configures 24bpp and sets the Color Depth
379 * (CD) field in the General Control Packet
380 */
381 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
382 }
383
384 /**
385 * sh_hdmi_audio_config()
386 */
387 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
388 {
389 u8 data;
390 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
391
392 /*
393 * [7:4] L/R data swap control
394 * [3:0] appropriate N[19:16]
395 */
396 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
397 /* appropriate N[15:8] */
398 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
399 /* appropriate N[7:0] */
400 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
401
402 /* [7:4] 48 kHz SPDIF not used */
403 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
404
405 /*
406 * [6:5] set required down sampling rate if required
407 * [4:3] set required audio source
408 */
409 switch (pdata->flags & HDMI_SND_SRC_MASK) {
410 default:
411 /* fall through */
412 case HDMI_SND_SRC_I2S:
413 data = 0x0 << 3;
414 break;
415 case HDMI_SND_SRC_SPDIF:
416 data = 0x1 << 3;
417 break;
418 case HDMI_SND_SRC_DSD:
419 data = 0x2 << 3;
420 break;
421 case HDMI_SND_SRC_HBR:
422 data = 0x3 << 3;
423 break;
424 }
425 hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
426
427 /* [3:0] set sending channel number for channel status */
428 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
429
430 /*
431 * [5:2] set valid I2S source input pin
432 * [1:0] set input I2S source mode
433 */
434 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
435
436 /* [7:4] set valid DSD source input pin */
437 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
438
439 /* [7:0] set appropriate I2S input pin swap settings if required */
440 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
441
442 /*
443 * [7] set validity bit for channel status
444 * [3:0] set original sample frequency for channel status
445 */
446 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
447
448 /*
449 * [7] set value for channel status
450 * [6] set value for channel status
451 * [5] set copyright bit for channel status
452 * [4:2] set additional information for channel status
453 * [1:0] set clock accuracy for channel status
454 */
455 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
456
457 /* [7:0] set category code for channel status */
458 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
459
460 /*
461 * [7:4] set source number for channel status
462 * [3:0] set word length for channel status
463 */
464 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
465
466 /* [7:4] set sample frequency for channel status */
467 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
468 }
469
470 /**
471 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
472 */
473 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
474 {
475 if (hdmi->var.pixclock < 10000) {
476 /* for 1080p8bit 148MHz */
477 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
478 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
479 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
480 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
481 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
482 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
483 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
484 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
485 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
486 } else if (hdmi->var.pixclock < 30000) {
487 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
488 /*
489 * [1:0] Speed_A
490 * [3:2] Speed_B
491 * [4] PLLA_Bypass
492 * [6] DRV_TEST_EN
493 * [7] DRV_TEST_IN
494 */
495 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
496 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
497 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
498 /*
499 * [2:0] BGR_I_OFFSET
500 * [6:4] BGR_V_OFFSET
501 */
502 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
503 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
504 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
505 /*
506 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
507 * LPF capacitance, LPF resistance[1]
508 */
509 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
510 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
511 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
512 /*
513 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
514 * LPF capacitance, LPF resistance[1]
515 */
516 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
517 /* DRV_CONFIG, PE_CONFIG */
518 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
519 /*
520 * [2:0] AMON_SEL (4 == LPF voltage)
521 * [4] PLLA_CONFIG[16]
522 * [5] PLLB_CONFIG[16]
523 */
524 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
525 } else {
526 /* for 480p8bit 27MHz */
527 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
528 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
529 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
530 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
531 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
532 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
533 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
534 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
535 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
536 }
537 }
538
539 /**
540 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
541 */
542 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
543 {
544 u8 vic;
545
546 /* AVI InfoFrame */
547 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
548
549 /* Packet Type = 0x82 */
550 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
551
552 /* Version = 0x02 */
553 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
554
555 /* Length = 13 (0x0D) */
556 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
557
558 /* N. A. Checksum */
559 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
560
561 /*
562 * Y = RGB
563 * A0 = No Data
564 * B = Bar Data not valid
565 * S = No Data
566 */
567 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
568
569 /*
570 * [7:6] C = Colorimetry: no data
571 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
572 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
573 */
574 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
575
576 /*
577 * ITC = No Data
578 * EC = xvYCC601
579 * Q = Default (depends on video format)
580 * SC = No Known non_uniform Scaling
581 */
582 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
583
584 /*
585 * VIC should be ignored if external config is used, so, we could just use 0,
586 * but play safe and use a valid value in any case just in case
587 */
588 if (hdmi->preprogrammed_vic)
589 vic = hdmi->preprogrammed_vic;
590 else
591 vic = 4;
592 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
593
594 /* PR = No Repetition */
595 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
596
597 /* Line Number of End of Top Bar (lower 8 bits) */
598 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
599
600 /* Line Number of End of Top Bar (upper 8 bits) */
601 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
602
603 /* Line Number of Start of Bottom Bar (lower 8 bits) */
604 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
605
606 /* Line Number of Start of Bottom Bar (upper 8 bits) */
607 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
608
609 /* Pixel Number of End of Left Bar (lower 8 bits) */
610 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
611
612 /* Pixel Number of End of Left Bar (upper 8 bits) */
613 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
614
615 /* Pixel Number of Start of Right Bar (lower 8 bits) */
616 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
617
618 /* Pixel Number of Start of Right Bar (upper 8 bits) */
619 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
620 }
621
622 /**
623 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
624 */
625 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
626 {
627 /* Audio InfoFrame */
628 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
629
630 /* Packet Type = 0x84 */
631 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
632
633 /* Version Number = 0x01 */
634 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
635
636 /* 0 Length = 10 (0x0A) */
637 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
638
639 /* n. a. Checksum */
640 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
641
642 /* Audio Channel Count = Refer to Stream Header */
643 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
644
645 /* Refer to Stream Header */
646 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
647
648 /* Format depends on coding type (i.e. CT0...CT3) */
649 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
650
651 /* Speaker Channel Allocation = Front Right + Front Left */
652 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
653
654 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
655 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
656
657 /* Reserved (0) */
658 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
659 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
660 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
661 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
662 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
663 }
664
665 /**
666 * sh_hdmi_configure() - Initialise HDMI for output
667 */
668 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
669 {
670 /* Configure video format */
671 sh_hdmi_video_config(hdmi);
672
673 /* Configure audio format */
674 sh_hdmi_audio_config(hdmi);
675
676 /* Configure PHY */
677 sh_hdmi_phy_config(hdmi);
678
679 /* Auxiliary Video Information (AVI) InfoFrame */
680 sh_hdmi_avi_infoframe_setup(hdmi);
681
682 /* Audio InfoFrame */
683 sh_hdmi_audio_infoframe_setup(hdmi);
684
685 /*
686 * Control packet auto send with VSYNC control: auto send
687 * General control, Gamut metadata, ISRC, and ACP packets
688 */
689 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
690
691 /* FIXME */
692 msleep(10);
693
694 /* PS mode b->d, reset PLLA and PLLB */
695 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
696
697 udelay(10);
698
699 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
700 }
701
702 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
703 const struct fb_videomode *mode,
704 unsigned long *hdmi_rate, unsigned long *parent_rate)
705 {
706 unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
707 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
708
709 *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
710 if ((long)*hdmi_rate < 0)
711 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
712
713 rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
714 if (rate_error && pdata->clk_optimize_parent)
715 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
716 else if (clk_get_parent(hdmi->hdmi_clk))
717 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
718
719 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
720 mode->left_margin, mode->xres,
721 mode->right_margin, mode->hsync_len,
722 mode->upper_margin, mode->yres,
723 mode->lower_margin, mode->vsync_len);
724
725 dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
726 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
727 mode->refresh, *parent_rate);
728
729 return rate_error;
730 }
731
732 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
733 unsigned long *parent_rate)
734 {
735 struct fb_var_screeninfo tmpvar;
736 struct fb_var_screeninfo *var = &tmpvar;
737 const struct fb_videomode *mode, *found = NULL;
738 struct fb_info *info = hdmi->info;
739 struct fb_modelist *modelist = NULL;
740 unsigned int f_width = 0, f_height = 0, f_refresh = 0;
741 unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
742 bool scanning = false, preferred_bad = false;
743 u8 edid[128];
744 char *forced;
745 int i;
746
747 /* Read EDID */
748 dev_dbg(hdmi->dev, "Read back EDID code:");
749 for (i = 0; i < 128; i++) {
750 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
751 #ifdef DEBUG
752 if ((i % 16) == 0) {
753 printk(KERN_CONT "\n");
754 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
755 } else {
756 printk(KERN_CONT " %02X", edid[i]);
757 }
758 #endif
759 }
760 #ifdef DEBUG
761 printk(KERN_CONT "\n");
762 #endif
763
764 if (!hdmi->edid_blocks) {
765 fb_edid_to_monspecs(edid, &hdmi->monspec);
766 hdmi->edid_blocks = edid[126] + 1;
767
768 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
769 hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
770 } else {
771 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
772 edid[0], edid[2]);
773 fb_edid_add_monspecs(edid, &hdmi->monspec);
774 }
775
776 if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
777 (hdmi->edid_block_addr >> 7) + 1) {
778 /* More blocks to read */
779 if (hdmi->edid_block_addr) {
780 hdmi->edid_block_addr = 0;
781 hdmi->edid_segment_nr++;
782 } else {
783 hdmi->edid_block_addr = 0x80;
784 }
785 /* Set EDID word address */
786 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
787 /* Enable EDID interrupt */
788 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
789 /* Set EDID segment pointer - starts reading EDID */
790 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
791 return -EAGAIN;
792 }
793
794 /* All E-EDID blocks ready */
795 dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
796
797 fb_get_options("sh_mobile_lcdc", &forced);
798 if (forced && *forced) {
799 /* Only primitive parsing so far */
800 i = sscanf(forced, "%ux%u@%u",
801 &f_width, &f_height, &f_refresh);
802 if (i < 2) {
803 f_width = 0;
804 f_height = 0;
805 } else {
806 /* The user wants us to use the EDID data */
807 scanning = true;
808 }
809 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
810 f_width, f_height, f_refresh);
811 }
812
813 /* Walk monitor modes to find the best or the exact match */
814 for (i = 0, mode = hdmi->monspec.modedb;
815 i < hdmi->monspec.modedb_len && scanning;
816 i++, mode++) {
817 unsigned long rate_error;
818
819 if (!f_width && !f_height) {
820 /*
821 * A parameter string "video=sh_mobile_lcdc:0x0" means
822 * use the preferred EDID mode. If it is rejected by
823 * .fb_check_var(), keep looking, until an acceptable
824 * one is found.
825 */
826 if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
827 scanning = false;
828 else
829 continue;
830 } else if (f_width != mode->xres || f_height != mode->yres) {
831 /* No interest in unmatching modes */
832 continue;
833 }
834
835 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
836
837 if (scanning) {
838 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
839 /*
840 * Exact match if either the refresh rate
841 * matches or it hasn't been specified and we've
842 * found a mode, for which we can configure the
843 * clock precisely
844 */
845 scanning = false;
846 else if (found && found_rate_error <= rate_error)
847 /*
848 * We otherwise search for the closest matching
849 * clock rate - either if no refresh rate has
850 * been specified or we cannot find an exactly
851 * matching one
852 */
853 continue;
854 }
855
856 /* Check if supported: sufficient fb memory, supported clock-rate */
857 fb_videomode_to_var(var, mode);
858
859 var->bits_per_pixel = info->var.bits_per_pixel;
860
861 if (info && info->fbops->fb_check_var &&
862 info->fbops->fb_check_var(var, info)) {
863 scanning = true;
864 preferred_bad = true;
865 continue;
866 }
867
868 found = mode;
869 found_rate_error = rate_error;
870 }
871
872 hdmi->var.width = hdmi->monspec.max_x * 10;
873 hdmi->var.height = hdmi->monspec.max_y * 10;
874
875 /*
876 * TODO 1: if no ->info is present, postpone running the config until
877 * after ->info first gets registered.
878 * TODO 2: consider registering the HDMI platform device from the LCDC
879 * driver, and passing ->info with HDMI platform data.
880 */
881 if (info && !found) {
882 modelist = info->modelist.next &&
883 !list_empty(&info->modelist) ?
884 list_entry(info->modelist.next,
885 struct fb_modelist, list) :
886 NULL;
887
888 if (modelist) {
889 found = &modelist->mode;
890 found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
891 }
892 }
893
894 /* No cookie today */
895 if (!found)
896 return -ENXIO;
897
898 if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
899 hdmi->preprogrammed_vic = 1;
900 else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
901 hdmi->preprogrammed_vic = 2;
902 else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
903 hdmi->preprogrammed_vic = 17;
904 else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
905 hdmi->preprogrammed_vic = 4;
906 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
907 hdmi->preprogrammed_vic = 32;
908 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
909 hdmi->preprogrammed_vic = 31;
910 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
911 hdmi->preprogrammed_vic = 16;
912 else
913 hdmi->preprogrammed_vic = 0;
914
915 dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
916 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
917 found->xres, found->yres, found->refresh,
918 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
919
920 fb_videomode_to_var(&hdmi->var, found);
921 sh_hdmi_external_video_param(hdmi);
922
923 return 0;
924 }
925
926 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
927 {
928 struct sh_hdmi *hdmi = dev_id;
929 u8 status1, status2, mask1, mask2;
930
931 /* mode_b and PLLA and PLLB reset */
932 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
933
934 /* How long shall reset be held? */
935 udelay(10);
936
937 /* mode_b and PLLA and PLLB reset release */
938 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
939
940 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
941 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
942
943 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
944 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
945
946 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
947 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
948 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
949
950 if (printk_ratelimit())
951 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
952 irq, status1, mask1, status2, mask2);
953
954 if (!((status1 & mask1) | (status2 & mask2))) {
955 return IRQ_NONE;
956 } else if (status1 & 0xc0) {
957 u8 msens;
958
959 /* Datasheet specifies 10ms... */
960 udelay(500);
961
962 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
963 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
964 /* Check, if hot plug & MSENS pin status are both high */
965 if ((msens & 0xC0) == 0xC0) {
966 /* Display plug in */
967 hdmi->edid_segment_nr = 0;
968 hdmi->edid_block_addr = 0;
969 hdmi->edid_blocks = 0;
970 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
971
972 /* Set EDID word address */
973 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
974 /* Enable EDID interrupt */
975 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
976 /* Set EDID segment pointer - starts reading EDID */
977 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
978 } else if (!(status1 & 0x80)) {
979 /* Display unplug, beware multiple interrupts */
980 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
981 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
982 schedule_delayed_work(&hdmi->edid_work, 0);
983 }
984 /* display_off will switch back to mode_a */
985 }
986 } else if (status1 & 2) {
987 /* EDID error interrupt: retry */
988 /* Set EDID word address */
989 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
990 /* Set EDID segment pointer */
991 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
992 } else if (status1 & 4) {
993 /* Disable EDID interrupt */
994 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
995 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
996 }
997
998 return IRQ_HANDLED;
999 }
1000
1001 /* locking: called with info->lock held, or before register_framebuffer() */
1002 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
1003 {
1004 /*
1005 * info is guaranteed to be valid, when we are called, because our
1006 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
1007 */
1008 struct sh_hdmi *hdmi = arg;
1009 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1010 struct sh_mobile_lcdc_chan *ch = info->par;
1011
1012 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
1013 pdata->lcd_dev, info->state);
1014
1015 /* No need to lock */
1016 hdmi->info = info;
1017
1018 /*
1019 * hp_state can be set to
1020 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
1021 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
1022 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
1023 */
1024 switch (hdmi->hp_state) {
1025 case HDMI_HOTPLUG_EDID_DONE:
1026 /* PS mode d->e. All functions are active */
1027 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
1028 dev_dbg(hdmi->dev, "HDMI running\n");
1029 break;
1030 case HDMI_HOTPLUG_DISCONNECTED:
1031 info->state = FBINFO_STATE_SUSPENDED;
1032 default:
1033 hdmi->var = ch->display_var;
1034 }
1035 }
1036
1037 /* locking: called with info->lock held */
1038 static void sh_hdmi_display_off(void *arg)
1039 {
1040 struct sh_hdmi *hdmi = arg;
1041 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1042
1043 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
1044 /* PS mode e->a */
1045 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1046 }
1047
1048 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1049 {
1050 struct fb_info *info = hdmi->info;
1051 struct sh_mobile_lcdc_chan *ch = info->par;
1052 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1053 struct fb_videomode mode1, mode2;
1054
1055 fb_var_to_videomode(&mode1, old_var);
1056 fb_var_to_videomode(&mode2, new_var);
1057
1058 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
1059 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1060
1061 if (fb_mode_is_equal(&mode1, &mode2)) {
1062 /* It can be a different monitor with an equal video-mode */
1063 old_var->width = new_var->width;
1064 old_var->height = new_var->height;
1065 return false;
1066 }
1067
1068 dev_dbg(info->dev, "Switching %u -> %u lines\n",
1069 mode1.yres, mode2.yres);
1070 *old_var = *new_var;
1071
1072 return true;
1073 }
1074
1075 /**
1076 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1077 * @hdmi: driver context
1078 * @hdmi_rate: HDMI clock frequency in Hz
1079 * @parent_rate: if != 0 - set parent clock rate for optimal precision
1080 * return: configured positive rate if successful
1081 * 0 if couldn't set the rate, but managed to enable the
1082 * clock, negative error, if couldn't enable the clock
1083 */
1084 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1085 unsigned long parent_rate)
1086 {
1087 int ret;
1088
1089 if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1090 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1091 if (ret < 0) {
1092 dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1093 hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1094 } else {
1095 dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1096 }
1097 }
1098
1099 ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1100 if (ret < 0) {
1101 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1102 hdmi_rate = 0;
1103 } else {
1104 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1105 }
1106
1107 return hdmi_rate;
1108 }
1109
1110 /* Hotplug interrupt occurred, read EDID */
1111 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1112 {
1113 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1114 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1115 struct sh_mobile_lcdc_chan *ch;
1116 int ret;
1117
1118 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1119 pdata->lcd_dev, hdmi->hp_state);
1120
1121 if (!pdata->lcd_dev)
1122 return;
1123
1124 mutex_lock(&hdmi->mutex);
1125
1126 if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
1127 struct fb_info *info = hdmi->info;
1128 unsigned long parent_rate = 0, hdmi_rate;
1129
1130 /* A device has been plugged in */
1131 pm_runtime_get_sync(hdmi->dev);
1132
1133 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1134 if (ret < 0)
1135 goto out;
1136
1137 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1138
1139 /* Reconfigure the clock */
1140 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1141 if (ret < 0)
1142 goto out;
1143
1144 msleep(10);
1145 sh_hdmi_configure(hdmi);
1146 /* Switched to another (d) power-save mode */
1147 msleep(10);
1148
1149 if (!info)
1150 goto out;
1151
1152 ch = info->par;
1153
1154 console_lock();
1155
1156 /* HDMI plug in */
1157 if (!sh_hdmi_must_reconfigure(hdmi) &&
1158 info->state == FBINFO_STATE_RUNNING) {
1159 /*
1160 * First activation with the default monitor - just turn
1161 * on, if we run a resume here, the logo disappears
1162 */
1163 if (lock_fb_info(info)) {
1164 info->var.width = hdmi->var.width;
1165 info->var.height = hdmi->var.height;
1166 sh_hdmi_display_on(hdmi, info);
1167 unlock_fb_info(info);
1168 }
1169 } else {
1170 /* New monitor or have to wake up */
1171 fb_set_suspend(info, 0);
1172 }
1173
1174 console_unlock();
1175 } else {
1176 ret = 0;
1177 if (!hdmi->info)
1178 goto out;
1179
1180 hdmi->monspec.modedb_len = 0;
1181 fb_destroy_modedb(hdmi->monspec.modedb);
1182 hdmi->monspec.modedb = NULL;
1183
1184 console_lock();
1185
1186 /* HDMI disconnect */
1187 fb_set_suspend(hdmi->info, 1);
1188
1189 console_unlock();
1190 pm_runtime_put(hdmi->dev);
1191 }
1192
1193 out:
1194 if (ret < 0 && ret != -EAGAIN)
1195 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1196 mutex_unlock(&hdmi->mutex);
1197
1198 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1199 }
1200
1201 static int sh_hdmi_notify(struct notifier_block *nb,
1202 unsigned long action, void *data)
1203 {
1204 struct fb_event *event = data;
1205 struct fb_info *info = event->info;
1206 struct sh_mobile_lcdc_chan *ch = info->par;
1207 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1208 struct sh_hdmi *hdmi = board_cfg->board_data;
1209
1210 if (!hdmi || nb != &hdmi->notifier || hdmi->info != info)
1211 return NOTIFY_DONE;
1212
1213 switch(action) {
1214 case FB_EVENT_FB_REGISTERED:
1215 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1216 break;
1217 case FB_EVENT_FB_UNREGISTERED:
1218 /*
1219 * We are called from unregister_framebuffer() with the
1220 * info->lock held. This is bad for us, because we can race with
1221 * the scheduled work, which has to call fb_set_suspend(), which
1222 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1223 * cannot take and hold info->lock for the whole function
1224 * duration. Using an additional lock creates a classical AB-BA
1225 * lock up. Therefore, we have to release the info->lock
1226 * temporarily, synchronise with the work queue and re-acquire
1227 * the info->lock.
1228 */
1229 unlock_fb_info(info);
1230 mutex_lock(&hdmi->mutex);
1231 hdmi->info = NULL;
1232 mutex_unlock(&hdmi->mutex);
1233 lock_fb_info(info);
1234 return NOTIFY_OK;
1235 }
1236 return NOTIFY_DONE;
1237 }
1238
1239 static int __init sh_hdmi_probe(struct platform_device *pdev)
1240 {
1241 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1242 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1243 struct sh_mobile_lcdc_board_cfg *board_cfg;
1244 int irq = platform_get_irq(pdev, 0), ret;
1245 struct sh_hdmi *hdmi;
1246 long rate;
1247
1248 if (!res || !pdata || irq < 0)
1249 return -ENODEV;
1250
1251 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1252 if (!hdmi) {
1253 dev_err(&pdev->dev, "Cannot allocate device data\n");
1254 return -ENOMEM;
1255 }
1256
1257 mutex_init(&hdmi->mutex);
1258
1259 hdmi->dev = &pdev->dev;
1260
1261 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1262 if (IS_ERR(hdmi->hdmi_clk)) {
1263 ret = PTR_ERR(hdmi->hdmi_clk);
1264 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1265 goto egetclk;
1266 }
1267
1268 /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1269 rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1270 if (rate > 0)
1271 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1272
1273 if (rate < 0) {
1274 ret = rate;
1275 goto erate;
1276 }
1277
1278 ret = clk_enable(hdmi->hdmi_clk);
1279 if (ret < 0) {
1280 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1281 goto erate;
1282 }
1283
1284 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1285
1286 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1287 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1288 ret = -EBUSY;
1289 goto ereqreg;
1290 }
1291
1292 hdmi->base = ioremap(res->start, resource_size(res));
1293 if (!hdmi->base) {
1294 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1295 ret = -ENOMEM;
1296 goto emap;
1297 }
1298
1299 platform_set_drvdata(pdev, hdmi);
1300
1301 /* Set up LCDC callbacks */
1302 board_cfg = &pdata->lcd_chan->board_cfg;
1303 board_cfg->owner = THIS_MODULE;
1304 board_cfg->board_data = hdmi;
1305 board_cfg->display_on = sh_hdmi_display_on;
1306 board_cfg->display_off = sh_hdmi_display_off;
1307
1308 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1309
1310 pm_runtime_enable(&pdev->dev);
1311 pm_runtime_resume(&pdev->dev);
1312
1313 /* Product and revision IDs are 0 in sh-mobile version */
1314 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1315 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1316
1317 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1318 dev_name(&pdev->dev), hdmi);
1319 if (ret < 0) {
1320 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1321 goto ereqirq;
1322 }
1323
1324 ret = snd_soc_register_codec(&pdev->dev,
1325 &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1326 if (ret < 0) {
1327 dev_err(&pdev->dev, "codec registration failed\n");
1328 goto ecodec;
1329 }
1330
1331 hdmi->notifier.notifier_call = sh_hdmi_notify;
1332 fb_register_client(&hdmi->notifier);
1333
1334 return 0;
1335
1336 ecodec:
1337 free_irq(irq, hdmi);
1338 ereqirq:
1339 pm_runtime_disable(&pdev->dev);
1340 iounmap(hdmi->base);
1341 emap:
1342 release_mem_region(res->start, resource_size(res));
1343 ereqreg:
1344 clk_disable(hdmi->hdmi_clk);
1345 erate:
1346 clk_put(hdmi->hdmi_clk);
1347 egetclk:
1348 mutex_destroy(&hdmi->mutex);
1349 kfree(hdmi);
1350
1351 return ret;
1352 }
1353
1354 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1355 {
1356 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1357 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1358 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1359 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1360 int irq = platform_get_irq(pdev, 0);
1361
1362 snd_soc_unregister_codec(&pdev->dev);
1363
1364 fb_unregister_client(&hdmi->notifier);
1365
1366 board_cfg->display_on = NULL;
1367 board_cfg->display_off = NULL;
1368 board_cfg->board_data = NULL;
1369 board_cfg->owner = NULL;
1370
1371 /* No new work will be scheduled, wait for running ISR */
1372 free_irq(irq, hdmi);
1373 /* Wait for already scheduled work */
1374 cancel_delayed_work_sync(&hdmi->edid_work);
1375 pm_runtime_disable(&pdev->dev);
1376 clk_disable(hdmi->hdmi_clk);
1377 clk_put(hdmi->hdmi_clk);
1378 iounmap(hdmi->base);
1379 release_mem_region(res->start, resource_size(res));
1380 mutex_destroy(&hdmi->mutex);
1381 kfree(hdmi);
1382
1383 return 0;
1384 }
1385
1386 static struct platform_driver sh_hdmi_driver = {
1387 .remove = __exit_p(sh_hdmi_remove),
1388 .driver = {
1389 .name = "sh-mobile-hdmi",
1390 },
1391 };
1392
1393 static int __init sh_hdmi_init(void)
1394 {
1395 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1396 }
1397 module_init(sh_hdmi_init);
1398
1399 static void __exit sh_hdmi_exit(void)
1400 {
1401 platform_driver_unregister(&sh_hdmi_driver);
1402 }
1403 module_exit(sh_hdmi_exit);
1404
1405 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1406 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1407 MODULE_LICENSE("GPL v2");
The kernel tree for Tao Ma.