1 /*************************************************************/
3 * RISCV64 assembler for TCC
7 #ifdef TARGET_DEFS_ONLY
10 /* 32 general purpose + 32 floating point registers */
11 #define NB_ASM_REGS 64
13 ST_FUNC
void g(int c
);
14 ST_FUNC
void gen_le16(int c
);
15 ST_FUNC
void gen_le32(int c
);
17 /*************************************************************/
19 /*************************************************************/
28 // Registers go from 0 to 31. We use next bit to choose general/float
29 #define REG_FLOAT_MASK 0x20
30 #define REG_IS_FLOAT(register_index) ((register_index) & REG_FLOAT_MASK)
31 #define REG_VALUE(register_index) ((register_index) & (REG_FLOAT_MASK-1))
32 #define C_ENCODE_RS1(register_index) (REG_VALUE(register_index) << 7)
33 #define C_ENCODE_RS2(register_index) (REG_VALUE(register_index) << 2)
34 #define ENCODE_RD(register_index) (REG_VALUE(register_index) << 7)
35 #define ENCODE_RS1(register_index) (REG_VALUE(register_index) << 15)
36 #define ENCODE_RS2(register_index) (REG_VALUE(register_index) << 20)
37 #define NTH_BIT(b, n) ((b >> n) & 1)
38 #define OP_IM12S (1 << OPT_IM12S)
39 #define OP_IM32 (1 << OPT_IM32)
40 #define OP_REG (1 << OPT_REG)
42 typedef struct Operand
{
51 static const Operand zero
= { OP_REG
, { 0 }};
52 static const Operand ra
= { OP_REG
, { 1 }};
53 static const Operand zimm
= { OP_IM12S
};
55 static void asm_binary_opcode(TCCState
* s1
, int token
);
56 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
);
57 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
, int nb_operands
, int nb_outputs
, const uint8_t *clobber_regs
, int *pout_reg
);
58 static void asm_emit_a(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*rd1
, int aq
, int rl
);
59 static void asm_emit_b(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*imm
);
60 static void asm_emit_i(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*rs2
);
61 static void asm_emit_j(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs2
);
62 static void asm_emit_opcode(uint32_t opcode
);
63 static void asm_emit_r(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*rs2
);
64 static void asm_emit_s(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*imm
);
65 static void asm_emit_u(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs2
);
66 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
, int nb_outputs
, int is_output
, uint8_t *clobber_regs
, int out_reg
);
67 static void asm_nullary_opcode(TCCState
*s1
, int token
);
68 ST_FUNC
void asm_opcode(TCCState
*s1
, int token
);
69 static int asm_parse_csrvar(int t
);
70 ST_FUNC
int asm_parse_regvar(int t
);
71 static void asm_ternary_opcode(TCCState
*s1
, int token
);
72 static void asm_unary_opcode(TCCState
*s1
, int token
);
73 static void asm_branch_opcode(TCCState
*s1
, int token
, int argc
);
74 ST_FUNC
void gen_expr32(ExprValue
*pe
);
75 static void parse_operand(TCCState
*s1
, Operand
*op
);
76 static void parse_branch_offset_operand(TCCState
*s1
, Operand
*op
);
77 static void parse_operands(TCCState
*s1
, Operand
*ops
, int count
);
78 static void parse_mem_access_operands(TCCState
*s1
, Operand
* ops
);
79 ST_FUNC
void subst_asm_operand(CString
*add_str
, SValue
*sv
, int modifier
);
81 static void asm_emit_ca(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
);
82 static void asm_emit_cb(int token
, uint16_t opcode
, const Operand
*rs1
, const Operand
*imm
);
83 static void asm_emit_ci(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
);
84 static void asm_emit_ciw(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
);
85 static void asm_emit_cj(int token
, uint16_t opcode
, const Operand
*imm
);
86 static void asm_emit_cl(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*imm
);
87 static void asm_emit_cr(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
);
88 static void asm_emit_cs(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*rs1
, const Operand
*imm
);
89 static void asm_emit_css(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*imm
);
91 /* XXX: make it faster ? */
98 if (ind1
> cur_text_section
->data_allocated
)
99 section_realloc(cur_text_section
, ind1
);
100 cur_text_section
->data
[ind
] = c
;
104 ST_FUNC
void gen_le16 (int i
)
110 ST_FUNC
void gen_le32 (int i
)
116 if (ind1
> cur_text_section
->data_allocated
)
117 section_realloc(cur_text_section
, ind1
);
118 cur_text_section
->data
[ind
++] = i
& 0xFF;
119 cur_text_section
->data
[ind
++] = (i
>> 8) & 0xFF;
120 cur_text_section
->data
[ind
++] = (i
>> 16) & 0xFF;
121 cur_text_section
->data
[ind
++] = (i
>> 24) & 0xFF;
124 ST_FUNC
void gen_expr32(ExprValue
*pe
)
129 static void asm_emit_opcode(uint32_t opcode
) {
133 static void asm_nullary_opcode(TCCState
*s1
, int token
)
138 case TOK_ASM_fence_i
: // I
139 asm_emit_opcode((0x3 << 2) | 3| (1 << 12));
144 case TOK_ASM_ecall
: // I (pseudo)
145 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12));
147 case TOK_ASM_ebreak
: // I (pseudo)
148 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12) | (1 << 20));
154 asm_emit_i(token
, (4 << 2) | 3, &zero
, &zero
, &zimm
);
158 asm_emit_opcode((0x1C << 2) | 3 | (0x105 << 20));
161 /* Pseudoinstructions */
163 /* jalr zero, x1, 0 */
164 asm_emit_opcode( 0x67 | (0 << 12) | ENCODE_RS1(1) );
168 case TOK_ASM_c_ebreak
:
169 asm_emit_cr(token
, 2 | (9 << 12), &zero
, &zero
);
172 asm_emit_ci(token
, 1, &zero
, &zimm
);
176 expect("nullary instruction");
180 /* Parse a text containing operand and store the result in OP */
181 static void parse_operand(TCCState
*s1
, Operand
*op
)
189 if ((reg
= asm_parse_regvar(tok
)) != -1) {
190 next(); // skip register name
192 op
->reg
= (uint8_t) reg
;
194 } else if (tok
== '$') {
196 next(); // skip '#' or '$'
197 } else if ((e
.v
= asm_parse_csrvar(tok
)) != -1) {
204 /* compare against unsigned 12-bit maximum */
206 if ((int) op
->e
.v
>= -0x1000 && (int) op
->e
.v
< 0x1000)
208 } else if (op
->e
.sym
->type
.t
& (VT_EXTERN
| VT_STATIC
)) {
209 label
.type
.t
= VT_VOID
| VT_STATIC
;
211 /* use the medium PIC model: GOT, auipc, lw */
212 if (op
->e
.sym
->type
.t
& VT_STATIC
)
213 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_PCREL_HI20
, 0);
215 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_GOT_HI20
, 0);
216 put_extern_sym(&label
, cur_text_section
, ind
, 0);
217 greloca(cur_text_section
, &label
, ind
+4, R_RISCV_PCREL_LO12_I
, 0);
226 static void parse_branch_offset_operand(TCCState
*s1
, Operand
*op
){
232 /* compare against unsigned 12-bit maximum */
234 if ((int) op
->e
.v
>= -0x1000 && (int) op
->e
.v
< 0x1000)
236 } else if (op
->e
.sym
->type
.t
& (VT_EXTERN
| VT_STATIC
)) {
237 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_BRANCH
, 0);
239 /* XXX: Implement far branches */
248 static void parse_jump_offset_operand(TCCState
*s1
, Operand
*op
){
254 /* compare against unsigned 12-bit maximum */
256 if ((int) op
->e
.v
>= -0x1000 && (int) op
->e
.v
< 0x1000)
258 } else if (op
->e
.sym
->type
.t
& (VT_EXTERN
| VT_STATIC
)) {
259 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_JAL
, 0);
267 static void parse_operands(TCCState
*s1
, Operand
* ops
, int count
){
269 for (i
= 0; i
< count
; i
++) {
272 parse_operand(s1
, &ops
[i
]);
276 /* parse `X, imm(Y)` to {X, Y, imm} operands */
277 static void parse_mem_access_operands(TCCState
*s1
, Operand
* ops
){
281 parse_operand(s1
, &ops
[0]);
286 parse_operand(s1
, &ops
[1]);
290 parse_operand(s1
, &ops
[2]);
292 /* `X, imm(Y)` case*/
294 parse_operand(s1
, &ops
[1]);
298 /* we parsed Y thinking it was imm, swap and default imm to zero */
307 /* This is special: First operand is optional */
308 static void asm_jal_opcode(TCCState
*s1
, int token
){
311 if (token
== TOK_ASM_j
){
312 ops
[0] = zero
; // j offset
313 } else if (asm_parse_regvar(tok
) == -1) {
314 ops
[0] = ra
; // jal offset
317 parse_operand(s1
, &ops
[0]);
318 if ( tok
== ',') next(); else expect("','");
320 parse_jump_offset_operand(s1
, &ops
[1]);
321 asm_emit_j(token
, 0x6f, &ops
[0], &ops
[1]);
324 /* This is special: It can be a pseudointruction or a instruction */
325 static void asm_jalr_opcode(TCCState
*s1
, int token
){
329 parse_operand(s1
, &ops
[0]);
333 /* no more operands, it's the pseudoinstruction:
338 asm_emit_i(token
, 0x67 | (0 << 12), &ra
, &ops
[0], &zimm
);
345 parse_operand(s1
, &ops
[1]);
349 parse_operand(s1
, &ops
[2]);
351 /* `X, imm(Y)` case*/
353 parse_operand(s1
, &ops
[1]);
357 /* we parsed Y thinking it was imm, swap and default imm to zero */
364 /* jalr(RD, RS1, IMM); I-format */
365 asm_emit_i(token
, 0x67 | (0 << 12), &ops
[0], &ops
[1], &ops
[2]);
369 static void asm_unary_opcode(TCCState
*s1
, int token
)
371 uint32_t opcode
= (0x1C << 2) | 3 | (2 << 12);
374 parse_operands(s1
, &op
, 1);
375 /* Note: Those all map to CSR--so they are pseudo-instructions. */
376 opcode
|= ENCODE_RD(op
.reg
);
379 /* pseudoinstructions */
380 case TOK_ASM_rdcycle
:
381 asm_emit_opcode(opcode
| (0xC00 << 20));
383 case TOK_ASM_rdcycleh
:
384 asm_emit_opcode(opcode
| (0xC80 << 20));
387 asm_emit_opcode(opcode
| (0xC01 << 20) | ENCODE_RD(op
.reg
));
389 case TOK_ASM_rdtimeh
:
390 asm_emit_opcode(opcode
| (0xC81 << 20) | ENCODE_RD(op
.reg
));
392 case TOK_ASM_rdinstret
:
393 asm_emit_opcode(opcode
| (0xC02 << 20) | ENCODE_RD(op
.reg
));
395 case TOK_ASM_rdinstreth
:
396 asm_emit_opcode(opcode
| (0xC82 << 20) | ENCODE_RD(op
.reg
));
400 /* jalr zero, 0(rs)*/
401 asm_emit_i(token
, 0x67 | (0 << 12), &zero
, &op
, &zimm
);
405 greloca(cur_text_section
, op
.e
.sym
, ind
, R_RISCV_CALL
, 0);
406 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(1));
407 /* jalr zero, 0(ra) */
408 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(1));
412 greloca(cur_text_section
, op
.e
.sym
, ind
, R_RISCV_CALL
, 0);
413 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(6));
414 /* jalr zero, 0(x6) */
415 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(6));
420 asm_emit_cj(token
, 1 | (5 << 13), &op
);
422 case TOK_ASM_c_jal
: /* RV32C-only */
423 asm_emit_cj(token
, 1 | (1 << 13), &op
);
426 asm_emit_cr(token
, 2 | (9 << 12), &op
, &zero
);
429 asm_emit_cr(token
, 2 | (8 << 12), &op
, &zero
);
432 expect("unary instruction");
436 static void asm_emit_u(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs2
)
438 if (rd
->type
!= OP_REG
) {
439 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
441 if (rs2
->type
!= OP_IM12S
&& rs2
->type
!= OP_IM32
) {
442 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token
, NULL
));
443 } else if (rs2
->e
.v
>= 0x100000) {
444 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0xfffff", get_tok_str(token
, NULL
));
446 /* U-type instruction:
450 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | (rs2
->e
.v
<< 12));
453 static int parse_fence_operand(){
455 if ( tok
== TOK_ASM_or
){
456 // we are in a fence instruction, parse as output read
457 t
= TOK_ASM_or_fence
;
460 return t
- (TOK_ASM_w_fence
- 1);
463 static void asm_fence_opcode(TCCState
*s1
, int token
){
464 // `fence` is both an instruction and a pseudoinstruction:
465 // `fence` expands to `fence iorw, iorw`
466 int succ
= 0xF, pred
= 0xF;
467 if (tok
!= TOK_LINEFEED
&& tok
!= ';' && tok
!= CH_EOF
){
468 pred
= parse_fence_operand();
469 if ( pred
> 0xF || pred
< 0) {
470 tcc_error("'%s': Expected first operand that is a valid predecessor operand", get_tok_str(token
, NULL
));
473 succ
= parse_fence_operand();
474 if ( succ
> 0xF || succ
< 0) {
475 tcc_error("'%s': Expected second operand that is a valid successor operand", get_tok_str(token
, NULL
));
478 asm_emit_opcode((0x3 << 2) | 3 | (0 << 12) | succ
<<20 | pred
<<24);
481 static void asm_binary_opcode(TCCState
* s1
, int token
)
483 Operand imm
= { OP_IM12S
};
488 parse_operands(s1
, &ops
[0], 2);
491 asm_emit_u(token
, (0xD << 2) | 3, &ops
[0], &ops
[1]);
494 asm_emit_u(token
, (0x05 << 2) | 3, &ops
[0], &ops
[1]);
499 asm_emit_cr(token
, 2 | (9 << 12), ops
, ops
+ 1);
502 asm_emit_cr(token
, 2 | (8 << 12), ops
, ops
+ 1);
505 case TOK_ASM_c_addi16sp
:
506 asm_emit_ci(token
, 1 | (3 << 13), ops
, ops
+ 1);
509 asm_emit_ci(token
, 1, ops
, ops
+ 1);
511 case TOK_ASM_c_addiw
:
512 asm_emit_ci(token
, 1 | (1 << 13), ops
, ops
+ 1);
514 case TOK_ASM_c_fldsp
:
515 asm_emit_ci(token
, 2 | (1 << 13), ops
, ops
+ 1);
517 case TOK_ASM_c_flwsp
: /* RV32FC-only */
518 asm_emit_ci(token
, 2 | (3 << 13), ops
, ops
+ 1);
521 asm_emit_ci(token
, 2 | (3 << 13), ops
, ops
+ 1);
524 asm_emit_ci(token
, 1 | (2 << 13), ops
, ops
+ 1);
527 asm_emit_ci(token
, 1 | (3 << 13), ops
, ops
+ 1);
530 asm_emit_ci(token
, 2 | (2 << 13), ops
, ops
+ 1);
533 asm_emit_ci(token
, 2, ops
, ops
+ 1);
536 case TOK_ASM_c_addi4spn
:
537 asm_emit_ciw(token
, 0, ops
, ops
+ 1);
540 #define CA (1 | (3 << 10) | (4 << 13))
542 asm_emit_ca(token
, CA
| (1 << 5) | (1 << 12), ops
, ops
+ 1);
545 asm_emit_ca(token
, CA
| (3 << 5), ops
, ops
+ 1);
548 asm_emit_ca(token
, CA
| (2 << 5), ops
, ops
+ 1);
551 asm_emit_ca(token
, CA
, ops
, ops
+ 1);
554 asm_emit_ca(token
, CA
| (1 << 12), ops
, ops
+ 1);
557 asm_emit_ca(token
, CA
| (1 << 5), ops
, ops
+ 1);
562 asm_emit_cb(token
, 1 | (2 << 10) | (4 << 13), ops
, ops
+ 1);
565 asm_emit_cb(token
, 1 | (6 << 13), ops
, ops
+ 1);
568 asm_emit_cb(token
, 1 | (7 << 13), ops
, ops
+ 1);
571 asm_emit_cb(token
, 1 | (1 << 10) | (4 << 13), ops
, ops
+ 1);
574 asm_emit_cb(token
, 1 | (4 << 13), ops
, ops
+ 1);
578 asm_emit_css(token
, 2 | (7 << 13), ops
, ops
+ 1);
581 asm_emit_css(token
, 2 | (6 << 13), ops
, ops
+ 1);
583 case TOK_ASM_c_fswsp
: /* RV32FC-only */
584 asm_emit_css(token
, 2 | (7 << 13), ops
, ops
+ 1);
586 case TOK_ASM_c_fsdsp
:
587 asm_emit_css(token
, 2 | (5 << 13), ops
, ops
+ 1);
590 /* pseudoinstructions */
594 asm_emit_u(token
, 3 | (5 << 2), ops
, ops
+ 1);
596 asm_emit_i(token
, 3 | (2 << 12), ops
, ops
, ops
+ 1);
600 asm_emit_u(token
, 3 | (5 << 2), ops
, ops
+ 1);
602 asm_emit_i(token
, 3 | (4 << 2), ops
, ops
, ops
+ 1);
605 if(ops
[1].type
!= OP_IM32
&& ops
[1].type
!= OP_IM12S
){
606 tcc_error("'%s': Expected first source operand that is an immediate value between 0 and 0xFFFFFFFFFFFFFFFF", get_tok_str(token
, NULL
));
609 hi
= (int64_t)ops
[1].e
.v
>> 32;
613 imm
.e
.v
= ((hi
+ 0x800) & 0xfffff000) >> 12;
614 /* lui rd, HI_20(HI_32(imm)) */
615 asm_emit_u(token
, (0xD << 2) | 3, &ops
[0], &imm
);
616 /* addi rd, rd, LO_12(HI_32(imm)) */
617 imm
.e
.v
= (int32_t)hi
<<20>>20;
618 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
619 /* slli rd, rd, 12 */
621 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[0], &imm
);
622 /* addi rd, rd, HI_12(LO_32(imm)) */
623 imm
.e
.v
= (lo
+ (1<<19)) >> 20;
624 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
625 /* slli rd, rd, 12 */
627 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[0], &imm
);
628 /* addi rd, rd, HI_12(LO_20(LO_32imm)) */
631 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
634 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[0], &imm
);
635 /* addi rd, rd, LO_8(LO_20(LO_32imm)) */
637 imm
.e
.v
= lo
<< 20 >> 20;
638 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
642 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[1], &imm
);
645 /* xori rd, rs, -1 */
647 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &imm
);
652 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &zero
, &imm
);
657 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &zero
, &imm
);
661 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(5));
662 greloca(cur_text_section
, ops
->e
.sym
, ind
, R_RISCV_CALL
, 0);
663 /* jalr zero, 0(x5) */
664 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(5));
667 /* sltiu rd, rs, 1 */
669 asm_emit_i(token
, (0x4 << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &imm
);
672 /* sltu rd, zero, rs */
674 asm_emit_r(token
, (0xC << 2) | 3 | (3 << 12), &ops
[0], &zero
, &ops
[1]);
677 /* slt rd, rs, zero */
678 asm_emit_r(token
, (0xC << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &zero
);
681 /* slt rd, zero, rs */
682 asm_emit_r(token
, (0xC << 2) | 3 | (2 << 12), &ops
[0], &zero
, &ops
[1]);
686 expect("binary instruction");
690 /* caller: Add funct3, funct7 into opcode */
691 static void asm_emit_r(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs1
, const Operand
* rs2
)
693 if (rd
->type
!= OP_REG
) {
694 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
696 if (rs1
->type
!= OP_REG
) {
697 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
699 if (rs2
->type
!= OP_REG
) {
700 tcc_error("'%s': Expected second source operand that is a register or immediate", get_tok_str(token
, NULL
));
702 /* R-type instruction:
709 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
));
712 /* caller: Add funct3 into opcode */
713 static void asm_emit_i(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs1
, const Operand
* rs2
)
715 if (rd
->type
!= OP_REG
) {
716 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
718 if (rs1
->type
!= OP_REG
) {
719 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
721 if (rs2
->type
!= OP_IM12S
) {
722 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token
, NULL
));
724 /* I-type instruction:
731 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | ENCODE_RS1(rs1
->reg
) | (rs2
->e
.v
<< 20));
734 static void asm_emit_j(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs2
)
738 if (rd
->type
!= OP_REG
) {
739 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
741 if (rs2
->type
!= OP_IM12S
&& rs2
->type
!= OP_IM32
) {
742 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token
, NULL
));
747 /* even offsets in a +- 1 MiB range */
748 if ((int)imm
> (1 << 20) -1 || (int)imm
<= -1 * ((1 << 20) -1)) {
749 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0x1fffff", get_tok_str(token
, NULL
));
753 tcc_error("'%s': Expected second source operand that is an even immediate value", get_tok_str(token
, NULL
));
755 /* J-type instruction:
762 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | (((imm
>> 20) & 1) << 31) | (((imm
>> 1) & 0x3ff) << 21) | (((imm
>> 11) & 1) << 20) | (((imm
>> 12) & 0xff) << 12));
765 static void asm_mem_access_opcode(TCCState
*s1
, int token
)
769 parse_mem_access_operands(s1
, &ops
[0]);
771 /* Pseudoinstruction: inst reg, label
775 * And with the proper relocation to label
777 if (ops
[1].type
== OP_IM32
&& ops
[1].e
.sym
&& ops
[1].e
.sym
->type
.t
& VT_STATIC
){
779 /* set the offset to zero */
780 ops
[2].type
= OP_IM12S
;
783 asm_emit_u(token
, (0x05 << 2) | 3, &ops
[0], &ops
[2]);
787 // l{b|h|w|d}[u] rd, imm(rs1); I-format
789 asm_emit_i(token
, (0x0 << 2) | 3, &ops
[0], &ops
[1], &ops
[2]);
792 asm_emit_i(token
, (0x0 << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
795 asm_emit_i(token
, (0x0 << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &ops
[2]);
798 asm_emit_i(token
, (0x0 << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &ops
[2]);
801 asm_emit_i(token
, (0x0 << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
804 asm_emit_i(token
, (0x0 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
807 asm_emit_i(token
, (0x0 << 2) | 3 | (6 << 12), &ops
[0], &ops
[1], &ops
[2]);
810 // s{b|h|w|d} rs2, imm(rs1); S-format (with rsX swapped)
812 asm_emit_s(token
, (0x8 << 2) | 3 | (0 << 12), &ops
[1], &ops
[0], &ops
[2]);
815 asm_emit_s(token
, (0x8 << 2) | 3 | (1 << 12), &ops
[1], &ops
[0], &ops
[2]);
818 asm_emit_s(token
, (0x8 << 2) | 3 | (2 << 12), &ops
[1], &ops
[0], &ops
[2]);
821 asm_emit_s(token
, (0x8 << 2) | 3 | (3 << 12), &ops
[1], &ops
[0], &ops
[2]);
826 static void asm_branch_opcode(TCCState
*s1
, int token
, int argc
)
829 parse_operands(s1
, &ops
[0], argc
-1);
831 parse_branch_offset_operand(s1
, &ops
[argc
-1]);
834 /* branch (RS1, RS2, IMM); B-format */
836 asm_emit_b(token
, 0x63 | (0 << 12), ops
, ops
+ 1, ops
+ 2);
839 asm_emit_b(token
, 0x63 | (1 << 12), ops
, ops
+ 1, ops
+ 2);
842 asm_emit_b(token
, 0x63 | (4 << 12), ops
, ops
+ 1, ops
+ 2);
845 asm_emit_b(token
, 0x63 | (5 << 12), ops
, ops
+ 1, ops
+ 2);
848 asm_emit_b(token
, 0x63 | (6 << 12), ops
, ops
+ 1, ops
+ 2);
851 asm_emit_b(token
, 0x63 | (7 << 12), ops
, ops
+ 1, ops
+ 2);
853 /* related pseudoinstructions */
855 asm_emit_b(token
, 0x63 | (4 << 12), ops
+ 1, ops
, ops
+ 2);
858 asm_emit_b(token
, 0x63 | (5 << 12), ops
+ 1, ops
, ops
+ 2);
861 asm_emit_b(token
, 0x63 | (6 << 12), ops
+ 1, ops
, ops
+ 2);
864 asm_emit_b(token
, 0x63 | (7 << 12), ops
+ 1, ops
, ops
+ 2);
866 /* shorter pseudoinstructions */
868 /* bne rs, zero, offset */
869 asm_emit_b(token
, 0x63 | (1 << 12), &ops
[0], &zero
, &ops
[1]);
872 /* bne rs, zero, offset */
873 asm_emit_b(token
, 0x63 | (0 << 12), &ops
[0], &zero
, &ops
[1]);
876 /* bge rs, zero, offset */
877 asm_emit_b(token
, 0x63 | (5 << 12), &ops
[0], &zero
, &ops
[1]);
880 /* bge zero, rs, offset */
881 asm_emit_b(token
, 0x63 | (5 << 12), &zero
, &ops
[0], &ops
[1]);
884 /* blt rs, zero, offset */
885 asm_emit_b(token
, 0x63 | (4 << 12), &ops
[0], &zero
, &ops
[1]);
888 /* blt zero, rs, offset */
889 asm_emit_b(token
, 0x63 | (4 << 12), &zero
, &ops
[0], &ops
[1]);
894 static void asm_ternary_opcode(TCCState
*s1
, int token
)
897 parse_operands(s1
, &ops
[0], 3);
901 asm_emit_r(token
, (0xC << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
904 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
907 asm_emit_r(token
, (0xC << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
910 asm_emit_i(token
, (0x4 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
913 asm_emit_r(token
, (0xC << 2) | 3 | (5 << 12) | (32 << 25), &ops
[0], &ops
[1], &ops
[2]);
916 asm_emit_i(token
, (0x4 << 2) | 3 | (5 << 12) | (16 << 26), &ops
[0], &ops
[1], &ops
[2]);
919 asm_emit_r(token
, (0xE << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
922 asm_emit_i(token
, (6 << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
925 asm_emit_r(token
, (0xE << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
928 asm_emit_i(token
, (0x6 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
931 asm_emit_r(token
, (0xE << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
934 asm_emit_i(token
, (0x6 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
937 // Arithmetic (RD,RS1,(RS2|IMM)); R-format, I-format or U-format
940 asm_emit_r(token
, (0xC << 2) | 3, &ops
[0], &ops
[1], &ops
[2]);
943 asm_emit_i(token
, (4 << 2) | 3, &ops
[0], &ops
[1], &ops
[2]);
946 asm_emit_r(token
, (0xC << 2) | 3 | (32 << 25), &ops
[0], &ops
[1], &ops
[2]);
949 asm_emit_r(token
, (0xE << 2) | 3 | (0 << 12), &ops
[0], &ops
[1], &ops
[2]);
951 case TOK_ASM_addiw
: // 64 bit
952 asm_emit_i(token
, (0x6 << 2) | 3 | (0 << 12), &ops
[0], &ops
[1], &ops
[2]);
955 asm_emit_r(token
, (0xE << 2) | 3 | (0 << 12) | (32 << 25), &ops
[0], &ops
[1], &ops
[2]);
958 // Logical (RD,RS1,(RS2|IMM)); R-format or I-format
961 asm_emit_r(token
, (0xC << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
964 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
967 asm_emit_r(token
, (0xC << 2) | 3 | (6 << 12), &ops
[0], &ops
[1], &ops
[2]);
970 asm_emit_i(token
, (0x4 << 2) | 3 | (6 << 12), &ops
[0], &ops
[1], &ops
[2]);
973 asm_emit_r(token
, (0xC << 2) | 3 | (7 << 12), &ops
[0], &ops
[1], &ops
[2]);
976 asm_emit_i(token
, (0x4 << 2) | 3 | (7 << 12), &ops
[0], &ops
[1], &ops
[2]);
979 // Compare (RD,RS1,(RS2|IMM)); R-format or I-format
982 asm_emit_r(token
, (0xC << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &ops
[2]);
985 asm_emit_i(token
, (0x4 << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &ops
[2]);
988 asm_emit_r(token
, (0xC << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &ops
[2]);
991 asm_emit_i(token
, (0x4 << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &ops
[2]);
996 asm_emit_r(token
, 0x33 | (4 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
999 asm_emit_r(token
, 0x33 | (5 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1002 asm_emit_r(token
, 0x3b | (5 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1005 asm_emit_r(token
, 0x3b | (4 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1008 asm_emit_r(token
, 0x33 | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1011 asm_emit_r(token
, 0x33 | (1 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1013 case TOK_ASM_mulhsu
:
1014 asm_emit_r(token
, 0x33 | (2 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1017 asm_emit_r(token
, 0x33 | (3 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1020 asm_emit_r(token
, 0x3b | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1023 asm_emit_r(token
, 0x33 | (6 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1026 asm_emit_r(token
, 0x33 | (7 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1029 asm_emit_r(token
, 0x3b | (7 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1032 asm_emit_r(token
, 0x3b | (6 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1035 /* Zicsr extension; (rd, csr, rs/uimm) */
1037 asm_emit_i(token
, 0x73 | (3 << 12), ops
, ops
+ 2, ops
+ 1);
1039 case TOK_ASM_csrrci
:
1040 /* using rs1 field for uimmm */
1041 ops
[2].type
= OP_REG
;
1042 asm_emit_i(token
, 0x73 | (7 << 12), ops
, ops
+ 2, ops
+ 1);
1045 asm_emit_i(token
, 0x73 | (2 << 12), ops
, ops
+ 2, ops
+ 1);
1047 case TOK_ASM_csrrsi
:
1048 ops
[2].type
= OP_REG
;
1049 asm_emit_i(token
, 0x73 | (6 << 12), ops
, ops
+ 2, ops
+ 1);
1052 asm_emit_i(token
, 0x73 | (1 << 12), ops
, ops
+ 2, ops
+ 1);
1054 case TOK_ASM_csrrwi
:
1055 ops
[2].type
= OP_REG
;
1056 asm_emit_i(token
, 0x73 | (5 << 12), ops
, ops
+ 2, ops
+ 1);
1060 /* register-based loads and stores (RD, RS1, IMM); CL-format */
1062 asm_emit_cl(token
, 1 << 13, ops
, ops
+ 1, ops
+ 2);
1064 case TOK_ASM_c_flw
: /* RV32FC-only */
1065 asm_emit_cl(token
, 3 << 13, ops
, ops
+ 1, ops
+ 2);
1068 asm_emit_cs(token
, 5 << 13, ops
, ops
+ 1, ops
+ 2);
1070 case TOK_ASM_c_fsw
: /* RV32FC-only */
1071 asm_emit_cs(token
, 7 << 13, ops
, ops
+ 1, ops
+ 2);
1074 asm_emit_cl(token
, 3 << 13, ops
, ops
+ 1, ops
+ 2);
1077 asm_emit_cl(token
, 2 << 13, ops
, ops
+ 1, ops
+ 2);
1080 asm_emit_cs(token
, 7 << 13, ops
, ops
+ 1, ops
+ 2);
1083 asm_emit_cs(token
, 6 << 13, ops
, ops
+ 1, ops
+ 2);
1087 expect("ternary instruction");
1091 static void asm_atomic_opcode(TCCState
*s1
, int token
)
1095 parse_operand(s1
, &ops
[0]);
1098 if ( token
<= TOK_ASM_lr_d_aqrl
&& token
>= TOK_ASM_lr_w
) {
1101 parse_operand(s1
, &ops
[1]);
1106 parse_operand(s1
, &ops
[2]);
1111 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1113 case TOK_ASM_lr_w_aq
:
1114 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1116 case TOK_ASM_lr_w_rl
:
1117 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1119 case TOK_ASM_lr_w_aqrl
:
1120 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1124 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1126 case TOK_ASM_lr_d_aq
:
1127 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1129 case TOK_ASM_lr_d_rl
:
1130 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1132 case TOK_ASM_lr_d_aqrl
:
1133 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1137 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1139 case TOK_ASM_sc_w_aq
:
1140 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1142 case TOK_ASM_sc_w_rl
:
1143 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1145 case TOK_ASM_sc_w_aqrl
:
1146 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1150 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1152 case TOK_ASM_sc_d_aq
:
1153 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1155 case TOK_ASM_sc_d_rl
:
1156 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1158 case TOK_ASM_sc_d_aqrl
:
1159 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1164 /* caller: Add funct3 and func5 to opcode */
1165 static void asm_emit_a(int token
, uint32_t opcode
, const Operand
*rd1
, const Operand
*rs2
, const Operand
*rs1
, int aq
, int rl
)
1167 if (rd1
->type
!= OP_REG
)
1168 tcc_error("'%s': Expected first destination operand that is a register", get_tok_str(token
, NULL
));
1169 if (rs2
->type
!= OP_REG
)
1170 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token
, NULL
));
1171 if (rs1
->type
!= OP_REG
)
1172 tcc_error("'%s': Expected third source operand that is a register", get_tok_str(token
, NULL
));
1173 /* A-type instruction:
1182 opcode always fixed pos. */
1183 gen_le32(opcode
| ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
) | ENCODE_RD(rd1
->reg
) | aq
<< 26 | rl
<< 25);
1186 /* caller: Add funct3 to opcode */
1187 static void asm_emit_s(int token
, uint32_t opcode
, const Operand
* rs1
, const Operand
* rs2
, const Operand
* imm
)
1189 if (rs1
->type
!= OP_REG
) {
1190 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
1192 if (rs2
->type
!= OP_REG
) {
1193 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token
, NULL
));
1195 if (imm
->type
!= OP_IM12S
) {
1196 tcc_error("'%s': Expected third operand that is an immediate value between 0 and 8191", get_tok_str(token
, NULL
));
1199 uint16_t v
= imm
->e
.v
;
1200 /* S-type instruction:
1207 opcode always fixed pos. */
1208 gen_le32(opcode
| ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
) | ((v
& 0x1F) << 7) | ((v
>> 5) << 25));
1212 static void asm_emit_b(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*imm
)
1216 if (rs1
->type
!= OP_REG
) {
1217 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
1219 if (rs2
->type
!= OP_REG
) {
1220 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
1222 if (imm
->type
!= OP_IM12S
) {
1223 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token
, NULL
));
1228 /* B-type instruction:
1237 asm_emit_opcode(opcode
| ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
) | (((offset
>> 1) & 0xF) << 8) | (((offset
>> 5) & 0x1f) << 25) | (((offset
>> 11) & 1) << 7) | (((offset
>> 12) & 1) << 31));
1240 ST_FUNC
void asm_opcode(TCCState
*s1
, int token
)
1243 case TOK_ASM_ebreak
:
1245 case TOK_ASM_fence_i
:
1250 asm_nullary_opcode(s1
, token
);
1254 asm_fence_opcode(s1
, token
);
1257 case TOK_ASM_rdcycle
:
1258 case TOK_ASM_rdcycleh
:
1259 case TOK_ASM_rdtime
:
1260 case TOK_ASM_rdtimeh
:
1261 case TOK_ASM_rdinstret
:
1262 case TOK_ASM_rdinstreth
:
1263 asm_unary_opcode(s1
, token
);
1268 asm_binary_opcode(s1
, token
);
1282 asm_mem_access_opcode(s1
, token
);
1286 asm_jalr_opcode(s1
, token
); /* it can be a pseudo instruction too*/
1289 asm_jal_opcode(s1
, token
); /* jal zero, offset*/
1292 asm_jal_opcode(s1
, token
); /* it can be a pseudo instruction too*/
1330 case TOK_ASM_mulhsu
:
1337 /* Zicsr extension */
1339 case TOK_ASM_csrrci
:
1341 case TOK_ASM_csrrsi
:
1343 case TOK_ASM_csrrwi
:
1344 asm_ternary_opcode(s1
, token
);
1354 asm_branch_opcode(s1
, token
, 3);
1358 case TOK_ASM_c_ebreak
:
1360 asm_nullary_opcode(s1
, token
);
1365 case TOK_ASM_c_jalr
:
1367 asm_unary_opcode(s1
, token
);
1371 case TOK_ASM_c_addi16sp
:
1372 case TOK_ASM_c_addi4spn
:
1373 case TOK_ASM_c_addi
:
1374 case TOK_ASM_c_addiw
:
1375 case TOK_ASM_c_addw
:
1377 case TOK_ASM_c_andi
:
1378 case TOK_ASM_c_beqz
:
1379 case TOK_ASM_c_bnez
:
1380 case TOK_ASM_c_fldsp
:
1381 case TOK_ASM_c_flwsp
:
1382 case TOK_ASM_c_fsdsp
:
1383 case TOK_ASM_c_fswsp
:
1384 case TOK_ASM_c_ldsp
:
1387 case TOK_ASM_c_lwsp
:
1390 case TOK_ASM_c_sdsp
:
1391 case TOK_ASM_c_slli
:
1392 case TOK_ASM_c_srai
:
1393 case TOK_ASM_c_srli
:
1395 case TOK_ASM_c_subw
:
1396 case TOK_ASM_c_swsp
:
1398 asm_binary_opcode(s1
, token
);
1409 asm_ternary_opcode(s1
, token
);
1412 /* pseudoinstructions */
1415 asm_nullary_opcode(s1
, token
);
1421 asm_unary_opcode(s1
, token
);
1436 asm_binary_opcode(s1
, token
);
1445 asm_branch_opcode(s1
, token
, 2);
1452 asm_branch_opcode(s1
, token
, 3);
1455 /* Atomic operations */
1457 case TOK_ASM_lr_w_aq
:
1458 case TOK_ASM_lr_w_rl
:
1459 case TOK_ASM_lr_w_aqrl
:
1461 case TOK_ASM_lr_d_aq
:
1462 case TOK_ASM_lr_d_rl
:
1463 case TOK_ASM_lr_d_aqrl
:
1465 case TOK_ASM_sc_w_aq
:
1466 case TOK_ASM_sc_w_rl
:
1467 case TOK_ASM_sc_w_aqrl
:
1469 case TOK_ASM_sc_d_aq
:
1470 case TOK_ASM_sc_d_rl
:
1471 case TOK_ASM_sc_d_aqrl
:
1472 asm_atomic_opcode(s1
, token
);
1476 expect("known instruction");
1480 static int asm_parse_csrvar(int t
)
1487 case TOK_ASM_fflags
:
1491 case TOK_ASM_instret
:
1495 case TOK_ASM_cycleh
:
1497 case TOK_ASM_instreth
:
1506 ST_FUNC
void subst_asm_operand(CString
*add_str
, SValue
*sv
, int modifier
)
1511 if ((r
& VT_VALMASK
) == VT_CONST
) {
1512 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n' &&
1514 //cstr_ccat(add_str, '#');
1517 const char *name
= get_tok_str(sv
->sym
->v
, NULL
);
1518 if (sv
->sym
->v
>= SYM_FIRST_ANOM
) {
1519 /* In case of anonymous symbols ("L.42", used
1520 for static data labels) we can't find them
1521 in the C symbol table when later looking up
1522 this name. So enter them now into the asm label
1523 list when we still know the symbol. */
1524 get_asm_sym(tok_alloc(name
, strlen(name
))->tok
, sv
->sym
);
1526 if (tcc_state
->leading_underscore
)
1527 cstr_ccat(add_str
, '_');
1528 cstr_cat(add_str
, name
, -1);
1529 if ((uint32_t) sv
->c
.i
== 0)
1531 cstr_ccat(add_str
, '+');
1534 if (modifier
== 'n')
1536 if (modifier
== 'z' && sv
->c
.i
== 0) {
1537 cstr_cat(add_str
, "zero", -1);
1539 cstr_printf(add_str
, "%d", (int) sv
->c
.i
);
1542 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1543 cstr_printf(add_str
, "%d", (int) sv
->c
.i
);
1544 } else if (r
& VT_LVAL
) {
1545 reg
= r
& VT_VALMASK
;
1546 if (reg
>= VT_CONST
)
1547 tcc_internal_error("");
1548 if ((sv
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1549 (sv
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1550 /* floating point register */
1551 reg
= TOK_ASM_f0
+ reg
;
1553 /* general purpose register */
1554 reg
= TOK_ASM_x0
+ reg
;
1556 cstr_cat(add_str
, get_tok_str(reg
, NULL
), -1);
1559 reg
= r
& VT_VALMASK
;
1560 if (reg
>= VT_CONST
)
1561 tcc_internal_error("");
1562 if ((sv
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1563 (sv
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1564 /* floating point register */
1565 reg
= TOK_ASM_f0
+ reg
;
1567 /* general purpose register */
1568 reg
= TOK_ASM_x0
+ reg
;
1570 cstr_cat(add_str
, get_tok_str(reg
, NULL
), -1);
1574 /* TCC does not use RISC-V register numbers internally, it uses 0-8 for
1575 * integers and 8-16 for floats instead */
1576 static int tcc_ireg(int r
){
1577 return REG_VALUE(r
) - 10;
1579 static int tcc_freg(int r
){
1580 return REG_VALUE(r
) - 10 + 8;
1583 /* generate prolog and epilog code for asm statement */
1584 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1585 int nb_outputs
, int is_output
,
1586 uint8_t *clobber_regs
,
1589 uint8_t regs_allocated
[NB_ASM_REGS
];
1593 static const uint8_t reg_saved
[] = {
1594 // General purpose regs
1595 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
1597 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59
1600 /* mark all used registers */
1601 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1602 for(i
= 0; i
< nb_operands
; i
++) {
1605 regs_allocated
[op
->reg
] = 1;
1610 /* generate reg save code */
1611 for(i
= 0; i
< sizeof(reg_saved
)/sizeof(reg_saved
[0]); i
++) {
1613 if (regs_allocated
[reg
]) {
1615 /* addi sp, sp, -offset */
1616 gen_le32((4 << 2) | 3 |
1617 ENCODE_RD(2) | ENCODE_RS1(2) | -8 << 20);
1618 if (REG_IS_FLOAT(reg
)){
1619 /* fsd reg, offset(sp) */
1620 gen_le32( 0x27 | (3 << 12) |
1621 ENCODE_RS2(reg
) | ENCODE_RS1(2) );
1623 /* sd reg, offset(sp) */
1624 gen_le32((0x8 << 2) | 3 | (3 << 12) |
1625 ENCODE_RS2(reg
) | ENCODE_RS1(2) );
1630 /* generate load code */
1631 for(i
= 0; i
< nb_operands
; i
++) {
1634 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1636 /* memory reference case (for both input and
1640 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
| VT_LVAL
;
1642 load(tcc_ireg(op
->reg
), &sv
);
1643 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1644 /* load value in register */
1645 if ((op
->vt
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1646 (op
->vt
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1647 load(tcc_freg(op
->reg
), op
->vt
);
1649 load(tcc_ireg(op
->reg
), op
->vt
);
1652 tcc_error("long long not implemented");
1658 /* generate save code */
1659 for(i
= 0 ; i
< nb_outputs
; i
++) {
1662 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1663 if (!op
->is_memory
) {
1666 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1668 load(tcc_ireg(out_reg
), &sv
);
1671 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1672 store(tcc_ireg(op
->reg
), &sv
);
1675 if ((op
->vt
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1676 (op
->vt
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1677 store(tcc_freg(op
->reg
), op
->vt
);
1679 store(tcc_ireg(op
->reg
), op
->vt
);
1682 tcc_error("long long not implemented");
1687 /* generate reg restore code for floating point registers */
1688 for(i
= sizeof(reg_saved
)/sizeof(reg_saved
[0]) - 1; i
>= 0; i
--) {
1690 if (regs_allocated
[reg
]) {
1692 if (REG_IS_FLOAT(reg
)){
1693 /* fld reg, offset(sp) */
1694 gen_le32(7 | (3 << 12) |
1695 ENCODE_RD(reg
) | ENCODE_RS1(2) | 0);
1697 /* ld reg, offset(sp) */
1698 gen_le32(3 | (3 << 12) |
1699 ENCODE_RD(reg
) | ENCODE_RS1(2) | 0);
1701 /* addi sp, sp, offset */
1702 gen_le32((4 << 2) | 3 |
1703 ENCODE_RD(2) | ENCODE_RS1(2) | 8 << 20);
1709 /* return the constraint priority (we allocate first the lowest
1710 numbered constraints) */
1711 static inline int constraint_priority(const char *str
)
1713 // TODO: How is this chosen??
1714 int priority
, c
, pr
;
1716 /* we take the lowest priority */
1724 case 'A': // address that is held in a general-purpose register.
1725 case 'S': // constraint that matches an absolute symbolic address.
1726 case 'f': // register [float]
1727 case 'r': // register [general]
1728 case 'p': // valid memory address for load,store [general]
1731 case 'I': // 12 bit signed immedate
1732 case 'i': // immediate integer operand, including symbolic constants [general]
1733 case 'm': // memory operand [general]
1734 case 'g': // general-purpose-register, memory, immediate integer [general]
1738 tcc_error("unimp: constraint '%c'", c
);
1740 tcc_error("unknown constraint '%d'", c
);
1748 static const char *skip_constraint_modifiers(const char *p
)
1750 /* Constraint modifier:
1751 = Operand is written to by this instruction
1752 + Operand is both read and written to by this instruction
1753 % Instruction is commutative for this operand and the following operand.
1755 Per-alternative constraint modifier:
1756 & Operand is clobbered before the instruction is done using the input operands
1758 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
1763 #define REG_OUT_MASK 0x01
1764 #define REG_IN_MASK 0x02
1766 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1768 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
,
1769 int nb_operands
, int nb_outputs
,
1770 const uint8_t *clobber_regs
,
1773 /* TODO: Simple constraints
1775 o memory operand that is offsetable
1776 V memory but not offsetable
1777 < memory operand with autodecrement addressing is allowed. Restrictions apply.
1778 > memory operand with autoincrement addressing is allowed. Restrictions apply.
1779 n immediate integer operand with a known numeric value
1780 E immediate floating operand (const_double) is allowed, but only if target=host
1781 F immediate floating operand (const_double or const_vector) is allowed
1782 s immediate integer operand whose value is not an explicit integer
1783 X any operand whatsoever
1784 0...9 (postfix); (can also be more than 1 digit number); an operand that matches the specified operand number is allowed
1787 /* TODO: RISCV constraints
1789 K A 5-bit unsigned immediate for CSR access instructions.
1790 A An address that is held in a general-purpose register.
1791 S A constraint that matches an absolute symbolic address.
1792 vr A vector register (if available)..
1793 vd A vector register, excluding v0 (if available).
1794 vm A vector register, only v0 (if available).
1797 int sorted_op
[MAX_ASM_OPERANDS
];
1798 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
1800 uint8_t regs_allocated
[NB_ASM_REGS
];
1803 for (i
= 0; i
< nb_operands
; i
++) {
1805 op
->input_index
= -1;
1811 /* compute constraint priority and evaluate references to output
1812 constraints if input constraints */
1813 for (i
= 0; i
< nb_operands
; i
++) {
1815 str
= op
->constraint
;
1816 str
= skip_constraint_modifiers(str
);
1817 if (isnum(*str
) || *str
== '[') {
1818 /* this is a reference to another constraint */
1819 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
1820 if ((unsigned) k
>= i
|| i
< nb_outputs
)
1821 tcc_error("invalid reference in constraint %d ('%s')",
1824 if (operands
[k
].input_index
>= 0)
1825 tcc_error("cannot reference twice the same operand");
1826 operands
[k
].input_index
= i
;
1828 } else if ((op
->vt
->r
& VT_VALMASK
) == VT_LOCAL
1830 && (reg
= op
->vt
->sym
->r
& VT_VALMASK
) < VT_CONST
) {
1834 op
->priority
= constraint_priority(str
);
1838 /* sort operands according to their priority */
1839 for (i
= 0; i
< nb_operands
; i
++)
1841 for (i
= 0; i
< nb_operands
- 1; i
++) {
1842 for (j
= i
+ 1; j
< nb_operands
; j
++) {
1843 p1
= operands
[sorted_op
[i
]].priority
;
1844 p2
= operands
[sorted_op
[j
]].priority
;
1847 sorted_op
[i
] = sorted_op
[j
];
1853 for (i
= 0; i
< NB_ASM_REGS
; i
++) {
1854 if (clobber_regs
[i
])
1855 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
1857 regs_allocated
[i
] = 0;
1860 /* allocate registers and generate corresponding asm moves */
1861 for (i
= 0; i
< nb_operands
; i
++) {
1864 str
= op
->constraint
;
1865 /* no need to allocate references */
1866 if (op
->ref_index
>= 0)
1868 /* select if register is used for output, input or both */
1869 if (op
->input_index
>= 0) {
1870 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1871 } else if (j
< nb_outputs
) {
1872 reg_mask
= REG_OUT_MASK
;
1874 reg_mask
= REG_IN_MASK
;
1877 if (is_reg_allocated(op
->reg
))
1879 ("asm regvar requests register that's taken already");
1885 case '=': // Operand is written-to
1887 case '+': // Operand is both READ and written-to
1890 case '&': // Operand is clobbered before the instruction is done using the input operands
1891 if (j
>= nb_outputs
)
1892 tcc_error("'%c' modifier can only be applied to outputs", c
);
1893 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1895 case 'r': // general-purpose register
1896 case 'p': // loadable/storable address
1897 /* any general register */
1899 if ((reg
= op
->reg
) >= 0)
1901 else for (reg
= 10; reg
<= 18; reg
++) {
1902 if (!is_reg_allocated(reg
))
1907 /* now we can reload in the register */
1910 regs_allocated
[reg
] |= reg_mask
;
1912 case 'f': // floating pont register
1913 /* floating point register */
1914 /* From fa0 to fa7 */
1915 if ((reg
= op
->reg
) >= 0)
1917 else for (reg
= 42; reg
<= 50; reg
++) {
1918 if (!is_reg_allocated(reg
))
1922 case 'I': // I-Type 12 bit signed immediate
1923 case 'i': // immediate integer operand, including symbolic constants
1924 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1927 case 'm': // memory operand
1928 case 'g': // any register
1929 /* nothing special to do because the operand is already in
1930 memory, except if the pointer itself is stored in a
1931 memory variable (VT_LLOCAL case) */
1932 /* XXX: fix constant case */
1933 /* if it is a reference to a memory zone, it must lie
1934 in a register, so we reserve the register in the
1935 input registers and a load will be generated
1937 if (j
< nb_outputs
|| c
== 'm') {
1938 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1939 /* any general register: from a0 to a7 */
1940 for (reg
= 10; reg
<= 18; reg
++) {
1941 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1946 /* now we can reload in the register */
1947 regs_allocated
[reg
] |= REG_IN_MASK
;
1954 tcc_error("asm constraint %d ('%s') could not be satisfied",
1958 /* if a reference is present for that operand, we assign it too */
1959 if (op
->input_index
>= 0) {
1960 operands
[op
->input_index
].reg
= op
->reg
;
1961 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1965 /* compute out_reg. It is used to store outputs registers to memory
1966 locations references by pointers (VT_LLOCAL case) */
1968 for (i
= 0; i
< nb_operands
; i
++) {
1971 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&& !op
->is_memory
) {
1972 if (REG_IS_FLOAT(op
->reg
)){
1973 /* From fa0 to fa7 */
1974 for (reg
= 42; reg
<= 50; reg
++) {
1975 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1980 for (reg
= 10; reg
<= 18; reg
++) {
1981 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1985 tcc_error("could not find free output register for reloading");
1992 /* print sorted constraints */
1994 for (i
= 0; i
< nb_operands
; i
++) {
1997 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1999 op
->id
? get_tok_str(op
->id
, NULL
) : "",
2000 op
->constraint
, op
->vt
->r
, op
->reg
);
2003 printf("out_reg=%d\n", *pout_reg
);
2007 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
)
2012 if (!strcmp(str
, "memory") ||
2013 !strcmp(str
, "cc") ||
2014 !strcmp(str
, "flags"))
2016 ts
= tok_alloc(str
, strlen(str
));
2017 reg
= asm_parse_regvar(ts
->tok
);
2019 tcc_error("invalid clobber register '%s'", str
);
2021 clobber_regs
[reg
] = 1;
2024 ST_FUNC
int asm_parse_regvar (int t
)
2026 /* PC register not implemented */
2027 if (t
>= TOK_ASM_pc
|| t
< TOK_ASM_x0
)
2031 return t
- TOK_ASM_x0
;
2033 if (t
< TOK_ASM_zero
)
2034 return t
- TOK_ASM_f0
+ 32; // Use higher 32 for floating point
2037 if (t
< TOK_ASM_ft0
)
2038 return t
- TOK_ASM_zero
;
2040 return t
- TOK_ASM_ft0
+ 32; // Use higher 32 for floating point
2043 /*************************************************************/
2046 /* caller: Add funct6, funct2 into opcode */
2047 static void asm_emit_ca(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
)
2051 if (rd
->type
!= OP_REG
) {
2052 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2055 if (rs2
->type
!= OP_REG
) {
2056 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2059 /* subtract index of x8 */
2063 /* only registers {x,f}8 to {x,f}15 are valid (3-bit) */
2065 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2069 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2072 /* CA-type instruction:
2079 gen_le16(opcode
| C_ENCODE_RS2(src
) | C_ENCODE_RS1(dst
));
2082 static void asm_emit_cb(int token
, uint16_t opcode
, const Operand
*rs1
, const Operand
*imm
)
2087 if (rs1
->type
!= OP_REG
) {
2088 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2091 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2092 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2098 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token
, NULL
));
2104 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2107 /* CB-type instruction:
2114 /* non-branch also using CB:
2123 case TOK_ASM_c_beqz
:
2124 case TOK_ASM_c_bnez
:
2125 gen_le16(opcode
| C_ENCODE_RS1(src
) | ((NTH_BIT(offset
, 5) | (((offset
>> 1) & 3) << 1) | (((offset
>> 6) & 3) << 3)) << 2) | ((((offset
>> 3) & 3) | NTH_BIT(offset
, 8)) << 10));
2128 gen_le16(opcode
| C_ENCODE_RS1(src
) | ((offset
& 0x1f) << 2) | (NTH_BIT(offset
, 5) << 12));
2133 static void asm_emit_ci(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
)
2137 if (rd
->type
!= OP_REG
) {
2138 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2141 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2142 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2145 immediate
= imm
->e
.v
;
2147 /* CI-type instruction:
2155 case TOK_ASM_c_addi
:
2156 case TOK_ASM_c_addiw
:
2158 case TOK_ASM_c_slli
:
2159 gen_le16(opcode
| ((immediate
& 0x1f) << 2) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 5) << 12));
2161 case TOK_ASM_c_addi16sp
:
2162 gen_le16(opcode
| NTH_BIT(immediate
, 5) << 2 | (((immediate
>> 7) & 3) << 3) | NTH_BIT(immediate
, 6) << 5 | NTH_BIT(immediate
, 4) << 6 | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 9) << 12));
2165 gen_le16(opcode
| (((immediate
>> 12) & 0x1f) << 2) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 17) << 12));
2167 case TOK_ASM_c_fldsp
:
2168 case TOK_ASM_c_ldsp
:
2169 gen_le16(opcode
| (((immediate
>> 6) & 7) << 2) | (((immediate
>> 3) & 2) << 5) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 5) << 12));
2171 case TOK_ASM_c_flwsp
:
2172 case TOK_ASM_c_lwsp
:
2173 gen_le16(opcode
| (((immediate
>> 6) & 3) << 2) | (((immediate
>> 2) & 7) << 4) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 5) << 12));
2179 expect("known instruction");
2183 /* caller: Add funct3 into opcode */
2184 static void asm_emit_ciw(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
)
2189 if (rd
->type
!= OP_REG
) {
2190 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2193 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2194 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2200 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2205 if (nzuimm
> 0x3fc) {
2206 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0x3ff", get_tok_str(token
, NULL
));
2210 tcc_error("'%s': Expected source operand that is a non-zero immediate value divisible by 4", get_tok_str(token
, NULL
));
2213 /* CIW-type instruction:
2219 gen_le16(opcode
| ENCODE_RS2(rd
->reg
) | ((NTH_BIT(nzuimm
, 3) | (NTH_BIT(nzuimm
, 2) << 1) | (((nzuimm
>> 6) & 0xf) << 2) | (((nzuimm
>> 4) & 3) << 6)) << 5));
2222 /* caller: Add funct3 into opcode */
2223 static void asm_emit_cj(int token
, uint16_t opcode
, const Operand
*imm
)
2228 if (imm
->type
!= OP_IM12S
) {
2229 tcc_error("'%s': Expected source operand that is a 12-bit immediate value", get_tok_str(token
, NULL
));
2235 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token
, NULL
));
2238 /* CJ-type instruction:
2240 12...2 offset[11|4|9:8|10|6|7|3:1|5]
2243 gen_le16(opcode
| (NTH_BIT(offset
, 5) << 2) | (((offset
>> 1) & 7) << 3) | (NTH_BIT(offset
, 7) << 6) | (NTH_BIT(offset
, 6) << 7) | (NTH_BIT(offset
, 10) << 8) | (((offset
>> 8) & 3) << 9) | (NTH_BIT(offset
, 4) << 11) | (NTH_BIT(offset
, 11) << 12));
2246 /* caller: Add funct3 into opcode */
2247 static void asm_emit_cl(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*imm
)
2252 if (rd
->type
!= OP_REG
) {
2253 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2256 if (rs1
->type
!= OP_REG
) {
2257 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2260 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2261 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2268 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2272 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2277 if (offset
> 0xff) {
2278 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token
, NULL
));
2282 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token
, NULL
));
2285 /* CL-type instruction:
2297 gen_le16(opcode
| C_ENCODE_RS2(dst
) | C_ENCODE_RS1(src
) | (NTH_BIT(offset
, 6) << 5) | (NTH_BIT(offset
, 2) << 6) | (((offset
>> 3) & 7) << 10));
2302 gen_le16(opcode
| C_ENCODE_RS2(dst
) | C_ENCODE_RS1(src
) | (((offset
>> 6) & 3) << 5) | (((offset
>> 3) & 7) << 10));
2305 expect("known instruction");
2309 /* caller: Add funct4 into opcode */
2310 static void asm_emit_cr(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
)
2312 if (rd
->type
!= OP_REG
) {
2313 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2316 if (rs2
->type
!= OP_REG
) {
2317 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2320 /* CR-type instruction:
2326 gen_le16(opcode
| C_ENCODE_RS1(rd
->reg
) | C_ENCODE_RS2(rs2
->reg
));
2329 /* caller: Add funct3 into opcode */
2330 static void asm_emit_cs(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*rs1
, const Operand
*imm
)
2335 if (rs2
->type
!= OP_REG
) {
2336 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2339 if (rs1
->type
!= OP_REG
) {
2340 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2343 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2344 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2347 base
= rs1
->reg
- 8;
2351 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2355 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2360 if (offset
> 0xff) {
2361 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token
, NULL
));
2365 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token
, NULL
));
2368 /* CS-type instruction:
2379 gen_le16(opcode
| C_ENCODE_RS2(base
) | C_ENCODE_RS1(src
) | (NTH_BIT(offset
, 6) << 5) | (NTH_BIT(offset
, 2) << 6) | (((offset
>> 3) & 7) << 10));
2384 gen_le16(opcode
| C_ENCODE_RS2(base
) | C_ENCODE_RS1(src
) | (((offset
>> 6) & 3) << 5) | (((offset
>> 3) & 7) << 10));
2387 expect("known instruction");
2391 /* caller: Add funct3 into opcode */
2392 static void asm_emit_css(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*imm
)
2396 if (rs2
->type
!= OP_REG
) {
2397 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2400 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2401 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2406 if (offset
> 0xff) {
2407 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token
, NULL
));
2411 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token
, NULL
));
2414 /* CSS-type instruction:
2422 case TOK_ASM_c_fswsp
:
2423 case TOK_ASM_c_swsp
:
2424 gen_le16(opcode
| ENCODE_RS2(rs2
->reg
) | (((offset
>> 6) & 3) << 7) | (((offset
>> 2) & 0xf) << 9));
2427 case TOK_ASM_c_fsdsp
:
2428 case TOK_ASM_c_sdsp
:
2429 gen_le16(opcode
| ENCODE_RS2(rs2
->reg
) | (((offset
>> 6) & 7) << 7) | (((offset
>> 3) & 7) << 10));
2432 expect("known instruction");
2436 /*************************************************************/
2437 #endif /* ndef TARGET_DEFS_ONLY */