1 #ifdef TARGET_DEFS_ONLY
3 // Number of registers available to allocator:
4 #define NB_REGS 19 // x10-x17 aka a0-a7, f10-f17 aka fa0-fa7, xxx, ra, sp
7 #define TREG_R(x) (x) // x = 0..7
8 #define TREG_F(x) (x + 8) // x = 0..7
10 // Register classes sorted from more general to more precise:
11 #define RC_INT (1 << 0)
12 #define RC_FLOAT (1 << 1)
13 #define RC_R(x) (1 << (2 + (x))) // x = 0..7
14 #define RC_F(x) (1 << (10 + (x))) // x = 0..7
16 #define RC_IRET (RC_R(0)) // int return register class
17 #define RC_IRE2 (RC_R(1)) // int 2nd return register class
18 #define RC_FRET (RC_F(0)) // float return register class
20 #define REG_IRET (TREG_R(0)) // int return register number
21 #define REG_IRE2 (TREG_R(1)) // int 2nd return register number
22 #define REG_FRET (TREG_F(0)) // float return register number
26 #define LDOUBLE_SIZE 16
27 #define LDOUBLE_ALIGN 16
31 #define CHAR_IS_UNSIGNED
38 ST_DATA
const char * const target_machine_defs
=
46 "__riscv_float_abi_double\0"
54 ST_DATA
const int reg_classes
[NB_REGS
] = {
76 #if defined(CONFIG_TCC_BCHECK)
77 static addr_t func_bound_offset
;
78 static unsigned long func_bound_ind
;
79 ST_DATA
int func_bound_add_epilog
;
82 static int ireg(int r
)
88 assert(r
>= 0 && r
< 8);
89 return r
+ 10; // tccrX --> aX == x(10+X)
92 static int is_ireg(int r
)
94 return (unsigned)r
< 8 || r
== TREG_RA
|| r
== TREG_SP
;
97 static int freg(int r
)
99 assert(r
>= 8 && r
< 16);
100 return r
- 8 + 10; // tccfX --> faX == f(10+X)
103 static int is_freg(int r
)
105 return r
>= 8 && r
< 16;
108 ST_FUNC
void o(unsigned int c
)
113 if (ind1
> cur_text_section
->data_allocated
)
114 section_realloc(cur_text_section
, ind1
);
115 write32le(cur_text_section
->data
+ ind
, c
);
119 static void EIu(uint32_t opcode
, uint32_t func3
,
120 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
122 o(opcode
| (func3
<< 12) | (rd
<< 7) | (rs1
<< 15) | (imm
<< 20));
125 static void ER(uint32_t opcode
, uint32_t func3
,
126 uint32_t rd
, uint32_t rs1
, uint32_t rs2
, uint32_t func7
)
128 o(opcode
| func3
<< 12 | rd
<< 7 | rs1
<< 15 | rs2
<< 20 | func7
<< 25);
131 static void EI(uint32_t opcode
, uint32_t func3
,
132 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
134 assert(! ((imm
+ (1 << 11)) >> 12));
135 EIu(opcode
, func3
, rd
, rs1
, imm
);
138 static void ES(uint32_t opcode
, uint32_t func3
,
139 uint32_t rs1
, uint32_t rs2
, uint32_t imm
)
141 assert(! ((imm
+ (1 << 11)) >> 12));
142 o(opcode
| (func3
<< 12) | ((imm
& 0x1f) << 7) | (rs1
<< 15)
143 | (rs2
<< 20) | ((imm
>> 5) << 25));
146 // Patch all branches in list pointed to by t to branch to a:
147 ST_FUNC
void gsym_addr(int t_
, int a_
)
152 unsigned char *ptr
= cur_text_section
->data
+ t
;
153 uint32_t next
= read32le(ptr
);
154 uint32_t r
= a
- t
, imm
;
155 if ((r
+ (1 << 21)) & ~((1U << 22) - 2))
156 tcc_error("out-of-range branch chain");
157 imm
= (((r
>> 12) & 0xff) << 12)
158 | (((r
>> 11) & 1) << 20)
159 | (((r
>> 1) & 0x3ff) << 21)
160 | (((r
>> 20) & 1) << 31);
161 write32le(ptr
, r
== 4 ? 0x33 : 0x6f | imm
); // nop || j imm
166 static int load_symofs(int r
, SValue
*sv
, int forstore
)
168 int rr
, doload
= 0, large_addend
= 0;
169 int fc
= sv
->c
.i
, v
= sv
->r
& VT_VALMASK
;
170 if (sv
->r
& VT_SYM
) {
172 assert(v
== VT_CONST
);
173 if (sv
->sym
->type
.t
& VT_STATIC
) { // XXX do this per linker relax
174 greloca(cur_text_section
, sv
->sym
, ind
,
175 R_RISCV_PCREL_HI20
, sv
->c
.i
);
178 if (((unsigned)fc
+ (1 << 11)) >> 12){
181 greloca(cur_text_section
, sv
->sym
, ind
,
182 R_RISCV_GOT_HI20
, 0);
185 label
.type
.t
= VT_VOID
| VT_STATIC
;
187 put_extern_sym(&label
, cur_text_section
, ind
, 0);
188 rr
= is_ireg(r
) ? ireg(r
) : 5;
189 o(0x17 | (rr
<< 7)); // auipc RR, 0 %pcrel_hi(sym)+addend
190 greloca(cur_text_section
, &label
, ind
,
192 ? R_RISCV_PCREL_LO12_I
: R_RISCV_PCREL_LO12_S
, 0);
194 EI(0x03, 3, rr
, rr
, 0); // ld RR, 0(RR)
196 o(0x37 | (6 << 7) | ((0x800 + fc
) & 0xfffff000)); //lui t1, high(fc)
197 ER(0x33, 0, rr
, rr
, 6, 0); // add RR, RR, t1
198 sv
->c
.i
= fc
<< 20 >> 20;
201 } else if (v
== VT_LOCAL
|| v
== VT_LLOCAL
) {
204 tcc_error("unimp: store(giant local off) (0x%lx)", (long)sv
->c
.i
);
205 if (((unsigned)fc
+ (1 << 11)) >> 12) {
206 rr
= is_ireg(r
) ? ireg(r
) : 5; // t0
207 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui RR, upper(fc)
208 ER(0x33, 0, rr
, rr
, 8, 0); // add RR, RR, s0
209 sv
->c
.i
= fc
<< 20 >> 20;
216 static void load_large_constant(int rr
, int fc
, uint32_t pi
)
220 o(0x37 | (rr
<< 7) | (((pi
+ 0x800) & 0xfffff000))); // lui RR, up(up(fc))
221 EI(0x13, 0, rr
, rr
, (int)pi
<< 20 >> 20); // addi RR, RR, lo(up(fc))
222 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
223 EI(0x13, 0, rr
, rr
, (fc
+ (1 << 19)) >> 20); // addi RR, RR, up(lo(fc))
224 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
226 EI(0x13, 0, rr
, rr
, fc
>> 8); // addi RR, RR, lo1(lo(fc))
227 EI(0x13, 1, rr
, rr
, 8); // slli RR, RR, 8
230 ST_FUNC
void load(int r
, SValue
*sv
)
233 int v
= fr
& VT_VALMASK
;
234 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
);
236 int bt
= sv
->type
.t
& VT_BTYPE
;
239 int func3
, opcode
= is_freg(r
) ? 0x07 : 0x03, br
;
240 size
= type_size(&sv
->type
, &align
);
241 assert (!is_freg(r
) || bt
== VT_FLOAT
|| bt
== VT_DOUBLE
);
242 if (bt
== VT_PTR
|| bt
== VT_FUNC
) /* XXX should be done in generic code */
244 func3
= size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3;
245 if (size
< 4 && !is_float(sv
->type
.t
) && (sv
->type
.t
& VT_UNSIGNED
))
247 if (v
== VT_LOCAL
|| (fr
& VT_SYM
)) {
248 br
= load_symofs(r
, sv
, 0);
250 } else if (v
< VT_CONST
) {
252 /*if (((unsigned)fc + (1 << 11)) >> 12)
253 tcc_error("unimp: load(large addend) (0x%x)", fc);*/
254 fc
= 0; // XXX store ofs in LVAL(reg)
255 } else if (v
== VT_LLOCAL
) {
256 br
= load_symofs(r
, sv
, 0);
258 EI(0x03, 3, rr
, br
, fc
); // ld RR, fc(BR)
261 } else if (v
== VT_CONST
) {
262 int64_t si
= sv
->c
.i
;
265 load_large_constant(rr
, fc
, si
);
268 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui RR, upper(fc)
273 tcc_error("unimp: load(non-local lval)");
275 EI(opcode
, func3
, rr
, br
, fc
); // l[bhwd][u] / fl[wd] RR, fc(BR)
276 } else if (v
== VT_CONST
) {
277 int rb
= 0, do32bit
= 8, zext
= 0;
278 assert((!is_float(sv
->type
.t
) && is_ireg(r
)) || bt
== VT_LDOUBLE
);
280 rb
= load_symofs(r
, sv
, 0);
284 if (is_float(sv
->type
.t
) && bt
!= VT_LDOUBLE
)
285 tcc_error("unimp: load(float)");
287 int64_t si
= sv
->c
.i
;
290 load_large_constant(rr
, fc
, si
);
294 } else if (bt
== VT_LLONG
) {
295 /* A 32bit unsigned constant for a 64bit type.
296 lui always sign extends, so we need to do an explicit zext.*/
300 if (((unsigned)fc
+ (1 << 11)) >> 12)
301 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)), rb
= rr
; //lui RR, upper(fc)
302 if (fc
|| (rr
!= rb
) || do32bit
|| (fr
& VT_SYM
))
303 EI(0x13 | do32bit
, 0, rr
, rb
, fc
<< 20 >> 20); // addi[w] R, x0|R, FC
305 EI(0x13, 1, rr
, rr
, 32); // slli RR, RR, 32
306 EI(0x13, 5, rr
, rr
, 32); // srli RR, RR, 32
308 } else if (v
== VT_LOCAL
) {
309 int br
= load_symofs(r
, sv
, 0);
312 EI(0x13, 0, rr
, br
, fc
); // addi R, s0, FC
313 } else if (v
< VT_CONST
) { /* reg-reg */
314 //assert(!fc); XXX support offseted regs
315 if (is_freg(r
) && is_freg(v
))
316 ER(0x53, 0, rr
, freg(v
), freg(v
), bt
== VT_DOUBLE
? 0x11 : 0x10); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
317 else if (is_ireg(r
) && is_ireg(v
))
318 EI(0x13, 0, rr
, ireg(v
), 0); // addi RR, V, 0 == mv RR, V
320 int func7
= is_ireg(r
) ? 0x70 : 0x78;
321 size
= type_size(&sv
->type
, &align
);
324 assert(size
== 4 || size
== 8);
325 o(0x53 | (rr
<< 7) | ((is_freg(v
) ? freg(v
) : ireg(v
)) << 15)
326 | (func7
<< 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
328 } else if (v
== VT_CMP
) {
329 int op
= vtop
->cmp_op
;
330 int a
= vtop
->cmp_r
& 0xff;
331 int b
= (vtop
->cmp_r
>> 8) & 0xff;
342 if (op
& 1) { // remove [U]GE,GT
346 if ((op
& 7) == 6) { // [U]LE
347 int t
= a
; a
= b
; b
= t
;
350 ER(0x33, (op
> TOK_UGT
) ? 2 : 3, rr
, a
, b
, 0); // slt[u] d, a, b
352 EI(0x13, 4, rr
, rr
, 1); // xori d, d, 1
357 ER(0x33, 0, rr
, a
, b
, 0x20); // sub d, a, b
359 ER(0x33, 3, rr
, 0, rr
, 0); // sltu d, x0, d == snez d,d
361 EI(0x13, 3, rr
, rr
, 1); // sltiu d, d, 1 == seqz d,d
364 } else if ((v
& ~1) == VT_JMP
) {
367 EI(0x13, 0, rr
, 0, t
); // addi RR, x0, t
370 EI(0x13, 0, rr
, 0, t
^ 1); // addi RR, x0, !t
372 tcc_error("unimp: load(non-const)");
375 ST_FUNC
void store(int r
, SValue
*sv
)
377 int fr
= sv
->r
& VT_VALMASK
;
378 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
), ptrreg
;
380 int bt
= sv
->type
.t
& VT_BTYPE
;
381 int align
, size
= type_size(&sv
->type
, &align
);
382 assert(!is_float(bt
) || is_freg(r
) || bt
== VT_LDOUBLE
);
383 /* long doubles are in two integer registers, but the load/store
384 primitives only deal with one, so do as if it's one reg. */
385 if (bt
== VT_LDOUBLE
)
388 tcc_error("unimp: store(struct)");
390 tcc_error("unimp: large sized store");
391 assert(sv
->r
& VT_LVAL
);
392 if (fr
== VT_LOCAL
|| (sv
->r
& VT_SYM
)) {
393 ptrreg
= load_symofs(-1, sv
, 1);
395 } else if (fr
< VT_CONST
) {
397 /*if (((unsigned)fc + (1 << 11)) >> 12)
398 tcc_error("unimp: store(large addend) (0x%x)", fc);*/
399 fc
= 0; // XXX support offsets regs
400 } else if (fr
== VT_CONST
) {
401 int64_t si
= sv
->c
.i
;
405 load_large_constant(ptrreg
, fc
, si
);
408 o(0x37 | (ptrreg
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui RR, upper(fc)
412 tcc_error("implement me: %s(!local)", __FUNCTION__
);
413 ES(is_freg(r
) ? 0x27 : 0x23, // fs... | s...
414 size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3, // ... [wd] | [bhwd]
415 ptrreg
, rr
, fc
); // RR, fc(base)
418 static void gcall_or_jmp(int docall
)
420 int tr
= docall
? 1 : 5; // ra or t0
421 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
&&
422 ((vtop
->r
& VT_SYM
) && vtop
->c
.i
== (int)vtop
->c
.i
)) {
423 /* constant symbolic case -> simple relocation */
424 greloca(cur_text_section
, vtop
->sym
, ind
,
425 R_RISCV_CALL_PLT
, (int)vtop
->c
.i
);
426 o(0x17 | (tr
<< 7)); // auipc TR, 0 %call(func)
427 EI(0x67, 0, tr
, tr
, 0);// jalr TR, r(TR)
428 } else if (vtop
->r
< VT_CONST
) {
429 int r
= ireg(vtop
->r
);
430 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
435 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
439 #if defined(CONFIG_TCC_BCHECK)
441 static void gen_bounds_call(int v
)
443 Sym
*sym
= external_helper_sym(v
);
445 greloca(cur_text_section
, sym
, ind
, R_RISCV_CALL_PLT
, 0);
446 o(0x17 | (1 << 7)); // auipc TR, 0 %call(func)
447 EI(0x67, 0, 1, 1, 0); // jalr TR, r(TR)
450 static void gen_bounds_prolog(void)
452 /* leave some room for bound checking code */
453 func_bound_offset
= lbounds_section
->data_offset
;
454 func_bound_ind
= ind
;
455 func_bound_add_epilog
= 0;
456 o(0x00000013); /* ld a0,#lbound section pointer */
458 o(0x00000013); /* nop -> call __bound_local_new */
462 static void gen_bounds_epilog(void)
469 int offset_modified
= func_bound_offset
!= lbounds_section
->data_offset
;
471 if (!offset_modified
&& !func_bound_add_epilog
)
474 /* add end of table info */
475 bounds_ptr
= section_ptr_add(lbounds_section
, sizeof(addr_t
));
478 sym_data
= get_sym_ref(&char_pointer_type
, lbounds_section
,
479 func_bound_offset
, PTR_SIZE
);
481 label
.type
.t
= VT_VOID
| VT_STATIC
;
482 /* generate bound local allocation */
483 if (offset_modified
) {
485 ind
= func_bound_ind
;
486 put_extern_sym(&label
, cur_text_section
, ind
, 0);
487 greloca(cur_text_section
, sym_data
, ind
, R_RISCV_GOT_HI20
, 0);
488 o(0x17 | (10 << 7)); // auipc a0, 0 %pcrel_hi(sym)+addend
489 greloca(cur_text_section
, &label
, ind
, R_RISCV_PCREL_LO12_I
, 0);
490 EI(0x03, 3, 10, 10, 0); // ld a0, 0(a0)
491 gen_bounds_call(TOK___bound_local_new
);
493 label
.c
= 0; /* force new local ELF symbol */
496 /* generate bound check local freeing */
497 o(0xe02a1101); /* addi sp,sp,-32 sd a0,0(sp) */
498 o(0xa82ae42e); /* sd a1,8(sp) fsd fa0,16(sp) */
499 put_extern_sym(&label
, cur_text_section
, ind
, 0);
500 greloca(cur_text_section
, sym_data
, ind
, R_RISCV_GOT_HI20
, 0);
501 o(0x17 | (10 << 7)); // auipc a0, 0 %pcrel_hi(sym)+addend
502 greloca(cur_text_section
, &label
, ind
, R_RISCV_PCREL_LO12_I
, 0);
503 EI(0x03, 3, 10, 10, 0); // ld a0, 0(a0)
504 gen_bounds_call(TOK___bound_local_delete
);
505 o(0x65a26502); /* ld a0,0(sp) ld a1,8(sp) */
506 o(0x61052542); /* fld fa0,16(sp) addi sp,sp,32 */
510 static void reg_pass_rec(CType
*type
, int *rc
, int *fieldofs
, int ofs
)
512 if ((type
->t
& VT_BTYPE
) == VT_STRUCT
) {
514 if (type
->ref
->type
.t
== VT_UNION
)
516 else for (f
= type
->ref
->next
; f
; f
= f
->next
)
517 reg_pass_rec(&f
->type
, rc
, fieldofs
, ofs
+ f
->c
);
518 } else if (type
->t
& VT_ARRAY
) {
519 if (type
->ref
->c
< 0 || type
->ref
->c
> 2)
522 int a
, sz
= type_size(&type
->ref
->type
, &a
);
523 reg_pass_rec(&type
->ref
->type
, rc
, fieldofs
, ofs
);
524 if (rc
[0] > 2 || (rc
[0] == 2 && type
->ref
->c
> 1))
526 else if (type
->ref
->c
== 2 && rc
[0] && rc
[1] == RC_FLOAT
) {
527 rc
[++rc
[0]] = RC_FLOAT
;
528 fieldofs
[rc
[0]] = ((ofs
+ sz
) << 4)
529 | (type
->ref
->type
.t
& VT_BTYPE
);
530 } else if (type
->ref
->c
== 2)
533 } else if (rc
[0] == 2 || rc
[0] < 0 || (type
->t
& VT_BTYPE
) == VT_LDOUBLE
)
535 else if (!rc
[0] || rc
[1] == RC_FLOAT
|| is_float(type
->t
)) {
536 rc
[++rc
[0]] = is_float(type
->t
) ? RC_FLOAT
: RC_INT
;
537 fieldofs
[rc
[0]] = (ofs
<< 4) | ((type
->t
& VT_BTYPE
) == VT_PTR
? VT_LLONG
: type
->t
& VT_BTYPE
);
542 static void reg_pass(CType
*type
, int *prc
, int *fieldofs
, int named
)
545 reg_pass_rec(type
, prc
, fieldofs
, 0);
546 if (prc
[0] <= 0 || !named
) {
547 int align
, size
= type_size(type
, &align
);
548 prc
[0] = (size
+ 7) >> 3;
549 prc
[1] = prc
[2] = RC_INT
;
550 fieldofs
[1] = (0 << 4) | (size
<= 1 ? VT_BYTE
: size
<= 2 ? VT_SHORT
: size
<= 4 ? VT_INT
: VT_LLONG
);
551 fieldofs
[2] = (8 << 4) | (size
<= 9 ? VT_BYTE
: size
<= 10 ? VT_SHORT
: size
<= 12 ? VT_INT
: VT_LLONG
);
555 ST_FUNC
void gfunc_call(int nb_args
)
557 int i
, align
, size
, areg
[2];
558 int *info
= tcc_malloc((nb_args
+ 1) * sizeof (int));
559 int stack_adj
= 0, tempspace
= 0, stack_add
, ofs
, splitofs
= 0;
563 #ifdef CONFIG_TCC_BCHECK
564 int bc_save
= tcc_state
->do_bounds_check
;
565 if (tcc_state
->do_bounds_check
)
566 gbound_args(nb_args
);
569 areg
[0] = 0; /* int arg regs */
570 areg
[1] = 8; /* float arg regs */
571 sa
= vtop
[-nb_args
].type
.ref
->next
;
572 for (i
= 0; i
< nb_args
; i
++) {
573 int nregs
, byref
= 0, tempofs
;
574 int prc
[3], fieldofs
[3];
575 sv
= &vtop
[1 + i
- nb_args
];
576 sv
->type
.t
&= ~VT_ARRAY
; // XXX this should be done in tccgen.c
577 size
= type_size(&sv
->type
, &align
);
581 tempspace
= (tempspace
+ align
- 1) & -align
;
585 byref
= 64 | (tempofs
<< 7);
587 reg_pass(&sv
->type
, prc
, fieldofs
, sa
!= 0);
588 if (!sa
&& align
== 2*XLEN
&& size
<= 2*XLEN
)
589 areg
[0] = (areg
[0] + 1) & ~1;
593 else if ((prc
[1] == RC_INT
&& areg
[0] >= 8)
594 || (prc
[1] == RC_FLOAT
&& areg
[1] >= 16)
595 || (nregs
== 2 && prc
[1] == RC_FLOAT
&& prc
[2] == RC_FLOAT
597 || (nregs
== 2 && prc
[1] != prc
[2]
598 && (areg
[1] >= 16 || areg
[0] >= 8))) {
602 stack_adj
+= (size
+ align
- 1) & -align
;
603 if (!sa
) /* one vararg on stack forces the rest on stack */
604 areg
[0] = 8, areg
[1] = 16;
606 info
[i
] = areg
[prc
[1] - 1]++;
608 info
[i
] |= (fieldofs
[1] & VT_BTYPE
) << 12;
609 assert(!(fieldofs
[1] >> 4));
611 if (prc
[2] == RC_FLOAT
|| areg
[0] < 8)
612 info
[i
] |= (1 + areg
[prc
[2] - 1]++) << 7;
618 assert((fieldofs
[2] >> 4) < 2048);
619 info
[i
] |= fieldofs
[2] << (12 + 4); // includes offset
627 stack_adj
= (stack_adj
+ 15) & -16;
628 tempspace
= (tempspace
+ 15) & -16;
629 stack_add
= stack_adj
+ tempspace
;
631 /* fetch cpu flag before generating any code */
632 if ((vtop
->r
& VT_VALMASK
) == VT_CMP
)
637 if (stack_add
>= 0x800) {
638 unsigned int bit11
= (((unsigned int)-stack_add
) >> 11) & 1;
640 ((-stack_add
+ (bit11
<< 12)) & 0xfffff000)); //lui t0, upper(v)
641 EI(0x13, 0, 5, 5, ((-stack_add
& 0xfff) - bit11
* (1 << 12)));
642 // addi t0, t0, lo(v)
643 ER(0x33, 0, 2, 2, 5, 0); // add sp, sp, t0
646 EI(0x13, 0, 2, 2, -stack_add
); // addi sp, sp, -adj
647 for (i
= ofs
= 0; i
< nb_args
; i
++) {
648 if (info
[i
] & (64 | 32)) {
650 size
= type_size(&vtop
->type
, &align
);
652 vset(&char_pointer_type
, TREG_SP
, 0);
653 vpushi(stack_adj
+ (info
[i
] >> 7));
655 vpushv(vtop
); // this replaces the old argument
658 vtop
->type
= vtop
[-1].type
;
667 /* Once we support offseted regs we can do this:
668 vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
669 to construct the lvalue for the outgoing stack slot,
670 until then we have to jump through hoops. */
671 vset(&char_pointer_type
, TREG_SP
, 0);
672 ofs
= (ofs
+ align
- 1) & -align
;
676 vtop
->type
= vtop
[-1].type
;
679 vtop
->r
= vtop
->r2
= VT_CONST
; // this arg is done
683 } else if (info
[i
] & 16) {
690 for (i
= 0; i
< nb_args
; i
++) {
691 int ii
= info
[nb_args
- 1 - i
], r
= ii
, r2
= r
;
696 r2
= r2
& 64 ? 0 : (r2
>> 7) & 31;
699 origtype
= vtop
->type
;
700 size
= type_size(&vtop
->type
, &align
);
703 loadt
= vtop
->type
.t
& VT_BTYPE
;
704 if (loadt
== VT_STRUCT
) {
705 loadt
= (ii
>> 12) & VT_BTYPE
;
707 if (info
[nb_args
- 1 - i
] & 16) {
711 if (loadt
== VT_LDOUBLE
) {
718 vtop
->type
.t
= loadt
| (vtop
->type
.t
& VT_UNSIGNED
);
719 gv(r
< 8 ? RC_R(r
) : RC_F(r
- 8));
720 vtop
->type
= origtype
;
722 if (r2
&& loadt
!= VT_LDOUBLE
) {
724 assert(r2
< 16 || r2
== TREG_RA
);
727 vtop
->type
= char_pointer_type
;
729 #ifdef CONFIG_TCC_BCHECK
730 if ((origtype
.t
& VT_BTYPE
) == VT_STRUCT
)
731 tcc_state
->do_bounds_check
= 0;
734 #ifdef CONFIG_TCC_BCHECK
735 tcc_state
->do_bounds_check
= bc_save
;
738 vtop
->type
= origtype
;
739 loadt
= vtop
->type
.t
& VT_BTYPE
;
740 if (loadt
== VT_STRUCT
) {
741 loadt
= (ii
>> 16) & VT_BTYPE
;
743 save_reg_upstack(r2
, 1);
744 vtop
->type
.t
= loadt
| (vtop
->type
.t
& VT_UNSIGNED
);
746 assert(r2
< VT_CONST
);
750 if (info
[nb_args
- 1 - i
] & 16) {
751 ES(0x23, 3, 2, ireg(vtop
->r2
), splitofs
); // sd t0, ofs(sp)
753 } else if (loadt
== VT_LDOUBLE
&& vtop
->r2
!= r2
) {
754 assert(vtop
->r2
<= 7 && r2
<= 7);
755 /* XXX we'd like to have 'gv' move directly into
756 the right class instead of us fixing it up. */
757 EI(0x13, 0, ireg(r2
), ireg(vtop
->r2
), 0); // mv Ra+1, RR2
765 save_regs(nb_args
+ 1);
769 if (stack_add
>= 0x800) {
770 unsigned int bit11
= ((unsigned int)stack_add
>> 11) & 1;
772 ((stack_add
+ (bit11
<< 12)) & 0xfffff000)); //lui t0, upper(v)
773 EI(0x13, 0, 5, 5, (stack_add
& 0xfff) - bit11
* (1 << 12));
774 // addi t0, t0, lo(v)
775 ER(0x33, 0, 2, 2, 5, 0); // add sp, sp, t0
778 EI(0x13, 0, 2, 2, stack_add
); // addi sp, sp, adj
783 static int func_sub_sp_offset
, num_va_regs
, func_va_list_ofs
;
785 ST_FUNC
void gfunc_prolog(Sym
*func_sym
)
787 CType
*func_type
= &func_sym
->type
;
788 int i
, addr
, align
, size
;
794 sym
= func_type
->ref
;
795 loc
= -16; // for ra and s0
796 func_sub_sp_offset
= ind
;
799 areg
[0] = 0, areg
[1] = 0;
801 /* if the function returns by reference, then add an
802 implicit pointer parameter */
803 size
= type_size(&func_vt
, &align
);
804 if (size
> 2 * XLEN
) {
807 ES(0x23, 3, 8, 10 + areg
[0]++, loc
); // sd a0, loc(s0)
809 /* define parameters */
810 while ((sym
= sym
->next
) != NULL
) {
813 int prc
[3], fieldofs
[3];
815 size
= type_size(type
, &align
);
816 if (size
> 2 * XLEN
) {
817 type
= &char_pointer_type
;
818 size
= align
= byref
= 8;
820 reg_pass(type
, prc
, fieldofs
, 1);
822 if (areg
[prc
[1] - 1] >= 8
824 && ((prc
[1] == RC_FLOAT
&& prc
[2] == RC_FLOAT
&& areg
[1] >= 7)
825 || (prc
[1] != prc
[2] && (areg
[1] >= 8 || areg
[0] >= 8))))) {
828 addr
= (addr
+ align
- 1) & -align
;
832 loc
-= regcount
* 8; // XXX could reserve only 'size' bytes
834 for (i
= 0; i
< regcount
; i
++) {
835 if (areg
[prc
[1+i
] - 1] >= 8) {
836 assert(i
== 1 && regcount
== 2 && !(addr
& 7));
837 EI(0x03, 3, 5, 8, addr
); // ld t0, addr(s0)
839 ES(0x23, 3, 8, 5, loc
+ i
*8); // sd t0, loc(s0)
840 } else if (prc
[1+i
] == RC_FLOAT
) {
841 ES(0x27, (size
/ regcount
) == 4 ? 2 : 3, 8, 10 + areg
[1]++, loc
+ (fieldofs
[i
+1] >> 4)); // fs[wd] FAi, loc(s0)
843 ES(0x23, 3, 8, 10 + areg
[0]++, loc
+ i
*8); // sd aX, loc(s0) // XXX
847 sym_push(sym
->v
& ~SYM_FIELD
, &sym
->type
,
848 (byref
? VT_LLOCAL
: VT_LOCAL
) | VT_LVAL
,
851 func_va_list_ofs
= addr
;
854 for (; areg
[0] < 8; areg
[0]++) {
856 ES(0x23, 3, 8, 10 + areg
[0], -8 + num_va_regs
* 8); // sd aX, loc(s0)
859 #ifdef CONFIG_TCC_BCHECK
860 if (tcc_state
->do_bounds_check
)
865 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
,
866 int *ret_align
, int *regsize
)
868 int align
, size
= type_size(vt
, &align
), nregs
;
869 int prc
[3], fieldofs
[3];
874 reg_pass(vt
, prc
, fieldofs
, 1);
876 if (nregs
== 2 && prc
[1] != prc
[2])
877 return -1; /* generic code can't deal with this case */
878 if (prc
[1] == RC_FLOAT
) {
879 *regsize
= size
/ nregs
;
881 ret
->t
= fieldofs
[1] & VT_BTYPE
;
886 ST_FUNC
void arch_transfer_ret_regs(int aftercall
)
888 int prc
[3], fieldofs
[3];
889 reg_pass(&vtop
->type
, prc
, fieldofs
, 1);
890 assert(prc
[0] == 2 && prc
[1] != prc
[2] && !(fieldofs
[1] >> 4));
891 assert(vtop
->r
== (VT_LOCAL
| VT_LVAL
));
893 vtop
->type
.t
= fieldofs
[1] & VT_BTYPE
;
894 (aftercall
? store
: load
)(prc
[1] == RC_INT
? REG_IRET
: REG_FRET
, vtop
);
895 vtop
->c
.i
+= fieldofs
[2] >> 4;
896 vtop
->type
.t
= fieldofs
[2] & VT_BTYPE
;
897 (aftercall
? store
: load
)(prc
[2] == RC_INT
? REG_IRET
: REG_FRET
, vtop
);
901 ST_FUNC
void gfunc_epilog(void)
903 int v
, saved_ind
, d
, large_ofs_ind
;
905 #ifdef CONFIG_TCC_BCHECK
906 if (tcc_state
->do_bounds_check
)
910 loc
= (loc
- num_va_regs
* 8);
911 d
= v
= (-loc
+ 15) & -16;
913 if (v
>= (1 << 11)) {
915 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
916 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
917 ER(0x33, 0, 2, 2, 5, 0); // add sp, sp, t0
919 EI(0x03, 3, 1, 2, d
- 8 - num_va_regs
* 8); // ld ra, v-8(sp)
920 EI(0x03, 3, 8, 2, d
- 16 - num_va_regs
* 8); // ld s0, v-16(sp)
921 EI(0x13, 0, 2, 2, d
); // addi sp, sp, v
922 EI(0x67, 0, 0, 1, 0); // jalr x0, 0(x1), aka ret
924 if (v
>= (1 << 11)) {
925 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
926 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
927 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
928 ER(0x33, 0, 2, 2, 5, 0x20); // sub sp, sp, t0
929 gjmp_addr(func_sub_sp_offset
+ 5*4);
933 ind
= func_sub_sp_offset
;
934 EI(0x13, 0, 2, 2, -d
); // addi sp, sp, -d
935 ES(0x23, 3, 2, 1, d
- 8 - num_va_regs
* 8); // sd ra, d-8(sp)
936 ES(0x23, 3, 2, 8, d
- 16 - num_va_regs
* 8); // sd s0, d-16(sp)
938 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
940 gjmp_addr(large_ofs_ind
);
941 if ((ind
- func_sub_sp_offset
) != 5*4)
942 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
946 ST_FUNC
void gen_va_start(void)
949 vset(&char_pointer_type
, VT_LOCAL
, func_va_list_ofs
);
952 ST_FUNC
void gen_fill_nops(int bytes
)
955 tcc_error("alignment of code section not multiple of 4");
957 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
962 // Generate forward branch to label:
963 ST_FUNC
int gjmp(int t
)
971 // Generate branch to known address:
972 ST_FUNC
void gjmp_addr(int a
)
974 uint32_t r
= a
- ind
, imm
;
975 if ((r
+ (1 << 21)) & ~((1U << 22) - 2)) {
976 o(0x17 | (5 << 7) | (((r
+ 0x800) & 0xfffff000))); // lui RR, up(r)
977 r
= (int)r
<< 20 >> 20;
978 EI(0x67, 0, 0, 5, r
); // jalr x0, r(t0)
980 imm
= (((r
>> 12) & 0xff) << 12)
981 | (((r
>> 11) & 1) << 20)
982 | (((r
>> 1) & 0x3ff) << 21)
983 | (((r
>> 20) & 1) << 31);
984 o(0x6f | imm
); // jal x0, imm == j imm
988 ST_FUNC
int gjmp_cond(int op
, int t
)
991 int a
= vtop
->cmp_r
& 0xff;
992 int b
= (vtop
->cmp_r
>> 8) & 0xff;
994 case TOK_ULT
: op
= 6; break;
995 case TOK_UGE
: op
= 7; break;
996 case TOK_ULE
: op
= 7; tmp
= a
; a
= b
; b
= tmp
; break;
997 case TOK_UGT
: op
= 6; tmp
= a
; a
= b
; b
= tmp
; break;
998 case TOK_LT
: op
= 4; break;
999 case TOK_GE
: op
= 5; break;
1000 case TOK_LE
: op
= 5; tmp
= a
; a
= b
; b
= tmp
; break;
1001 case TOK_GT
: op
= 4; tmp
= a
; a
= b
; b
= tmp
; break;
1002 case TOK_NE
: op
= 1; break;
1003 case TOK_EQ
: op
= 0; break;
1005 o(0x63 | (op
^ 1) << 12 | a
<< 15 | b
<< 20 | 8 << 7); // bOP a,b,+4
1009 ST_FUNC
int gjmp_append(int n
, int t
)
1012 /* insert jump list n into t */
1014 uint32_t n1
= n
, n2
;
1015 while ((n2
= read32le(p
= cur_text_section
->data
+ n1
)))
1023 static void gen_opil(int op
, int ll
)
1028 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
) {
1030 if (fc
== vtop
->c
.i
&& !(((unsigned)fc
+ (1 << 11)) >> 12)) {
1032 int m
= ll
? 31 : 63;
1035 a
= ireg(vtop
[0].r
);
1037 d
= get_reg(RC_INT
);
1042 if (fc
<= -(1 << 11))
1046 func3
= 0; // addi d, a, fc
1049 EI(0x13 | cll
, func3
, ireg(d
), a
, fc
);
1051 if (op
>= TOK_ULT
&& op
<= TOK_GT
) {
1052 vset_VT_CMP(TOK_NE
);
1053 vtop
->cmp_r
= ireg(d
) | 0 << 8;
1058 if (fc
>= (1 << 11) - 1)
1061 case TOK_LT
: func3
= 2; goto do_cop
; // slti d, a, fc
1063 if (fc
>= (1 << 11) - 1 || fc
== -1)
1066 case TOK_ULT
: func3
= 3; goto do_cop
; // sltiu d, a, fc
1067 case '^': func3
= 4; goto do_cop
; // xori d, a, fc
1068 case '|': func3
= 6; goto do_cop
; // ori d, a, fc
1069 case '&': func3
= 7; goto do_cop
; // andi d, a, fc
1070 case TOK_SHL
: func3
= 1; cll
= ll
; fc
&= m
; goto do_cop
; // slli d, a, fc
1071 case TOK_SHR
: func3
= 5; cll
= ll
; fc
&= m
; goto do_cop
; // srli d, a, fc
1072 case TOK_SAR
: func3
= 5; cll
= ll
; fc
= 1024 | (fc
& m
); goto do_cop
;
1074 case TOK_UGE
: /* -> TOK_ULT */
1075 case TOK_UGT
: /* -> TOK_ULE */
1076 case TOK_GE
: /* -> TOK_LT */
1077 case TOK_GT
: /* -> TOK_LE */
1078 gen_opil(op
- 1, !ll
);
1085 gen_opil('-', !ll
), a
= ireg(vtop
++->r
);
1088 vtop
->cmp_r
= a
| 0 << 8;
1093 gv2(RC_INT
, RC_INT
);
1094 a
= ireg(vtop
[-1].r
);
1095 b
= ireg(vtop
[0].r
);
1097 d
= get_reg(RC_INT
);
1103 if (op
>= TOK_ULT
&& op
<= TOK_GT
) {
1105 vtop
->cmp_r
= a
| b
<< 8;
1108 tcc_error("implement me: %s(%s)", __FUNCTION__
, get_tok_str(op
, NULL
));
1112 ER(0x33 | ll
, 0, d
, a
, b
, 0); // add d, a, b
1115 ER(0x33 | ll
, 0, d
, a
, b
, 0x20); // sub d, a, b
1118 ER(0x33 | ll
| ll
, 5, d
, a
, b
, 0x20); // sra d, a, b
1121 ER(0x33 | ll
| ll
, 5, d
, a
, b
, 0); // srl d, a, b
1124 ER(0x33 | ll
, 1, d
, a
, b
, 0); // sll d, a, b
1127 ER(0x33 | ll
, 0, d
, a
, b
, 1); // mul d, a, b
1130 ER(0x33 | ll
, 4, d
, a
, b
, 1); // div d, a, b
1133 ER(0x33, 7, d
, a
, b
, 0); // and d, a, b
1136 ER(0x33, 4, d
, a
, b
, 0); // xor d, a, b
1139 ER(0x33, 6, d
, a
, b
, 0); // or d, a, b
1142 ER(ll
? 0x3b: 0x33, 6, d
, a
, b
, 1); // rem d, a, b
1145 ER(0x33 | ll
, 7, d
, a
, b
, 1); // remu d, a, b
1149 ER(0x33 | ll
, 5, d
, a
, b
, 1); // divu d, a, b
1154 ST_FUNC
void gen_opi(int op
)
1159 ST_FUNC
void gen_opl(int op
)
1164 ST_FUNC
void gen_opf(int op
)
1166 int rs1
, rs2
, rd
, dbl
, invert
;
1167 if (vtop
[0].type
.t
== VT_LDOUBLE
) {
1168 CType type
= vtop
[0].type
;
1172 case '*': func
= TOK___multf3
; break;
1173 case '+': func
= TOK___addtf3
; break;
1174 case '-': func
= TOK___subtf3
; break;
1175 case '/': func
= TOK___divtf3
; break;
1176 case TOK_EQ
: func
= TOK___eqtf2
; cond
= 1; break;
1177 case TOK_NE
: func
= TOK___netf2
; cond
= 0; break;
1178 case TOK_LT
: func
= TOK___lttf2
; cond
= 10; break;
1179 case TOK_GE
: func
= TOK___getf2
; cond
= 11; break;
1180 case TOK_LE
: func
= TOK___letf2
; cond
= 12; break;
1181 case TOK_GT
: func
= TOK___gttf2
; cond
= 13; break;
1182 default: assert(0); break;
1184 vpush_helper_func(func
);
1189 vtop
->r2
= cond
< 0 ? TREG_R(1) : VT_CONST
;
1199 gv2(RC_FLOAT
, RC_FLOAT
);
1200 assert(vtop
->type
.t
== VT_DOUBLE
|| vtop
->type
.t
== VT_FLOAT
);
1201 dbl
= vtop
->type
.t
== VT_DOUBLE
;
1202 rs1
= freg(vtop
[-1].r
);
1203 rs2
= freg(vtop
->r
);
1212 rd
= get_reg(RC_FLOAT
);
1215 ER(0x53, 7, rd
, rs1
, rs2
, dbl
| (op
<< 2)); // fop.[sd] RD, RS1, RS2 (dyn rm)
1229 rd
= get_reg(RC_INT
);
1232 ER(0x53, op
, rd
, rs1
, rs2
, dbl
| 0x50); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
1234 EI(0x13, 4, rd
, rd
, 1); // xori RD, 1
1248 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
1252 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
1257 ST_FUNC
void gen_cvt_sxtw(void)
1259 /* XXX on risc-v the registers are usually sign-extended already.
1260 Let's try to not do anything here. */
1263 ST_FUNC
void gen_cvt_itof(int t
)
1265 int rr
= ireg(gv(RC_INT
)), dr
;
1266 int u
= vtop
->type
.t
& VT_UNSIGNED
;
1267 int l
= (vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
;
1268 if (t
== VT_LDOUBLE
) {
1270 (u
? TOK___floatunditf
: TOK___floatditf
) :
1271 (u
? TOK___floatunsitf
: TOK___floatsitf
);
1272 vpush_helper_func(func
);
1278 vtop
->r2
= TREG_R(1);
1281 dr
= get_reg(RC_FLOAT
);
1285 EIu(0x53, 7, dr
, rr
, ((0x68 | (t
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[sd].[wl][u]
1289 ST_FUNC
void gen_cvt_ftoi(int t
)
1291 int ft
= vtop
->type
.t
& VT_BTYPE
;
1292 int l
= (t
& VT_BTYPE
) == VT_LLONG
;
1293 int u
= t
& VT_UNSIGNED
;
1294 if (ft
== VT_LDOUBLE
) {
1296 (u
? TOK___fixunstfdi
: TOK___fixtfdi
) :
1297 (u
? TOK___fixunstfsi
: TOK___fixtfsi
);
1298 vpush_helper_func(func
);
1305 int rr
= freg(gv(RC_FLOAT
)), dr
;
1307 dr
= get_reg(RC_INT
);
1311 EIu(0x53, 1, dr
, rr
, ((0x60 | (ft
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[wl][u].[sd] rtz
1315 ST_FUNC
void gen_cvt_ftof(int dt
)
1317 int st
= vtop
->type
.t
& VT_BTYPE
, rs
, rd
;
1321 if (dt
== VT_LDOUBLE
|| st
== VT_LDOUBLE
) {
1322 int func
= (dt
== VT_LDOUBLE
) ?
1323 (st
== VT_FLOAT
? TOK___extendsftf2
: TOK___extenddftf2
) :
1324 (dt
== VT_FLOAT
? TOK___trunctfsf2
: TOK___trunctfdf2
);
1325 /* We can't use gfunc_call, as func_old_type works like vararg
1326 functions, and on riscv unnamed float args are passed like
1327 integers. But we really need them in the float argument registers
1328 for extendsftf2/extenddftf2. So, do it explicitely. */
1330 if (dt
== VT_LDOUBLE
)
1334 assert(vtop
->r2
< 7);
1335 if (vtop
->r2
!= 1 + vtop
->r
) {
1336 EI(0x13, 0, ireg(vtop
->r
) + 1, ireg(vtop
->r2
), 0); // mv Ra+1, RR2
1337 vtop
->r2
= 1 + vtop
->r
;
1340 vpush_helper_func(func
);
1345 if (dt
== VT_LDOUBLE
)
1346 vtop
->r
= REG_IRET
, vtop
->r2
= REG_IRET
+1;
1350 assert (dt
== VT_FLOAT
|| dt
== VT_DOUBLE
);
1351 assert (st
== VT_FLOAT
|| st
== VT_DOUBLE
);
1353 rd
= get_reg(RC_FLOAT
);
1354 if (dt
== VT_DOUBLE
)
1355 EI(0x53, 0, freg(rd
), freg(rs
), 0x21 << 5); // fcvt.d.s RD, RS (no rm)
1357 EI(0x53, 7, freg(rd
), freg(rs
), (0x20 << 5) | 1); // fcvt.s.d RD, RS (dyn rm)
1362 /* increment tcov counter */
1363 ST_FUNC
void gen_increment_tcov (SValue
*sv
)
1367 label
.type
.t
= VT_VOID
| VT_STATIC
;
1370 vtop
->r
= r1
= get_reg(RC_INT
);
1371 r2
= get_reg(RC_INT
);
1374 greloca(cur_text_section
, sv
->sym
, ind
, R_RISCV_PCREL_HI20
, 0);
1375 put_extern_sym(&label
, cur_text_section
, ind
, 0);
1376 o(0x17 | (r1
<< 7)); // auipc RR, 0 %pcrel_hi(sym)
1377 greloca(cur_text_section
, &label
, ind
, R_RISCV_PCREL_LO12_I
, 0);
1378 EI(0x03, 3, r2
, r1
, 0); // ld r2, x[r1]
1379 EI(0x13, 0, r2
, r2
, 1); // addi r2, r2, #1
1380 greloca(cur_text_section
, sv
->sym
, ind
, R_RISCV_PCREL_HI20
, 0);
1381 label
.c
= 0; /* force new local ELF symbol */
1382 put_extern_sym(&label
, cur_text_section
, ind
, 0);
1383 o(0x17 | (r1
<< 7)); // auipc RR, 0 %pcrel_hi(sym)
1384 greloca(cur_text_section
, &label
, ind
, R_RISCV_PCREL_LO12_S
, 0);
1385 ES(0x23, 3, r1
, r2
, 0); // sd r2, [r1]
1389 ST_FUNC
void ggoto(void)
1395 ST_FUNC
void gen_vla_sp_save(int addr
)
1397 if (((unsigned)addr
+ (1 << 11)) >> 12) {
1398 o(0x37 | (5 << 7) | ((0x800 + addr
) & 0xfffff000)); //lui t0,upper(addr)
1399 ER(0x33, 0, 5, 5, 8, 0); // add t0, t0, s0
1400 ES(0x23, 3, 5, 2, (int)addr
<< 20 >> 20); // sd sp, fc(t0)
1403 ES(0x23, 3, 8, 2, addr
); // sd sp, fc(s0)
1406 ST_FUNC
void gen_vla_sp_restore(int addr
)
1408 if (((unsigned)addr
+ (1 << 11)) >> 12) {
1409 o(0x37 | (5 << 7) | ((0x800 + addr
) & 0xfffff000)); //lui t0,upper(addr)
1410 ER(0x33, 0, 5, 5, 8, 0); // add t0, t0, s0
1411 EI(0x03, 3, 2, 5, (int)addr
<< 20 >> 20); // ld sp, fc(t0)
1414 EI(0x03, 3, 2, 8, addr
); // ld sp, fc(s0)
1417 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
)
1420 #if defined(CONFIG_TCC_BCHECK)
1421 if (tcc_state
->do_bounds_check
)
1424 rr
= ireg(gv(RC_INT
));
1425 #if defined(CONFIG_TCC_BCHECK)
1426 if (tcc_state
->do_bounds_check
)
1427 EI(0x13, 0, rr
, rr
, 15+1); // addi RR, RR, 15+1
1430 EI(0x13, 0, rr
, rr
, 15); // addi RR, RR, 15
1431 EI(0x13, 7, rr
, rr
, -16); // andi, RR, RR, -16
1432 ER(0x33, 0, 2, 2, rr
, 0x20); // sub sp, sp, rr
1434 #if defined(CONFIG_TCC_BCHECK)
1435 if (tcc_state
->do_bounds_check
) {
1437 vtop
->r
= TREG_R(0);
1438 o(0x00010513); /* mv a0,sp */
1440 vpush_helper_func(TOK___bound_new_region
);
1443 func_bound_add_epilog
= 1;