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fix: respect CFLAGS from environment, or set defaults
[tinycc.git] / riscv64-asm.c
blob8b7c4cefcac103e0ddf9e6d7dd7771f088ad447a
1 /*************************************************************/
2 /*
3 * RISCV64 assembler for TCC
4 *
5 */
6
7 #ifdef TARGET_DEFS_ONLY
8
9 #define CONFIG_TCC_ASM
10 /* 32 general purpose + 32 floating point registers */
11 #define NB_ASM_REGS 64
12
13 ST_FUNC void g(int c);
14 ST_FUNC void gen_le16(int c);
15 ST_FUNC void gen_le32(int c);
16
17 /*************************************************************/
18 #else
19 /*************************************************************/
20 #define USING_GLOBALS
21 #include "tcc.h"
22
23 enum {
24 OPT_REG,
25 OPT_IM12S,
26 OPT_IM32,
27 };
28 // Registers go from 0 to 31. We use next bit to choose general/float
29 #define REG_FLOAT_MASK 0x20
30 #define REG_IS_FLOAT(register_index) ((register_index) & REG_FLOAT_MASK)
31 #define REG_VALUE(register_index) ((register_index) & (REG_FLOAT_MASK-1))
32 #define C_ENCODE_RS1(register_index) (REG_VALUE(register_index) << 7)
33 #define C_ENCODE_RS2(register_index) (REG_VALUE(register_index) << 2)
34 #define ENCODE_RD(register_index) (REG_VALUE(register_index) << 7)
35 #define ENCODE_RS1(register_index) (REG_VALUE(register_index) << 15)
36 #define ENCODE_RS2(register_index) (REG_VALUE(register_index) << 20)
37 #define NTH_BIT(b, n) ((b >> n) & 1)
38 #define OP_IM12S (1 << OPT_IM12S)
39 #define OP_IM32 (1 << OPT_IM32)
40 #define OP_REG (1 << OPT_REG)
41
42 typedef struct Operand {
43 uint32_t type;
44 union {
45 uint8_t reg;
46 uint16_t regset;
47 ExprValue e;
48 };
49 } Operand;
50
51 static const Operand zero = { OP_REG, { 0 }};
52 static const Operand ra = { OP_REG, { 1 }};
53 static const Operand zimm = { OP_IM12S };
54
55 static void asm_binary_opcode(TCCState* s1, int token);
56 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str);
57 ST_FUNC void asm_compute_constraints(ASMOperand *operands, int nb_operands, int nb_outputs, const uint8_t *clobber_regs, int *pout_reg);
58 static void asm_emit_a(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *rd1, int aq, int rl);
59 static void asm_emit_b(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm);
60 static void asm_emit_i(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2);
61 static void asm_emit_j(int token, uint32_t opcode, const Operand *rd, const Operand *rs2);
62 static void asm_emit_opcode(uint32_t opcode);
63 static void asm_emit_r(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2);
64 static void asm_emit_s(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm);
65 static void asm_emit_u(int token, uint32_t opcode, const Operand *rd, const Operand *rs2);
66 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands, int nb_outputs, int is_output, uint8_t *clobber_regs, int out_reg);
67 static void asm_nullary_opcode(TCCState *s1, int token);
68 ST_FUNC void asm_opcode(TCCState *s1, int token);
69 static int asm_parse_csrvar(int t);
70 ST_FUNC int asm_parse_regvar(int t);
71 static void asm_ternary_opcode(TCCState *s1, int token);
72 static void asm_unary_opcode(TCCState *s1, int token);
73 static void asm_branch_opcode(TCCState *s1, int token, int argc);
74 ST_FUNC void gen_expr32(ExprValue *pe);
75 static void parse_operand(TCCState *s1, Operand *op);
76 static void parse_branch_offset_operand(TCCState *s1, Operand *op);
77 static void parse_operands(TCCState *s1, Operand *ops, int count);
78 static void parse_mem_access_operands(TCCState *s1, Operand* ops);
79 ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier);
80 /* C extension */
81 static void asm_emit_ca(int token, uint16_t opcode, const Operand *rd, const Operand *rs2);
82 static void asm_emit_cb(int token, uint16_t opcode, const Operand *rs1, const Operand *imm);
83 static void asm_emit_ci(int token, uint16_t opcode, const Operand *rd, const Operand *imm);
84 static void asm_emit_ciw(int token, uint16_t opcode, const Operand *rd, const Operand *imm);
85 static void asm_emit_cj(int token, uint16_t opcode, const Operand *imm);
86 static void asm_emit_cl(int token, uint16_t opcode, const Operand *rd, const Operand *rs1, const Operand *imm);
87 static void asm_emit_cr(int token, uint16_t opcode, const Operand *rd, const Operand *rs2);
88 static void asm_emit_cs(int token, uint16_t opcode, const Operand *rs2, const Operand *rs1, const Operand *imm);
89 static void asm_emit_css(int token, uint16_t opcode, const Operand *rs2, const Operand *imm);
90
91 /* XXX: make it faster ? */
92 ST_FUNC void g(int c)
93 {
94 int ind1;
95 if (nocode_wanted)
96 return;
97 ind1 = ind + 1;
98 if (ind1 > cur_text_section->data_allocated)
99 section_realloc(cur_text_section, ind1);
100 cur_text_section->data[ind] = c;
101 ind = ind1;
102 }
103
104 ST_FUNC void gen_le16 (int i)
105 {
106 g(i);
107 g(i>>8);
108 }
109
110 ST_FUNC void gen_le32 (int i)
111 {
112 int ind1;
113 if (nocode_wanted)
114 return;
115 ind1 = ind + 4;
116 if (ind1 > cur_text_section->data_allocated)
117 section_realloc(cur_text_section, ind1);
118 cur_text_section->data[ind++] = i & 0xFF;
119 cur_text_section->data[ind++] = (i >> 8) & 0xFF;
120 cur_text_section->data[ind++] = (i >> 16) & 0xFF;
121 cur_text_section->data[ind++] = (i >> 24) & 0xFF;
122 }
123
124 ST_FUNC void gen_expr32(ExprValue *pe)
125 {
126 gen_le32(pe->v);
127 }
128
129 static void asm_emit_opcode(uint32_t opcode) {
130 gen_le32(opcode);
131 }
132
133 static void asm_nullary_opcode(TCCState *s1, int token)
134 {
135 switch (token) {
136 // Sync instructions
137
138 case TOK_ASM_fence_i: // I
139 asm_emit_opcode((0x3 << 2) | 3| (1 << 12));
140 return;
141
142 // System calls
143
144 case TOK_ASM_ecall: // I (pseudo)
145 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12));
146 return;
147 case TOK_ASM_ebreak: // I (pseudo)
148 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12) | (1 << 20));
149 return;
150
151 // Other
152
153 case TOK_ASM_nop:
154 asm_emit_i(token, (4 << 2) | 3, &zero, &zero, &zimm);
155 return;
156
157 case TOK_ASM_wfi:
158 asm_emit_opcode((0x1C << 2) | 3 | (0x105 << 20));
159 return;
160
161 /* Pseudoinstructions */
162 case TOK_ASM_ret:
163 /* jalr zero, x1, 0 */
164 asm_emit_opcode( 0x67 | (0 << 12) | ENCODE_RS1(1) );
165 return;
166
167 /* C extension */
168 case TOK_ASM_c_ebreak:
169 asm_emit_cr(token, 2 | (9 << 12), &zero, &zero);
170 return;
171 case TOK_ASM_c_nop:
172 asm_emit_ci(token, 1, &zero, &zimm);
173 return;
174
175 default:
176 expect("nullary instruction");
177 }
178 }
179
180 /* Parse a text containing operand and store the result in OP */
181 static void parse_operand(TCCState *s1, Operand *op)
182 {
183 ExprValue e = {0};
184 Sym label = {0};
185 int8_t reg;
186
187 op->type = 0;
188
189 if ((reg = asm_parse_regvar(tok)) != -1) {
190 next(); // skip register name
191 op->type = OP_REG;
192 op->reg = (uint8_t) reg;
193 return;
194 } else if (tok == '$') {
195 /* constant value */
196 next(); // skip '#' or '$'
197 } else if ((e.v = asm_parse_csrvar(tok)) != -1) {
198 next();
199 } else {
200 asm_expr(s1, &e);
201 }
202 op->type = OP_IM32;
203 op->e = e;
204 /* compare against unsigned 12-bit maximum */
205 if (!op->e.sym) {
206 if ((int) op->e.v >= -0x1000 && (int) op->e.v < 0x1000)
207 op->type = OP_IM12S;
208 } else if (op->e.sym->type.t & (VT_EXTERN | VT_STATIC)) {
209 label.type.t = VT_VOID | VT_STATIC;
210
211 /* use the medium PIC model: GOT, auipc, lw */
212 if (op->e.sym->type.t & VT_STATIC)
213 greloca(cur_text_section, op->e.sym, ind, R_RISCV_PCREL_HI20, 0);
214 else
215 greloca(cur_text_section, op->e.sym, ind, R_RISCV_GOT_HI20, 0);
216 put_extern_sym(&label, cur_text_section, ind, 0);
217 greloca(cur_text_section, &label, ind+4, R_RISCV_PCREL_LO12_I, 0);
218
219 op->type = OP_IM12S;
220 op->e.v = 0;
221 } else {
222 expect("operand");
223 }
224 }
225
226 static void parse_branch_offset_operand(TCCState *s1, Operand *op){
227 ExprValue e = {0};
228
229 asm_expr(s1, &e);
230 op->type = OP_IM32;
231 op->e = e;
232 /* compare against unsigned 12-bit maximum */
233 if (!op->e.sym) {
234 if ((int) op->e.v >= -0x1000 && (int) op->e.v < 0x1000)
235 op->type = OP_IM12S;
236 } else if (op->e.sym->type.t & (VT_EXTERN | VT_STATIC)) {
237 greloca(cur_text_section, op->e.sym, ind, R_RISCV_BRANCH, 0);
238
239 /* XXX: Implement far branches */
240
241 op->type = OP_IM12S;
242 op->e.v = 0;
243 } else {
244 expect("operand");
245 }
246 }
247
248 static void parse_jump_offset_operand(TCCState *s1, Operand *op){
249 ExprValue e = {0};
250
251 asm_expr(s1, &e);
252 op->type = OP_IM32;
253 op->e = e;
254 /* compare against unsigned 12-bit maximum */
255 if (!op->e.sym) {
256 if ((int) op->e.v >= -0x1000 && (int) op->e.v < 0x1000)
257 op->type = OP_IM12S;
258 } else if (op->e.sym->type.t & (VT_EXTERN | VT_STATIC)) {
259 greloca(cur_text_section, op->e.sym, ind, R_RISCV_JAL, 0);
260 op->type = OP_IM12S;
261 op->e.v = 0;
262 } else {
263 expect("operand");
264 }
265 }
266
267 static void parse_operands(TCCState *s1, Operand* ops, int count){
268 int i;
269 for (i = 0; i < count; i++) {
270 if ( i != 0 )
271 skip(',');
272 parse_operand(s1, &ops[i]);
273 }
274 }
275
276 /* parse `X, imm(Y)` to {X, Y, imm} operands */
277 static void parse_mem_access_operands(TCCState *s1, Operand* ops){
278
279 Operand op;
280
281 parse_operand(s1, &ops[0]);
282 skip(',');
283 if ( tok == '(') {
284 /* `X, (Y)` case*/
285 next();
286 parse_operand(s1, &ops[1]);
287 skip(')');
288 ops[2] = zimm;
289 } else {
290 parse_operand(s1, &ops[2]);
291 if ( tok == '('){
292 /* `X, imm(Y)` case*/
293 next();
294 parse_operand(s1, &ops[1]);
295 skip(')');
296 } else {
297 /* `X, Y` case*/
298 /* we parsed Y thinking it was imm, swap and default imm to zero */
299 op = ops[2];
300 ops[1] = ops[2];
301 ops[2] = op;
302 ops[2] = zimm;
303 }
304 }
305 }
306
307 /* This is special: First operand is optional */
308 static void asm_jal_opcode(TCCState *s1, int token){
309 Operand ops[2];
310
311 if (token == TOK_ASM_j ){
312 ops[0] = zero; // j offset
313 } else if (asm_parse_regvar(tok) == -1) {
314 ops[0] = ra; // jal offset
315 } else {
316 // jal reg, offset
317 parse_operand(s1, &ops[0]);
318 if ( tok == ',') next(); else expect("','");
319 }
320 parse_jump_offset_operand(s1, &ops[1]);
321 asm_emit_j(token, 0x6f, &ops[0], &ops[1]);
322 }
323
324 /* This is special: It can be a pseudointruction or a instruction */
325 static void asm_jalr_opcode(TCCState *s1, int token){
326 Operand ops[3];
327 Operand op;
328
329 parse_operand(s1, &ops[0]);
330 if ( tok == ',')
331 next();
332 else {
333 /* no more operands, it's the pseudoinstruction:
334 * jalr rs
335 * Expand to:
336 * jalr ra, 0(rs)
337 */
338 asm_emit_i(token, 0x67 | (0 << 12), &ra, &ops[0], &zimm);
339 return;
340 }
341
342 if ( tok == '(') {
343 /* `X, (Y)` case*/
344 next();
345 parse_operand(s1, &ops[1]);
346 skip(')');
347 ops[2] = zimm;
348 } else {
349 parse_operand(s1, &ops[2]);
350 if ( tok == '('){
351 /* `X, imm(Y)` case*/
352 next();
353 parse_operand(s1, &ops[1]);
354 skip(')');
355 } else {
356 /* `X, Y` case*/
357 /* we parsed Y thinking it was imm, swap and default imm to zero */
358 op = ops[2];
359 ops[1] = ops[2];
360 ops[2] = op;
361 ops[2] = zimm;
362 }
363 }
364 /* jalr(RD, RS1, IMM); I-format */
365 asm_emit_i(token, 0x67 | (0 << 12), &ops[0], &ops[1], &ops[2]);
366 }
367
368
369 static void asm_unary_opcode(TCCState *s1, int token)
370 {
371 uint32_t opcode = (0x1C << 2) | 3 | (2 << 12);
372 Operand op;
373
374 parse_operands(s1, &op, 1);
375 /* Note: Those all map to CSR--so they are pseudo-instructions. */
376 opcode |= ENCODE_RD(op.reg);
377
378 switch (token) {
379 /* pseudoinstructions */
380 case TOK_ASM_rdcycle:
381 asm_emit_opcode(opcode | (0xC00 << 20));
382 return;
383 case TOK_ASM_rdcycleh:
384 asm_emit_opcode(opcode | (0xC80 << 20));
385 return;
386 case TOK_ASM_rdtime:
387 asm_emit_opcode(opcode | (0xC01 << 20) | ENCODE_RD(op.reg));
388 return;
389 case TOK_ASM_rdtimeh:
390 asm_emit_opcode(opcode | (0xC81 << 20) | ENCODE_RD(op.reg));
391 return;
392 case TOK_ASM_rdinstret:
393 asm_emit_opcode(opcode | (0xC02 << 20) | ENCODE_RD(op.reg));
394 return;
395 case TOK_ASM_rdinstreth:
396 asm_emit_opcode(opcode | (0xC82 << 20) | ENCODE_RD(op.reg));
397 return;
398
399 case TOK_ASM_jr:
400 /* jalr zero, 0(rs)*/
401 asm_emit_i(token, 0x67 | (0 << 12), &zero, &op, &zimm);
402 return;
403 case TOK_ASM_call:
404 /* auipc ra, 0 */
405 greloca(cur_text_section, op.e.sym, ind, R_RISCV_CALL, 0);
406 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(1));
407 /* jalr zero, 0(ra) */
408 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(1));
409 return;
410 case TOK_ASM_tail:
411 /* auipc x6, 0 */
412 greloca(cur_text_section, op.e.sym, ind, R_RISCV_CALL, 0);
413 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(6));
414 /* jalr zero, 0(x6) */
415 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(6));
416 return;
417
418 /* C extension */
419 case TOK_ASM_c_j:
420 asm_emit_cj(token, 1 | (5 << 13), &op);
421 return;
422 case TOK_ASM_c_jal: /* RV32C-only */
423 asm_emit_cj(token, 1 | (1 << 13), &op);
424 return;
425 case TOK_ASM_c_jalr:
426 asm_emit_cr(token, 2 | (9 << 12), &op, &zero);
427 return;
428 case TOK_ASM_c_jr:
429 asm_emit_cr(token, 2 | (8 << 12), &op, &zero);
430 return;
431 default:
432 expect("unary instruction");
433 }
434 }
435
436 static void asm_emit_u(int token, uint32_t opcode, const Operand* rd, const Operand* rs2)
437 {
438 if (rd->type != OP_REG) {
439 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
440 }
441 if (rs2->type != OP_IM12S && rs2->type != OP_IM32) {
442 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token, NULL));
443 } else if (rs2->e.v >= 0x100000) {
444 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0xfffff", get_tok_str(token, NULL));
445 }
446 /* U-type instruction:
447 31...12 imm[31:12]
448 11...7 rd
449 6...0 opcode */
450 gen_le32(opcode | ENCODE_RD(rd->reg) | (rs2->e.v << 12));
451 }
452
453 static int parse_fence_operand(){
454 int t = tok;
455 if ( tok == TOK_ASM_or ){
456 // we are in a fence instruction, parse as output read
457 t = TOK_ASM_or_fence;
458 }
459 next();
460 return t - (TOK_ASM_w_fence - 1);
461 }
462
463 static void asm_fence_opcode(TCCState *s1, int token){
464 // `fence` is both an instruction and a pseudoinstruction:
465 // `fence` expands to `fence iorw, iorw`
466 int succ = 0xF, pred = 0xF;
467 if (tok != TOK_LINEFEED && tok != ';' && tok != CH_EOF){
468 pred = parse_fence_operand();
469 if ( pred > 0xF || pred < 0) {
470 tcc_error("'%s': Expected first operand that is a valid predecessor operand", get_tok_str(token, NULL));
471 }
472 skip(',');
473 succ = parse_fence_operand();
474 if ( succ > 0xF || succ < 0) {
475 tcc_error("'%s': Expected second operand that is a valid successor operand", get_tok_str(token, NULL));
476 }
477 }
478 asm_emit_opcode((0x3 << 2) | 3 | (0 << 12) | succ<<20 | pred<<24);
479 }
480
481 static void asm_binary_opcode(TCCState* s1, int token)
482 {
483 Operand imm = { OP_IM12S };
484 Operand ops[2];
485 int32_t lo;
486 uint32_t hi;
487
488 parse_operands(s1, &ops[0], 2);
489 switch (token) {
490 case TOK_ASM_lui:
491 asm_emit_u(token, (0xD << 2) | 3, &ops[0], &ops[1]);
492 return;
493 case TOK_ASM_auipc:
494 asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[1]);
495 return;
496
497 /* C extension */
498 case TOK_ASM_c_add:
499 asm_emit_cr(token, 2 | (9 << 12), ops, ops + 1);
500 return;
501 case TOK_ASM_c_mv:
502 asm_emit_cr(token, 2 | (8 << 12), ops, ops + 1);
503 return;
504
505 case TOK_ASM_c_addi16sp:
506 asm_emit_ci(token, 1 | (3 << 13), ops, ops + 1);
507 return;
508 case TOK_ASM_c_addi:
509 asm_emit_ci(token, 1, ops, ops + 1);
510 return;
511 case TOK_ASM_c_addiw:
512 asm_emit_ci(token, 1 | (1 << 13), ops, ops + 1);
513 return;
514 case TOK_ASM_c_fldsp:
515 asm_emit_ci(token, 2 | (1 << 13), ops, ops + 1);
516 return;
517 case TOK_ASM_c_flwsp: /* RV32FC-only */
518 asm_emit_ci(token, 2 | (3 << 13), ops, ops + 1);
519 return;
520 case TOK_ASM_c_ldsp:
521 asm_emit_ci(token, 2 | (3 << 13), ops, ops + 1);
522 return;
523 case TOK_ASM_c_li:
524 asm_emit_ci(token, 1 | (2 << 13), ops, ops + 1);
525 return;
526 case TOK_ASM_c_lui:
527 asm_emit_ci(token, 1 | (3 << 13), ops, ops + 1);
528 return;
529 case TOK_ASM_c_lwsp:
530 asm_emit_ci(token, 2 | (2 << 13), ops, ops + 1);
531 return;
532 case TOK_ASM_c_slli:
533 asm_emit_ci(token, 2, ops, ops + 1);
534 return;
535
536 case TOK_ASM_c_addi4spn:
537 asm_emit_ciw(token, 0, ops, ops + 1);
538 return;
539
540 #define CA (1 | (3 << 10) | (4 << 13))
541 case TOK_ASM_c_addw:
542 asm_emit_ca(token, CA | (1 << 5) | (1 << 12), ops, ops + 1);
543 return;
544 case TOK_ASM_c_and:
545 asm_emit_ca(token, CA | (3 << 5), ops, ops + 1);
546 return;
547 case TOK_ASM_c_or:
548 asm_emit_ca(token, CA | (2 << 5), ops, ops + 1);
549 return;
550 case TOK_ASM_c_sub:
551 asm_emit_ca(token, CA, ops, ops + 1);
552 return;
553 case TOK_ASM_c_subw:
554 asm_emit_ca(token, CA | (1 << 12), ops, ops + 1);
555 return;
556 case TOK_ASM_c_xor:
557 asm_emit_ca(token, CA | (1 << 5), ops, ops + 1);
558 return;
559 #undef CA
560
561 case TOK_ASM_c_andi:
562 asm_emit_cb(token, 1 | (2 << 10) | (4 << 13), ops, ops + 1);
563 return;
564 case TOK_ASM_c_beqz:
565 asm_emit_cb(token, 1 | (6 << 13), ops, ops + 1);
566 return;
567 case TOK_ASM_c_bnez:
568 asm_emit_cb(token, 1 | (7 << 13), ops, ops + 1);
569 return;
570 case TOK_ASM_c_srai:
571 asm_emit_cb(token, 1 | (1 << 10) | (4 << 13), ops, ops + 1);
572 return;
573 case TOK_ASM_c_srli:
574 asm_emit_cb(token, 1 | (4 << 13), ops, ops + 1);
575 return;
576
577 case TOK_ASM_c_sdsp:
578 asm_emit_css(token, 2 | (7 << 13), ops, ops + 1);
579 return;
580 case TOK_ASM_c_swsp:
581 asm_emit_css(token, 2 | (6 << 13), ops, ops + 1);
582 return;
583 case TOK_ASM_c_fswsp: /* RV32FC-only */
584 asm_emit_css(token, 2 | (7 << 13), ops, ops + 1);
585 return;
586 case TOK_ASM_c_fsdsp:
587 asm_emit_css(token, 2 | (5 << 13), ops, ops + 1);
588 return;
589
590 /* pseudoinstructions */
591 /* rd, sym */
592 case TOK_ASM_la:
593 /* auipc rd, 0 */
594 asm_emit_u(token, 3 | (5 << 2), ops, ops + 1);
595 /* lw rd, rd, 0 */
596 asm_emit_i(token, 3 | (2 << 12), ops, ops, ops + 1);
597 return;
598 case TOK_ASM_lla:
599 /* auipc rd, 0 */
600 asm_emit_u(token, 3 | (5 << 2), ops, ops + 1);
601 /* addi rd, rd, 0 */
602 asm_emit_i(token, 3 | (4 << 2), ops, ops, ops + 1);
603 return;
604 case TOK_ASM_li:
605 if(ops[1].type != OP_IM32 && ops[1].type != OP_IM12S){
606 tcc_error("'%s': Expected first source operand that is an immediate value between 0 and 0xFFFFFFFFFFFFFFFF", get_tok_str(token, NULL));
607 }
608 lo = ops[1].e.v;
609 hi = (int64_t)ops[1].e.v >> 32;
610 if(lo < 0){
611 hi += 1;
612 }
613 imm.e.v = ((hi + 0x800) & 0xfffff000) >> 12;
614 /* lui rd, HI_20(HI_32(imm)) */
615 asm_emit_u(token, (0xD << 2) | 3, &ops[0], &imm);
616 /* addi rd, rd, LO_12(HI_32(imm)) */
617 imm.e.v = (int32_t)hi<<20>>20;
618 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
619 /* slli rd, rd, 12 */
620 imm.e.v = 12;
621 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
622 /* addi rd, rd, HI_12(LO_32(imm)) */
623 imm.e.v = (lo + (1<<19)) >> 20;
624 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
625 /* slli rd, rd, 12 */
626 imm.e.v = 12;
627 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
628 /* addi rd, rd, HI_12(LO_20(LO_32imm)) */
629 lo = lo << 12 >> 12;
630 imm.e.v = lo >> 8;
631 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
632 /* slli rd, rd, 8 */
633 imm.e.v = 8;
634 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
635 /* addi rd, rd, LO_8(LO_20(LO_32imm)) */
636 lo &= 0xff;
637 imm.e.v = lo << 20 >> 20;
638 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
639 return;
640 case TOK_ASM_mv:
641 /* addi rd, rs, 0 */
642 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[1], &imm);
643 return;
644 case TOK_ASM_not:
645 /* xori rd, rs, -1 */
646 imm.e.v = -1;
647 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &imm);
648 return;
649 case TOK_ASM_neg:
650 /* sub rd, x0, rs */
651 imm.e.v = 1;
652 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &zero, &imm);
653 return;
654 case TOK_ASM_negw:
655 /* sub rd, x0, rs */
656 imm.e.v = 1;
657 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &zero, &imm);
658 return;
659 case TOK_ASM_jump:
660 /* auipc x5, 0 */
661 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(5));
662 greloca(cur_text_section, ops->e.sym, ind, R_RISCV_CALL, 0);
663 /* jalr zero, 0(x5) */
664 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(5));
665 return;
666 case TOK_ASM_seqz:
667 /* sltiu rd, rs, 1 */
668 imm.e.v = 1;
669 asm_emit_i(token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &imm);
670 return;
671 case TOK_ASM_snez:
672 /* sltu rd, zero, rs */
673 imm.e.v = 1;
674 asm_emit_r(token, (0xC << 2) | 3 | (3 << 12), &ops[0], &zero, &ops[1]);
675 return;
676 case TOK_ASM_sltz:
677 /* slt rd, rs, zero */
678 asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &ops[1], &zero);
679 return;
680 case TOK_ASM_sgtz:
681 /* slt rd, zero, rs */
682 asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &zero, &ops[1]);
683 return;
684
685 default:
686 expect("binary instruction");
687 }
688 }
689
690 /* caller: Add funct3, funct7 into opcode */
691 static void asm_emit_r(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2)
692 {
693 if (rd->type != OP_REG) {
694 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
695 }
696 if (rs1->type != OP_REG) {
697 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
698 }
699 if (rs2->type != OP_REG) {
700 tcc_error("'%s': Expected second source operand that is a register or immediate", get_tok_str(token, NULL));
701 }
702 /* R-type instruction:
703 31...25 funct7
704 24...20 rs2
705 19...15 rs1
706 14...12 funct3
707 11...7 rd
708 6...0 opcode */
709 gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg));
710 }
711
712 /* caller: Add funct3 into opcode */
713 static void asm_emit_i(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2)
714 {
715 if (rd->type != OP_REG) {
716 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
717 }
718 if (rs1->type != OP_REG) {
719 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
720 }
721 if (rs2->type != OP_IM12S) {
722 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token, NULL));
723 }
724 /* I-type instruction:
725 31...20 imm[11:0]
726 19...15 rs1
727 14...12 funct3
728 11...7 rd
729 6...0 opcode */
730
731 gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | (rs2->e.v << 20));
732 }
733
734 static void asm_emit_j(int token, uint32_t opcode, const Operand* rd, const Operand* rs2)
735 {
736 uint32_t imm;
737
738 if (rd->type != OP_REG) {
739 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
740 }
741 if (rs2->type != OP_IM12S && rs2->type != OP_IM32) {
742 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token, NULL));
743 }
744
745 imm = rs2->e.v;
746
747 /* even offsets in a +- 1 MiB range */
748 if ((int)imm > (1 << 20) -1 || (int)imm <= -1 * ((1 << 20) -1)) {
749 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0x1fffff", get_tok_str(token, NULL));
750 }
751
752 if (imm & 1) {
753 tcc_error("'%s': Expected second source operand that is an even immediate value", get_tok_str(token, NULL));
754 }
755 /* J-type instruction:
756 31 imm[20]
757 30...21 imm[10:1]
758 20 imm[11]
759 19...12 imm[19:12]
760 11...7 rd
761 6...0 opcode */
762 gen_le32(opcode | ENCODE_RD(rd->reg) | (((imm >> 20) & 1) << 31) | (((imm >> 1) & 0x3ff) << 21) | (((imm >> 11) & 1) << 20) | (((imm >> 12) & 0xff) << 12));
763 }
764
765 static void asm_mem_access_opcode(TCCState *s1, int token)
766 {
767
768 Operand ops[3];
769 parse_mem_access_operands(s1, &ops[0]);
770
771 /* Pseudoinstruction: inst reg, label
772 * expand to:
773 * auipc reg, 0
774 * inst reg, 0(reg)
775 * And with the proper relocation to label
776 */
777 if (ops[1].type == OP_IM32 && ops[1].e.sym && ops[1].e.sym->type.t & VT_STATIC){
778 ops[1] = ops[0];
779 /* set the offset to zero */
780 ops[2].type = OP_IM12S;
781 ops[2].e.v = 0;
782 /* auipc reg, 0 */
783 asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[2]);
784 }
785
786 switch (token) {
787 // l{b|h|w|d}[u] rd, imm(rs1); I-format
788 case TOK_ASM_lb:
789 asm_emit_i(token, (0x0 << 2) | 3, &ops[0], &ops[1], &ops[2]);
790 return;
791 case TOK_ASM_lh:
792 asm_emit_i(token, (0x0 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
793 return;
794 case TOK_ASM_lw:
795 asm_emit_i(token, (0x0 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]);
796 return;
797 case TOK_ASM_ld:
798 asm_emit_i(token, (0x0 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]);
799 return;
800 case TOK_ASM_lbu:
801 asm_emit_i(token, (0x0 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
802 return;
803 case TOK_ASM_lhu:
804 asm_emit_i(token, (0x0 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
805 return;
806 case TOK_ASM_lwu:
807 asm_emit_i(token, (0x0 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]);
808 return;
809
810 // s{b|h|w|d} rs2, imm(rs1); S-format (with rsX swapped)
811 case TOK_ASM_sb:
812 asm_emit_s(token, (0x8 << 2) | 3 | (0 << 12), &ops[1], &ops[0], &ops[2]);
813 return;
814 case TOK_ASM_sh:
815 asm_emit_s(token, (0x8 << 2) | 3 | (1 << 12), &ops[1], &ops[0], &ops[2]);
816 return;
817 case TOK_ASM_sw:
818 asm_emit_s(token, (0x8 << 2) | 3 | (2 << 12), &ops[1], &ops[0], &ops[2]);
819 return;
820 case TOK_ASM_sd:
821 asm_emit_s(token, (0x8 << 2) | 3 | (3 << 12), &ops[1], &ops[0], &ops[2]);
822 return;
823 }
824 }
825
826 static void asm_branch_opcode(TCCState *s1, int token, int argc)
827 {
828 Operand ops[3];
829 parse_operands(s1, &ops[0], argc-1);
830 skip(',');
831 parse_branch_offset_operand(s1, &ops[argc-1]);
832
833 switch(token){
834 /* branch (RS1, RS2, IMM); B-format */
835 case TOK_ASM_beq:
836 asm_emit_b(token, 0x63 | (0 << 12), ops, ops + 1, ops + 2);
837 return;
838 case TOK_ASM_bne:
839 asm_emit_b(token, 0x63 | (1 << 12), ops, ops + 1, ops + 2);
840 return;
841 case TOK_ASM_blt:
842 asm_emit_b(token, 0x63 | (4 << 12), ops, ops + 1, ops + 2);
843 return;
844 case TOK_ASM_bge:
845 asm_emit_b(token, 0x63 | (5 << 12), ops, ops + 1, ops + 2);
846 return;
847 case TOK_ASM_bltu:
848 asm_emit_b(token, 0x63 | (6 << 12), ops, ops + 1, ops + 2);
849 return;
850 case TOK_ASM_bgeu:
851 asm_emit_b(token, 0x63 | (7 << 12), ops, ops + 1, ops + 2);
852 return;
853 /* related pseudoinstructions */
854 case TOK_ASM_bgt:
855 asm_emit_b(token, 0x63 | (4 << 12), ops + 1, ops, ops + 2);
856 return;
857 case TOK_ASM_ble:
858 asm_emit_b(token, 0x63 | (5 << 12), ops + 1, ops, ops + 2);
859 return;
860 case TOK_ASM_bgtu:
861 asm_emit_b(token, 0x63 | (6 << 12), ops + 1, ops, ops + 2);
862 return;
863 case TOK_ASM_bleu:
864 asm_emit_b(token, 0x63 | (7 << 12), ops + 1, ops, ops + 2);
865 return;
866 /* shorter pseudoinstructions */
867 case TOK_ASM_bnez:
868 /* bne rs, zero, offset */
869 asm_emit_b(token, 0x63 | (1 << 12), &ops[0], &zero, &ops[1]);
870 return;
871 case TOK_ASM_beqz:
872 /* bne rs, zero, offset */
873 asm_emit_b(token, 0x63 | (0 << 12), &ops[0], &zero, &ops[1]);
874 return;
875 case TOK_ASM_blez:
876 /* bge rs, zero, offset */
877 asm_emit_b(token, 0x63 | (5 << 12), &ops[0], &zero, &ops[1]);
878 return;
879 case TOK_ASM_bgez:
880 /* bge zero, rs, offset */
881 asm_emit_b(token, 0x63 | (5 << 12), &zero, &ops[0], &ops[1]);
882 return;
883 case TOK_ASM_bltz:
884 /* blt rs, zero, offset */
885 asm_emit_b(token, 0x63 | (4 << 12), &ops[0], &zero, &ops[1]);
886 return;
887 case TOK_ASM_bgtz:
888 /* blt zero, rs, offset */
889 asm_emit_b(token, 0x63 | (4 << 12), &zero, &ops[0], &ops[1]);
890 return;
891 }
892 }
893
894 static void asm_ternary_opcode(TCCState *s1, int token)
895 {
896 Operand ops[3];
897 parse_operands(s1, &ops[0], 3);
898
899 switch (token) {
900 case TOK_ASM_sll:
901 asm_emit_r(token, (0xC << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
902 return;
903 case TOK_ASM_slli:
904 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
905 return;
906 case TOK_ASM_srl:
907 asm_emit_r(token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
908 return;
909 case TOK_ASM_srli:
910 asm_emit_i(token, (0x4 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
911 return;
912 case TOK_ASM_sra:
913 asm_emit_r(token, (0xC << 2) | 3 | (5 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]);
914 return;
915 case TOK_ASM_srai:
916 asm_emit_i(token, (0x4 << 2) | 3 | (5 << 12) | (16 << 26), &ops[0], &ops[1], &ops[2]);
917 return;
918 case TOK_ASM_sllw:
919 asm_emit_r(token, (0xE << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
920 return;
921 case TOK_ASM_slliw:
922 asm_emit_i(token, (6 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
923 return;
924 case TOK_ASM_srlw:
925 asm_emit_r(token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
926 return;
927 case TOK_ASM_srliw:
928 asm_emit_i(token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
929 return;
930 case TOK_ASM_sraw:
931 asm_emit_r(token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
932 return;
933 case TOK_ASM_sraiw:
934 asm_emit_i(token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
935 return;
936
937 // Arithmetic (RD,RS1,(RS2|IMM)); R-format, I-format or U-format
938
939 case TOK_ASM_add:
940 asm_emit_r(token, (0xC << 2) | 3, &ops[0], &ops[1], &ops[2]);
941 return;
942 case TOK_ASM_addi:
943 asm_emit_i(token, (4 << 2) | 3, &ops[0], &ops[1], &ops[2]);
944 return;
945 case TOK_ASM_sub:
946 asm_emit_r(token, (0xC << 2) | 3 | (32 << 25), &ops[0], &ops[1], &ops[2]);
947 return;
948 case TOK_ASM_addw:
949 asm_emit_r(token, (0xE << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]);
950 return;
951 case TOK_ASM_addiw: // 64 bit
952 asm_emit_i(token, (0x6 << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]);
953 return;
954 case TOK_ASM_subw:
955 asm_emit_r(token, (0xE << 2) | 3 | (0 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]);
956 return;
957
958 // Logical (RD,RS1,(RS2|IMM)); R-format or I-format
959
960 case TOK_ASM_xor:
961 asm_emit_r(token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
962 return;
963 case TOK_ASM_xori:
964 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
965 return;
966 case TOK_ASM_or:
967 asm_emit_r(token, (0xC << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]);
968 return;
969 case TOK_ASM_ori:
970 asm_emit_i(token, (0x4 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]);
971 return;
972 case TOK_ASM_and:
973 asm_emit_r(token, (0xC << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]);
974 return;
975 case TOK_ASM_andi:
976 asm_emit_i(token, (0x4 << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]);
977 return;
978
979 // Compare (RD,RS1,(RS2|IMM)); R-format or I-format
980
981 case TOK_ASM_slt:
982 asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]);
983 return;
984 case TOK_ASM_slti:
985 asm_emit_i(token, (0x4 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]);
986 return;
987 case TOK_ASM_sltu:
988 asm_emit_r(token, (0xC << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]);
989 return;
990 case TOK_ASM_sltiu:
991 asm_emit_i(token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]);
992 return;
993
994 /* M extension */
995 case TOK_ASM_div:
996 asm_emit_r(token, 0x33 | (4 << 12) | (1 << 25), ops, ops + 1, ops + 2);
997 return;
998 case TOK_ASM_divu:
999 asm_emit_r(token, 0x33 | (5 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1000 return;
1001 case TOK_ASM_divuw:
1002 asm_emit_r(token, 0x3b | (5 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1003 return;
1004 case TOK_ASM_divw:
1005 asm_emit_r(token, 0x3b | (4 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1006 return;
1007 case TOK_ASM_mul:
1008 asm_emit_r(token, 0x33 | (1 << 25), ops, ops + 1, ops + 2);
1009 return;
1010 case TOK_ASM_mulh:
1011 asm_emit_r(token, 0x33 | (1 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1012 return;
1013 case TOK_ASM_mulhsu:
1014 asm_emit_r(token, 0x33 | (2 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1015 return;
1016 case TOK_ASM_mulhu:
1017 asm_emit_r(token, 0x33 | (3 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1018 return;
1019 case TOK_ASM_mulw:
1020 asm_emit_r(token, 0x3b | (1 << 25), ops, ops + 1, ops + 2);
1021 return;
1022 case TOK_ASM_rem:
1023 asm_emit_r(token, 0x33 | (6 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1024 return;
1025 case TOK_ASM_remu:
1026 asm_emit_r(token, 0x33 | (7 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1027 return;
1028 case TOK_ASM_remuw:
1029 asm_emit_r(token, 0x3b | (7 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1030 return;
1031 case TOK_ASM_remw:
1032 asm_emit_r(token, 0x3b | (6 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1033 return;
1034
1035 /* Zicsr extension; (rd, csr, rs/uimm) */
1036 case TOK_ASM_csrrc:
1037 asm_emit_i(token, 0x73 | (3 << 12), ops, ops + 2, ops + 1);
1038 return;
1039 case TOK_ASM_csrrci:
1040 /* using rs1 field for uimmm */
1041 ops[2].type = OP_REG;
1042 asm_emit_i(token, 0x73 | (7 << 12), ops, ops + 2, ops + 1);
1043 return;
1044 case TOK_ASM_csrrs:
1045 asm_emit_i(token, 0x73 | (2 << 12), ops, ops + 2, ops + 1);
1046 return;
1047 case TOK_ASM_csrrsi:
1048 ops[2].type = OP_REG;
1049 asm_emit_i(token, 0x73 | (6 << 12), ops, ops + 2, ops + 1);
1050 return;
1051 case TOK_ASM_csrrw:
1052 asm_emit_i(token, 0x73 | (1 << 12), ops, ops + 2, ops + 1);
1053 return;
1054 case TOK_ASM_csrrwi:
1055 ops[2].type = OP_REG;
1056 asm_emit_i(token, 0x73 | (5 << 12), ops, ops + 2, ops + 1);
1057 return;
1058
1059 /* C extension */
1060 /* register-based loads and stores (RD, RS1, IMM); CL-format */
1061 case TOK_ASM_c_fld:
1062 asm_emit_cl(token, 1 << 13, ops, ops + 1, ops + 2);
1063 return;
1064 case TOK_ASM_c_flw: /* RV32FC-only */
1065 asm_emit_cl(token, 3 << 13, ops, ops + 1, ops + 2);
1066 return;
1067 case TOK_ASM_c_fsd:
1068 asm_emit_cs(token, 5 << 13, ops, ops + 1, ops + 2);
1069 return;
1070 case TOK_ASM_c_fsw: /* RV32FC-only */
1071 asm_emit_cs(token, 7 << 13, ops, ops + 1, ops + 2);
1072 return;
1073 case TOK_ASM_c_ld:
1074 asm_emit_cl(token, 3 << 13, ops, ops + 1, ops + 2);
1075 return;
1076 case TOK_ASM_c_lw:
1077 asm_emit_cl(token, 2 << 13, ops, ops + 1, ops + 2);
1078 return;
1079 case TOK_ASM_c_sd:
1080 asm_emit_cs(token, 7 << 13, ops, ops + 1, ops + 2);
1081 return;
1082 case TOK_ASM_c_sw:
1083 asm_emit_cs(token, 6 << 13, ops, ops + 1, ops + 2);
1084 return;
1085
1086 default:
1087 expect("ternary instruction");
1088 }
1089 }
1090
1091 static void asm_atomic_opcode(TCCState *s1, int token)
1092 {
1093 Operand ops[3];
1094
1095 parse_operand(s1, &ops[0]);
1096 skip(',');
1097
1098 if ( token <= TOK_ASM_lr_d_aqrl && token >= TOK_ASM_lr_w ) {
1099 ops[1] = zero;
1100 } else {
1101 parse_operand(s1, &ops[1]);
1102 skip(',');
1103 }
1104
1105 skip('(');
1106 parse_operand(s1, &ops[2]);
1107 skip(')');
1108
1109 switch(token){
1110 case TOK_ASM_lr_w:
1111 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1112 break;
1113 case TOK_ASM_lr_w_aq:
1114 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1115 break;
1116 case TOK_ASM_lr_w_rl:
1117 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1118 break;
1119 case TOK_ASM_lr_w_aqrl:
1120 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1121 break;
1122
1123 case TOK_ASM_lr_d:
1124 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1125 break;
1126 case TOK_ASM_lr_d_aq:
1127 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1128 break;
1129 case TOK_ASM_lr_d_rl:
1130 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1131 break;
1132 case TOK_ASM_lr_d_aqrl:
1133 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1134 break;
1135
1136 case TOK_ASM_sc_w:
1137 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1138 break;
1139 case TOK_ASM_sc_w_aq:
1140 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1141 break;
1142 case TOK_ASM_sc_w_rl:
1143 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1144 break;
1145 case TOK_ASM_sc_w_aqrl:
1146 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1147 break;
1148
1149 case TOK_ASM_sc_d:
1150 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1151 break;
1152 case TOK_ASM_sc_d_aq:
1153 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1154 break;
1155 case TOK_ASM_sc_d_rl:
1156 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1157 break;
1158 case TOK_ASM_sc_d_aqrl:
1159 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1160 break;
1161 }
1162 }
1163
1164 /* caller: Add funct3 and func5 to opcode */
1165 static void asm_emit_a(int token, uint32_t opcode, const Operand *rd1, const Operand *rs2, const Operand *rs1, int aq, int rl)
1166 {
1167 if (rd1->type != OP_REG)
1168 tcc_error("'%s': Expected first destination operand that is a register", get_tok_str(token, NULL));
1169 if (rs2->type != OP_REG)
1170 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token, NULL));
1171 if (rs1->type != OP_REG)
1172 tcc_error("'%s': Expected third source operand that is a register", get_tok_str(token, NULL));
1173 /* A-type instruction:
1174 31...27 funct5
1175 26 aq
1176 25 rl
1177 24...20 rs2
1178 19...15 rs1
1179 14...11 funct3
1180 11...7 rd
1181 6...0 opcode
1182 opcode always fixed pos. */
1183 gen_le32(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | ENCODE_RD(rd1->reg) | aq << 26 | rl << 25);
1184 }
1185
1186 /* caller: Add funct3 to opcode */
1187 static void asm_emit_s(int token, uint32_t opcode, const Operand* rs1, const Operand* rs2, const Operand* imm)
1188 {
1189 if (rs1->type != OP_REG) {
1190 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
1191 }
1192 if (rs2->type != OP_REG) {
1193 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token, NULL));
1194 }
1195 if (imm->type != OP_IM12S) {
1196 tcc_error("'%s': Expected third operand that is an immediate value between 0 and 8191", get_tok_str(token, NULL));
1197 }
1198 {
1199 uint16_t v = imm->e.v;
1200 /* S-type instruction:
1201 31...25 imm[11:5]
1202 24...20 rs2
1203 19...15 rs1
1204 14...12 funct3
1205 11...7 imm[4:0]
1206 6...0 opcode
1207 opcode always fixed pos. */
1208 gen_le32(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | ((v & 0x1F) << 7) | ((v >> 5) << 25));
1209 }
1210 }
1211
1212 static void asm_emit_b(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm)
1213 {
1214 uint32_t offset;
1215
1216 if (rs1->type != OP_REG) {
1217 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
1218 }
1219 if (rs2->type != OP_REG) {
1220 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
1221 }
1222 if (imm->type != OP_IM12S) {
1223 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token, NULL));
1224 }
1225
1226 offset = imm->e.v;
1227
1228 /* B-type instruction:
1229 31 imm[12]
1230 30...25 imm[10:5]
1231 24...20 rs2
1232 19...15 rs1
1233 14...12 funct3
1234 8...11 imm[4:1]
1235 7 imm[11]
1236 6...0 opcode */
1237 asm_emit_opcode(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | (((offset >> 1) & 0xF) << 8) | (((offset >> 5) & 0x1f) << 25) | (((offset >> 11) & 1) << 7) | (((offset >> 12) & 1) << 31));
1238 }
1239
1240 ST_FUNC void asm_opcode(TCCState *s1, int token)
1241 {
1242 switch (token) {
1243 case TOK_ASM_ebreak:
1244 case TOK_ASM_ecall:
1245 case TOK_ASM_fence_i:
1246 case TOK_ASM_hrts:
1247 case TOK_ASM_mrth:
1248 case TOK_ASM_mrts:
1249 case TOK_ASM_wfi:
1250 asm_nullary_opcode(s1, token);
1251 return;
1252
1253 case TOK_ASM_fence:
1254 asm_fence_opcode(s1, token);
1255 return;
1256
1257 case TOK_ASM_rdcycle:
1258 case TOK_ASM_rdcycleh:
1259 case TOK_ASM_rdtime:
1260 case TOK_ASM_rdtimeh:
1261 case TOK_ASM_rdinstret:
1262 case TOK_ASM_rdinstreth:
1263 asm_unary_opcode(s1, token);
1264 return;
1265
1266 case TOK_ASM_lui:
1267 case TOK_ASM_auipc:
1268 asm_binary_opcode(s1, token);
1269 return;
1270
1271 case TOK_ASM_lb:
1272 case TOK_ASM_lh:
1273 case TOK_ASM_lw:
1274 case TOK_ASM_ld:
1275 case TOK_ASM_lbu:
1276 case TOK_ASM_lhu:
1277 case TOK_ASM_lwu:
1278 case TOK_ASM_sb:
1279 case TOK_ASM_sh:
1280 case TOK_ASM_sw:
1281 case TOK_ASM_sd:
1282 asm_mem_access_opcode(s1, token);
1283 break;
1284
1285 case TOK_ASM_jalr:
1286 asm_jalr_opcode(s1, token); /* it can be a pseudo instruction too*/
1287 break;
1288 case TOK_ASM_j:
1289 asm_jal_opcode(s1, token); /* jal zero, offset*/
1290 return;
1291 case TOK_ASM_jal:
1292 asm_jal_opcode(s1, token); /* it can be a pseudo instruction too*/
1293 break;
1294
1295 case TOK_ASM_add:
1296 case TOK_ASM_addi:
1297 case TOK_ASM_addiw:
1298 case TOK_ASM_addw:
1299 case TOK_ASM_and:
1300 case TOK_ASM_andi:
1301 case TOK_ASM_or:
1302 case TOK_ASM_ori:
1303 case TOK_ASM_sll:
1304 case TOK_ASM_slli:
1305 case TOK_ASM_slliw:
1306 case TOK_ASM_sllw:
1307 case TOK_ASM_slt:
1308 case TOK_ASM_slti:
1309 case TOK_ASM_sltiu:
1310 case TOK_ASM_sltu:
1311 case TOK_ASM_sra:
1312 case TOK_ASM_srai:
1313 case TOK_ASM_sraiw:
1314 case TOK_ASM_sraw:
1315 case TOK_ASM_srl:
1316 case TOK_ASM_srli:
1317 case TOK_ASM_srliw:
1318 case TOK_ASM_srlw:
1319 case TOK_ASM_sub:
1320 case TOK_ASM_subw:
1321 case TOK_ASM_xor:
1322 case TOK_ASM_xori:
1323 /* M extension */
1324 case TOK_ASM_div:
1325 case TOK_ASM_divu:
1326 case TOK_ASM_divuw:
1327 case TOK_ASM_divw:
1328 case TOK_ASM_mul:
1329 case TOK_ASM_mulh:
1330 case TOK_ASM_mulhsu:
1331 case TOK_ASM_mulhu:
1332 case TOK_ASM_mulw:
1333 case TOK_ASM_rem:
1334 case TOK_ASM_remu:
1335 case TOK_ASM_remuw:
1336 case TOK_ASM_remw:
1337 /* Zicsr extension */
1338 case TOK_ASM_csrrc:
1339 case TOK_ASM_csrrci:
1340 case TOK_ASM_csrrs:
1341 case TOK_ASM_csrrsi:
1342 case TOK_ASM_csrrw:
1343 case TOK_ASM_csrrwi:
1344 asm_ternary_opcode(s1, token);
1345 return;
1346
1347 /* Branches */
1348 case TOK_ASM_beq:
1349 case TOK_ASM_bge:
1350 case TOK_ASM_bgeu:
1351 case TOK_ASM_blt:
1352 case TOK_ASM_bltu:
1353 case TOK_ASM_bne:
1354 asm_branch_opcode(s1, token, 3);
1355 break;
1356
1357 /* C extension */
1358 case TOK_ASM_c_ebreak:
1359 case TOK_ASM_c_nop:
1360 asm_nullary_opcode(s1, token);
1361 return;
1362
1363 case TOK_ASM_c_j:
1364 case TOK_ASM_c_jal:
1365 case TOK_ASM_c_jalr:
1366 case TOK_ASM_c_jr:
1367 asm_unary_opcode(s1, token);
1368 return;
1369
1370 case TOK_ASM_c_add:
1371 case TOK_ASM_c_addi16sp:
1372 case TOK_ASM_c_addi4spn:
1373 case TOK_ASM_c_addi:
1374 case TOK_ASM_c_addiw:
1375 case TOK_ASM_c_addw:
1376 case TOK_ASM_c_and:
1377 case TOK_ASM_c_andi:
1378 case TOK_ASM_c_beqz:
1379 case TOK_ASM_c_bnez:
1380 case TOK_ASM_c_fldsp:
1381 case TOK_ASM_c_flwsp:
1382 case TOK_ASM_c_fsdsp:
1383 case TOK_ASM_c_fswsp:
1384 case TOK_ASM_c_ldsp:
1385 case TOK_ASM_c_li:
1386 case TOK_ASM_c_lui:
1387 case TOK_ASM_c_lwsp:
1388 case TOK_ASM_c_mv:
1389 case TOK_ASM_c_or:
1390 case TOK_ASM_c_sdsp:
1391 case TOK_ASM_c_slli:
1392 case TOK_ASM_c_srai:
1393 case TOK_ASM_c_srli:
1394 case TOK_ASM_c_sub:
1395 case TOK_ASM_c_subw:
1396 case TOK_ASM_c_swsp:
1397 case TOK_ASM_c_xor:
1398 asm_binary_opcode(s1, token);
1399 return;
1400
1401 case TOK_ASM_c_fld:
1402 case TOK_ASM_c_flw:
1403 case TOK_ASM_c_fsd:
1404 case TOK_ASM_c_fsw:
1405 case TOK_ASM_c_ld:
1406 case TOK_ASM_c_lw:
1407 case TOK_ASM_c_sd:
1408 case TOK_ASM_c_sw:
1409 asm_ternary_opcode(s1, token);
1410 return;
1411
1412 /* pseudoinstructions */
1413 case TOK_ASM_nop:
1414 case TOK_ASM_ret:
1415 asm_nullary_opcode(s1, token);
1416 return;
1417
1418 case TOK_ASM_jr:
1419 case TOK_ASM_call:
1420 case TOK_ASM_tail:
1421 asm_unary_opcode(s1, token);
1422 return;
1423
1424 case TOK_ASM_la:
1425 case TOK_ASM_lla:
1426 case TOK_ASM_li:
1427 case TOK_ASM_jump:
1428 case TOK_ASM_seqz:
1429 case TOK_ASM_snez:
1430 case TOK_ASM_sltz:
1431 case TOK_ASM_sgtz:
1432 case TOK_ASM_mv:
1433 case TOK_ASM_not:
1434 case TOK_ASM_neg:
1435 case TOK_ASM_negw:
1436 asm_binary_opcode(s1, token);
1437 return;
1438
1439 case TOK_ASM_bnez:
1440 case TOK_ASM_beqz:
1441 case TOK_ASM_blez:
1442 case TOK_ASM_bgez:
1443 case TOK_ASM_bltz:
1444 case TOK_ASM_bgtz:
1445 asm_branch_opcode(s1, token, 2);
1446 return;
1447
1448 case TOK_ASM_bgt:
1449 case TOK_ASM_bgtu:
1450 case TOK_ASM_ble:
1451 case TOK_ASM_bleu:
1452 asm_branch_opcode(s1, token, 3);
1453 return;
1454
1455 /* Atomic operations */
1456 case TOK_ASM_lr_w:
1457 case TOK_ASM_lr_w_aq:
1458 case TOK_ASM_lr_w_rl:
1459 case TOK_ASM_lr_w_aqrl:
1460 case TOK_ASM_lr_d:
1461 case TOK_ASM_lr_d_aq:
1462 case TOK_ASM_lr_d_rl:
1463 case TOK_ASM_lr_d_aqrl:
1464 case TOK_ASM_sc_w:
1465 case TOK_ASM_sc_w_aq:
1466 case TOK_ASM_sc_w_rl:
1467 case TOK_ASM_sc_w_aqrl:
1468 case TOK_ASM_sc_d:
1469 case TOK_ASM_sc_d_aq:
1470 case TOK_ASM_sc_d_rl:
1471 case TOK_ASM_sc_d_aqrl:
1472 asm_atomic_opcode(s1, token);
1473 break;
1474
1475 default:
1476 expect("known instruction");
1477 }
1478 }
1479
1480 static int asm_parse_csrvar(int t)
1481 {
1482 switch (t) {
1483 case TOK_ASM_cycle:
1484 return 0xc00;
1485 case TOK_ASM_fcsr:
1486 return 3;
1487 case TOK_ASM_fflags:
1488 return 1;
1489 case TOK_ASM_frm:
1490 return 2;
1491 case TOK_ASM_instret:
1492 return 0xc02;
1493 case TOK_ASM_time:
1494 return 0xc01;
1495 case TOK_ASM_cycleh:
1496 return 0xc80;
1497 case TOK_ASM_instreth:
1498 return 0xc82;
1499 case TOK_ASM_timeh:
1500 return 0xc81;
1501 default:
1502 return -1;
1503 }
1504 }
1505
1506 ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier)
1507 {
1508 int r, reg, val;
1509
1510 r = sv->r;
1511 if ((r & VT_VALMASK) == VT_CONST) {
1512 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n' &&
1513 modifier != 'P') {
1514 //cstr_ccat(add_str, '#');
1515 }
1516 if (r & VT_SYM) {
1517 const char *name = get_tok_str(sv->sym->v, NULL);
1518 if (sv->sym->v >= SYM_FIRST_ANOM) {
1519 /* In case of anonymous symbols ("L.42", used
1520 for static data labels) we can't find them
1521 in the C symbol table when later looking up
1522 this name. So enter them now into the asm label
1523 list when we still know the symbol. */
1524 get_asm_sym(tok_alloc(name, strlen(name))->tok, sv->sym);
1525 }
1526 if (tcc_state->leading_underscore)
1527 cstr_ccat(add_str, '_');
1528 cstr_cat(add_str, name, -1);
1529 if ((uint32_t) sv->c.i == 0)
1530 goto no_offset;
1531 cstr_ccat(add_str, '+');
1532 }
1533 val = sv->c.i;
1534 if (modifier == 'n')
1535 val = -val;
1536 if (modifier == 'z' && sv->c.i == 0) {
1537 cstr_cat(add_str, "zero", -1);
1538 } else {
1539 cstr_printf(add_str, "%d", (int) sv->c.i);
1540 }
1541 no_offset:;
1542 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1543 cstr_printf(add_str, "%d", (int) sv->c.i);
1544 } else if (r & VT_LVAL) {
1545 reg = r & VT_VALMASK;
1546 if (reg >= VT_CONST)
1547 tcc_internal_error("");
1548 if ((sv->type.t & VT_BTYPE) == VT_FLOAT ||
1549 (sv->type.t & VT_BTYPE) == VT_DOUBLE) {
1550 /* floating point register */
1551 reg = TOK_ASM_f0 + reg;
1552 } else {
1553 /* general purpose register */
1554 reg = TOK_ASM_x0 + reg;
1555 }
1556 cstr_cat(add_str, get_tok_str(reg, NULL), -1);
1557 } else {
1558 /* register case */
1559 reg = r & VT_VALMASK;
1560 if (reg >= VT_CONST)
1561 tcc_internal_error("");
1562 if ((sv->type.t & VT_BTYPE) == VT_FLOAT ||
1563 (sv->type.t & VT_BTYPE) == VT_DOUBLE) {
1564 /* floating point register */
1565 reg = TOK_ASM_f0 + reg;
1566 } else {
1567 /* general purpose register */
1568 reg = TOK_ASM_x0 + reg;
1569 }
1570 cstr_cat(add_str, get_tok_str(reg, NULL), -1);
1571 }
1572 }
1573
1574 /* TCC does not use RISC-V register numbers internally, it uses 0-8 for
1575 * integers and 8-16 for floats instead */
1576 static int tcc_ireg(int r){
1577 return REG_VALUE(r) - 10;
1578 }
1579 static int tcc_freg(int r){
1580 return REG_VALUE(r) - 10 + 8;
1581 }
1582
1583 /* generate prolog and epilog code for asm statement */
1584 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1585 int nb_outputs, int is_output,
1586 uint8_t *clobber_regs,
1587 int out_reg)
1588 {
1589 uint8_t regs_allocated[NB_ASM_REGS];
1590 ASMOperand *op;
1591 int i, reg;
1592
1593 static const uint8_t reg_saved[] = {
1594 // General purpose regs
1595 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
1596 // Float regs
1597 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59
1598 };
1599
1600 /* mark all used registers */
1601 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1602 for(i = 0; i < nb_operands; i++) {
1603 op = &operands[i];
1604 if (op->reg >= 0) {
1605 regs_allocated[op->reg] = 1;
1606 }
1607 }
1608
1609 if(!is_output) {
1610 /* generate reg save code */
1611 for(i = 0; i < sizeof(reg_saved)/sizeof(reg_saved[0]); i++) {
1612 reg = reg_saved[i];
1613 if (regs_allocated[reg]) {
1614 /* push */
1615 /* addi sp, sp, -offset */
1616 gen_le32((4 << 2) | 3 |
1617 ENCODE_RD(2) | ENCODE_RS1(2) | -8 << 20);
1618 if (REG_IS_FLOAT(reg)){
1619 /* fsd reg, offset(sp) */
1620 gen_le32( 0x27 | (3 << 12) |
1621 ENCODE_RS2(reg) | ENCODE_RS1(2) );
1622 } else {
1623 /* sd reg, offset(sp) */
1624 gen_le32((0x8 << 2) | 3 | (3 << 12) |
1625 ENCODE_RS2(reg) | ENCODE_RS1(2) );
1626 }
1627 }
1628 }
1629
1630 /* generate load code */
1631 for(i = 0; i < nb_operands; i++) {
1632 op = &operands[i];
1633 if (op->reg >= 0) {
1634 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1635 op->is_memory) {
1636 /* memory reference case (for both input and
1637 output cases) */
1638 SValue sv;
1639 sv = *op->vt;
1640 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL | VT_LVAL;
1641 sv.type.t = VT_PTR;
1642 load(tcc_ireg(op->reg), &sv);
1643 } else if (i >= nb_outputs || op->is_rw) {
1644 /* load value in register */
1645 if ((op->vt->type.t & VT_BTYPE) == VT_FLOAT ||
1646 (op->vt->type.t & VT_BTYPE) == VT_DOUBLE) {
1647 load(tcc_freg(op->reg), op->vt);
1648 } else {
1649 load(tcc_ireg(op->reg), op->vt);
1650 }
1651 if (op->is_llong) {
1652 tcc_error("long long not implemented");
1653 }
1654 }
1655 }
1656 }
1657 } else {
1658 /* generate save code */
1659 for(i = 0 ; i < nb_outputs; i++) {
1660 op = &operands[i];
1661 if (op->reg >= 0) {
1662 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1663 if (!op->is_memory) {
1664 SValue sv;
1665 sv = *op->vt;
1666 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1667 sv.type.t = VT_PTR;
1668 load(tcc_ireg(out_reg), &sv);
1669
1670 sv = *op->vt;
1671 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1672 store(tcc_ireg(op->reg), &sv);
1673 }
1674 } else {
1675 if ((op->vt->type.t & VT_BTYPE) == VT_FLOAT ||
1676 (op->vt->type.t & VT_BTYPE) == VT_DOUBLE) {
1677 store(tcc_freg(op->reg), op->vt);
1678 } else {
1679 store(tcc_ireg(op->reg), op->vt);
1680 }
1681 if (op->is_llong) {
1682 tcc_error("long long not implemented");
1683 }
1684 }
1685 }
1686 }
1687 /* generate reg restore code for floating point registers */
1688 for(i = sizeof(reg_saved)/sizeof(reg_saved[0]) - 1; i >= 0; i--) {
1689 reg = reg_saved[i];
1690 if (regs_allocated[reg]) {
1691 /* pop */
1692 if (REG_IS_FLOAT(reg)){
1693 /* fld reg, offset(sp) */
1694 gen_le32(7 | (3 << 12) |
1695 ENCODE_RD(reg) | ENCODE_RS1(2) | 0);
1696 } else {
1697 /* ld reg, offset(sp) */
1698 gen_le32(3 | (3 << 12) |
1699 ENCODE_RD(reg) | ENCODE_RS1(2) | 0);
1700 }
1701 /* addi sp, sp, offset */
1702 gen_le32((4 << 2) | 3 |
1703 ENCODE_RD(2) | ENCODE_RS1(2) | 8 << 20);
1704 }
1705 }
1706 }
1707 }
1708
1709 /* return the constraint priority (we allocate first the lowest
1710 numbered constraints) */
1711 static inline int constraint_priority(const char *str)
1712 {
1713 // TODO: How is this chosen??
1714 int priority, c, pr;
1715
1716 /* we take the lowest priority */
1717 priority = 0;
1718 for(;;) {
1719 c = *str;
1720 if (c == '\0')
1721 break;
1722 str++;
1723 switch(c) {
1724 case 'A': // address that is held in a general-purpose register.
1725 case 'S': // constraint that matches an absolute symbolic address.
1726 case 'f': // register [float]
1727 case 'r': // register [general]
1728 case 'p': // valid memory address for load,store [general]
1729 pr = 3;
1730 break;
1731 case 'I': // 12 bit signed immedate
1732 case 'i': // immediate integer operand, including symbolic constants [general]
1733 case 'm': // memory operand [general]
1734 case 'g': // general-purpose-register, memory, immediate integer [general]
1735 pr = 4;
1736 break;
1737 case 'v':
1738 tcc_error("unimp: constraint '%c'", c);
1739 default:
1740 tcc_error("unknown constraint '%d'", c);
1741 }
1742 if (pr > priority)
1743 priority = pr;
1744 }
1745 return priority;
1746 }
1747
1748 static const char *skip_constraint_modifiers(const char *p)
1749 {
1750 /* Constraint modifier:
1751 = Operand is written to by this instruction
1752 + Operand is both read and written to by this instruction
1753 % Instruction is commutative for this operand and the following operand.
1754
1755 Per-alternative constraint modifier:
1756 & Operand is clobbered before the instruction is done using the input operands
1757 */
1758 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1759 p++;
1760 return p;
1761 }
1762
1763 #define REG_OUT_MASK 0x01
1764 #define REG_IN_MASK 0x02
1765
1766 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1767
1768 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1769 int nb_operands, int nb_outputs,
1770 const uint8_t *clobber_regs,
1771 int *pout_reg)
1772 {
1773 /* TODO: Simple constraints
1774 whitespace ignored
1775 o memory operand that is offsetable
1776 V memory but not offsetable
1777 < memory operand with autodecrement addressing is allowed. Restrictions apply.
1778 > memory operand with autoincrement addressing is allowed. Restrictions apply.
1779 n immediate integer operand with a known numeric value
1780 E immediate floating operand (const_double) is allowed, but only if target=host
1781 F immediate floating operand (const_double or const_vector) is allowed
1782 s immediate integer operand whose value is not an explicit integer
1783 X any operand whatsoever
1784 0...9 (postfix); (can also be more than 1 digit number); an operand that matches the specified operand number is allowed
1785 */
1786
1787 /* TODO: RISCV constraints
1788 J The integer 0.
1789 K A 5-bit unsigned immediate for CSR access instructions.
1790 A An address that is held in a general-purpose register.
1791 S A constraint that matches an absolute symbolic address.
1792 vr A vector register (if available)..
1793 vd A vector register, excluding v0 (if available).
1794 vm A vector register, only v0 (if available).
1795 */
1796 ASMOperand *op;
1797 int sorted_op[MAX_ASM_OPERANDS];
1798 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1799 const char *str;
1800 uint8_t regs_allocated[NB_ASM_REGS];
1801
1802 /* init fields */
1803 for (i = 0; i < nb_operands; i++) {
1804 op = &operands[i];
1805 op->input_index = -1;
1806 op->ref_index = -1;
1807 op->reg = -1;
1808 op->is_memory = 0;
1809 op->is_rw = 0;
1810 }
1811 /* compute constraint priority and evaluate references to output
1812 constraints if input constraints */
1813 for (i = 0; i < nb_operands; i++) {
1814 op = &operands[i];
1815 str = op->constraint;
1816 str = skip_constraint_modifiers(str);
1817 if (isnum(*str) || *str == '[') {
1818 /* this is a reference to another constraint */
1819 k = find_constraint(operands, nb_operands, str, NULL);
1820 if ((unsigned) k >= i || i < nb_outputs)
1821 tcc_error("invalid reference in constraint %d ('%s')",
1822 i, str);
1823 op->ref_index = k;
1824 if (operands[k].input_index >= 0)
1825 tcc_error("cannot reference twice the same operand");
1826 operands[k].input_index = i;
1827 op->priority = 5;
1828 } else if ((op->vt->r & VT_VALMASK) == VT_LOCAL
1829 && op->vt->sym
1830 && (reg = op->vt->sym->r & VT_VALMASK) < VT_CONST) {
1831 op->priority = 1;
1832 op->reg = reg;
1833 } else {
1834 op->priority = constraint_priority(str);
1835 }
1836 }
1837
1838 /* sort operands according to their priority */
1839 for (i = 0; i < nb_operands; i++)
1840 sorted_op[i] = i;
1841 for (i = 0; i < nb_operands - 1; i++) {
1842 for (j = i + 1; j < nb_operands; j++) {
1843 p1 = operands[sorted_op[i]].priority;
1844 p2 = operands[sorted_op[j]].priority;
1845 if (p2 < p1) {
1846 tmp = sorted_op[i];
1847 sorted_op[i] = sorted_op[j];
1848 sorted_op[j] = tmp;
1849 }
1850 }
1851 }
1852
1853 for (i = 0; i < NB_ASM_REGS; i++) {
1854 if (clobber_regs[i])
1855 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1856 else
1857 regs_allocated[i] = 0;
1858 }
1859
1860 /* allocate registers and generate corresponding asm moves */
1861 for (i = 0; i < nb_operands; i++) {
1862 j = sorted_op[i];
1863 op = &operands[j];
1864 str = op->constraint;
1865 /* no need to allocate references */
1866 if (op->ref_index >= 0)
1867 continue;
1868 /* select if register is used for output, input or both */
1869 if (op->input_index >= 0) {
1870 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1871 } else if (j < nb_outputs) {
1872 reg_mask = REG_OUT_MASK;
1873 } else {
1874 reg_mask = REG_IN_MASK;
1875 }
1876 if (op->reg >= 0) {
1877 if (is_reg_allocated(op->reg))
1878 tcc_error
1879 ("asm regvar requests register that's taken already");
1880 reg = op->reg;
1881 }
1882 try_next:
1883 c = *str++;
1884 switch (c) {
1885 case '=': // Operand is written-to
1886 goto try_next;
1887 case '+': // Operand is both READ and written-to
1888 op->is_rw = 1;
1889 /* FALL THRU */
1890 case '&': // Operand is clobbered before the instruction is done using the input operands
1891 if (j >= nb_outputs)
1892 tcc_error("'%c' modifier can only be applied to outputs", c);
1893 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1894 goto try_next;
1895 case 'r': // general-purpose register
1896 case 'p': // loadable/storable address
1897 /* any general register */
1898 /* From a0 to a7 */
1899 if ((reg = op->reg) >= 0)
1900 goto reg_found;
1901 else for (reg = 10; reg <= 18; reg++) {
1902 if (!is_reg_allocated(reg))
1903 goto reg_found;
1904 }
1905 goto try_next;
1906 reg_found:
1907 /* now we can reload in the register */
1908 op->is_llong = 0;
1909 op->reg = reg;
1910 regs_allocated[reg] |= reg_mask;
1911 break;
1912 case 'f': // floating pont register
1913 /* floating point register */
1914 /* From fa0 to fa7 */
1915 if ((reg = op->reg) >= 0)
1916 goto reg_found;
1917 else for (reg = 42; reg <= 50; reg++) {
1918 if (!is_reg_allocated(reg))
1919 goto reg_found;
1920 }
1921 goto try_next;
1922 case 'I': // I-Type 12 bit signed immediate
1923 case 'i': // immediate integer operand, including symbolic constants
1924 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1925 goto try_next;
1926 break;
1927 case 'm': // memory operand
1928 case 'g': // any register
1929 /* nothing special to do because the operand is already in
1930 memory, except if the pointer itself is stored in a
1931 memory variable (VT_LLOCAL case) */
1932 /* XXX: fix constant case */
1933 /* if it is a reference to a memory zone, it must lie
1934 in a register, so we reserve the register in the
1935 input registers and a load will be generated
1936 later */
1937 if (j < nb_outputs || c == 'm') {
1938 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1939 /* any general register: from a0 to a7 */
1940 for (reg = 10; reg <= 18; reg++) {
1941 if (!(regs_allocated[reg] & REG_IN_MASK))
1942 goto reg_found1;
1943 }
1944 goto try_next;
1945 reg_found1:
1946 /* now we can reload in the register */
1947 regs_allocated[reg] |= REG_IN_MASK;
1948 op->reg = reg;
1949 op->is_memory = 1;
1950 }
1951 }
1952 break;
1953 default:
1954 tcc_error("asm constraint %d ('%s') could not be satisfied",
1955 j, op->constraint);
1956 break;
1957 }
1958 /* if a reference is present for that operand, we assign it too */
1959 if (op->input_index >= 0) {
1960 operands[op->input_index].reg = op->reg;
1961 operands[op->input_index].is_llong = op->is_llong;
1962 }
1963 }
1964
1965 /* compute out_reg. It is used to store outputs registers to memory
1966 locations references by pointers (VT_LLOCAL case) */
1967 *pout_reg = -1;
1968 for (i = 0; i < nb_operands; i++) {
1969 op = &operands[i];
1970 if (op->reg >= 0 &&
1971 (op->vt->r & VT_VALMASK) == VT_LLOCAL && !op->is_memory) {
1972 if (REG_IS_FLOAT(op->reg)){
1973 /* From fa0 to fa7 */
1974 for (reg = 42; reg <= 50; reg++) {
1975 if (!(regs_allocated[reg] & REG_OUT_MASK))
1976 goto reg_found2;
1977 }
1978 } else {
1979 /* From a0 to a7 */
1980 for (reg = 10; reg <= 18; reg++) {
1981 if (!(regs_allocated[reg] & REG_OUT_MASK))
1982 goto reg_found2;
1983 }
1984 }
1985 tcc_error("could not find free output register for reloading");
1986 reg_found2:
1987 *pout_reg = reg;
1988 break;
1989 }
1990 }
1991
1992 /* print sorted constraints */
1993 #ifdef ASM_DEBUG
1994 for (i = 0; i < nb_operands; i++) {
1995 j = sorted_op[i];
1996 op = &operands[j];
1997 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1998 j,
1999 op->id ? get_tok_str(op->id, NULL) : "",
2000 op->constraint, op->vt->r, op->reg);
2001 }
2002 if (*pout_reg >= 0)
2003 printf("out_reg=%d\n", *pout_reg);
2004 #endif
2005 }
2006
2007 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
2008 {
2009 int reg;
2010 TokenSym *ts;
2011
2012 if (!strcmp(str, "memory") ||
2013 !strcmp(str, "cc") ||
2014 !strcmp(str, "flags"))
2015 return;
2016 ts = tok_alloc(str, strlen(str));
2017 reg = asm_parse_regvar(ts->tok);
2018 if (reg == -1) {
2019 tcc_error("invalid clobber register '%s'", str);
2020 }
2021 clobber_regs[reg] = 1;
2022 }
2023
2024 ST_FUNC int asm_parse_regvar (int t)
2025 {
2026 /* PC register not implemented */
2027 if (t >= TOK_ASM_pc || t < TOK_ASM_x0)
2028 return -1;
2029
2030 if (t < TOK_ASM_f0)
2031 return t - TOK_ASM_x0;
2032
2033 if (t < TOK_ASM_zero)
2034 return t - TOK_ASM_f0 + 32; // Use higher 32 for floating point
2035
2036 /* ABI mnemonic */
2037 if (t < TOK_ASM_ft0)
2038 return t - TOK_ASM_zero;
2039
2040 return t - TOK_ASM_ft0 + 32; // Use higher 32 for floating point
2041 }
2042
2043 /*************************************************************/
2044 /* C extension */
2045
2046 /* caller: Add funct6, funct2 into opcode */
2047 static void asm_emit_ca(int token, uint16_t opcode, const Operand *rd, const Operand *rs2)
2048 {
2049 uint8_t dst, src;
2050
2051 if (rd->type != OP_REG) {
2052 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2053 }
2054
2055 if (rs2->type != OP_REG) {
2056 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2057 }
2058
2059 /* subtract index of x8 */
2060 dst = rd->reg - 8;
2061 src = rs2->reg - 8;
2062
2063 /* only registers {x,f}8 to {x,f}15 are valid (3-bit) */
2064 if (dst > 7) {
2065 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2066 }
2067
2068 if (src > 7) {
2069 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2070 }
2071
2072 /* CA-type instruction:
2073 15...10 funct6
2074 9...7 rd'/rs1'
2075 6..5 funct2
2076 4...2 rs2'
2077 1...0 opcode */
2078
2079 gen_le16(opcode | C_ENCODE_RS2(src) | C_ENCODE_RS1(dst));
2080 }
2081
2082 static void asm_emit_cb(int token, uint16_t opcode, const Operand *rs1, const Operand *imm)
2083 {
2084 uint32_t offset;
2085 uint8_t src;
2086
2087 if (rs1->type != OP_REG) {
2088 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2089 }
2090
2091 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2092 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2093 }
2094
2095 offset = imm->e.v;
2096
2097 if (offset & 1) {
2098 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token, NULL));
2099 }
2100
2101 src = rs1->reg - 8;
2102
2103 if (src > 7) {
2104 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2105 }
2106
2107 /* CB-type instruction:
2108 15...13 funct3
2109 12...10 offset
2110 9..7 rs1'
2111 6...2 offset
2112 1...0 opcode */
2113
2114 /* non-branch also using CB:
2115 15...13 funct3
2116 12 imm
2117 11..10 funct2
2118 9...7 rd'/rs1'
2119 6..2 imm
2120 1...0 opcode */
2121
2122 switch (token) {
2123 case TOK_ASM_c_beqz:
2124 case TOK_ASM_c_bnez:
2125 gen_le16(opcode | C_ENCODE_RS1(src) | ((NTH_BIT(offset, 5) | (((offset >> 1) & 3) << 1) | (((offset >> 6) & 3) << 3)) << 2) | ((((offset >> 3) & 3) | NTH_BIT(offset, 8)) << 10));
2126 return;
2127 default:
2128 gen_le16(opcode | C_ENCODE_RS1(src) | ((offset & 0x1f) << 2) | (NTH_BIT(offset, 5) << 12));
2129 return;
2130 }
2131 }
2132
2133 static void asm_emit_ci(int token, uint16_t opcode, const Operand *rd, const Operand *imm)
2134 {
2135 uint32_t immediate;
2136
2137 if (rd->type != OP_REG) {
2138 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2139 }
2140
2141 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2142 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2143 }
2144
2145 immediate = imm->e.v;
2146
2147 /* CI-type instruction:
2148 15...13 funct3
2149 12 imm
2150 11...7 rd/rs1
2151 6...2 imm
2152 1...0 opcode */
2153
2154 switch (token) {
2155 case TOK_ASM_c_addi:
2156 case TOK_ASM_c_addiw:
2157 case TOK_ASM_c_li:
2158 case TOK_ASM_c_slli:
2159 gen_le16(opcode | ((immediate & 0x1f) << 2) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 5) << 12));
2160 return;
2161 case TOK_ASM_c_addi16sp:
2162 gen_le16(opcode | NTH_BIT(immediate, 5) << 2 | (((immediate >> 7) & 3) << 3) | NTH_BIT(immediate, 6) << 5 | NTH_BIT(immediate, 4) << 6 | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 9) << 12));
2163 return;
2164 case TOK_ASM_c_lui:
2165 gen_le16(opcode | (((immediate >> 12) & 0x1f) << 2) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 17) << 12));
2166 return;
2167 case TOK_ASM_c_fldsp:
2168 case TOK_ASM_c_ldsp:
2169 gen_le16(opcode | (((immediate >> 6) & 7) << 2) | (((immediate >> 3) & 2) << 5) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 5) << 12));
2170 return;
2171 case TOK_ASM_c_flwsp:
2172 case TOK_ASM_c_lwsp:
2173 gen_le16(opcode | (((immediate >> 6) & 3) << 2) | (((immediate >> 2) & 7) << 4) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 5) << 12));
2174 return;
2175 case TOK_ASM_c_nop:
2176 gen_le16(opcode);
2177 return;
2178 default:
2179 expect("known instruction");
2180 }
2181 }
2182
2183 /* caller: Add funct3 into opcode */
2184 static void asm_emit_ciw(int token, uint16_t opcode, const Operand *rd, const Operand *imm)
2185 {
2186 uint32_t nzuimm;
2187 uint8_t dst;
2188
2189 if (rd->type != OP_REG) {
2190 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2191 }
2192
2193 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2194 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2195 }
2196
2197 dst = rd->reg - 8;
2198
2199 if (dst > 7) {
2200 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2201 }
2202
2203 nzuimm = imm->e.v;
2204
2205 if (nzuimm > 0x3fc) {
2206 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0x3ff", get_tok_str(token, NULL));
2207 }
2208
2209 if (nzuimm & 3) {
2210 tcc_error("'%s': Expected source operand that is a non-zero immediate value divisible by 4", get_tok_str(token, NULL));
2211 }
2212
2213 /* CIW-type instruction:
2214 15...13 funct3
2215 12...5 imm
2216 4...2 rd'
2217 1...0 opcode */
2218
2219 gen_le16(opcode | ENCODE_RS2(rd->reg) | ((NTH_BIT(nzuimm, 3) | (NTH_BIT(nzuimm, 2) << 1) | (((nzuimm >> 6) & 0xf) << 2) | (((nzuimm >> 4) & 3) << 6)) << 5));
2220 }
2221
2222 /* caller: Add funct3 into opcode */
2223 static void asm_emit_cj(int token, uint16_t opcode, const Operand *imm)
2224 {
2225 uint32_t offset;
2226
2227 /* +-2 KiB range */
2228 if (imm->type != OP_IM12S) {
2229 tcc_error("'%s': Expected source operand that is a 12-bit immediate value", get_tok_str(token, NULL));
2230 }
2231
2232 offset = imm->e.v;
2233
2234 if (offset & 1) {
2235 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token, NULL));
2236 }
2237
2238 /* CJ-type instruction:
2239 15...13 funct3
2240 12...2 offset[11|4|9:8|10|6|7|3:1|5]
2241 1...0 opcode */
2242
2243 gen_le16(opcode | (NTH_BIT(offset, 5) << 2) | (((offset >> 1) & 7) << 3) | (NTH_BIT(offset, 7) << 6) | (NTH_BIT(offset, 6) << 7) | (NTH_BIT(offset, 10) << 8) | (((offset >> 8) & 3) << 9) | (NTH_BIT(offset, 4) << 11) | (NTH_BIT(offset, 11) << 12));
2244 }
2245
2246 /* caller: Add funct3 into opcode */
2247 static void asm_emit_cl(int token, uint16_t opcode, const Operand *rd, const Operand *rs1, const Operand *imm)
2248 {
2249 uint32_t offset;
2250 uint8_t dst, src;
2251
2252 if (rd->type != OP_REG) {
2253 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2254 }
2255
2256 if (rs1->type != OP_REG) {
2257 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2258 }
2259
2260 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2261 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2262 }
2263
2264 dst = rd->reg - 8;
2265 src = rs1->reg - 8;
2266
2267 if (dst > 7) {
2268 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2269 }
2270
2271 if (src > 7) {
2272 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2273 }
2274
2275 offset = imm->e.v;
2276
2277 if (offset > 0xff) {
2278 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token, NULL));
2279 }
2280
2281 if (offset & 3) {
2282 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token, NULL));
2283 }
2284
2285 /* CL-type instruction:
2286 15...13 funct3
2287 12...10 imm
2288 9...7 rs1'
2289 6...5 imm
2290 4...2 rd'
2291 1...0 opcode */
2292
2293 switch (token) {
2294 /* imm variant 1 */
2295 case TOK_ASM_c_flw:
2296 case TOK_ASM_c_lw:
2297 gen_le16(opcode | C_ENCODE_RS2(dst) | C_ENCODE_RS1(src) | (NTH_BIT(offset, 6) << 5) | (NTH_BIT(offset, 2) << 6) | (((offset >> 3) & 7) << 10));
2298 return;
2299 /* imm variant 2 */
2300 case TOK_ASM_c_fld:
2301 case TOK_ASM_c_ld:
2302 gen_le16(opcode | C_ENCODE_RS2(dst) | C_ENCODE_RS1(src) | (((offset >> 6) & 3) << 5) | (((offset >> 3) & 7) << 10));
2303 return;
2304 default:
2305 expect("known instruction");
2306 }
2307 }
2308
2309 /* caller: Add funct4 into opcode */
2310 static void asm_emit_cr(int token, uint16_t opcode, const Operand *rd, const Operand *rs2)
2311 {
2312 if (rd->type != OP_REG) {
2313 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2314 }
2315
2316 if (rs2->type != OP_REG) {
2317 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2318 }
2319
2320 /* CR-type instruction:
2321 15...12 funct4
2322 11..7 rd/rs1
2323 6...2 rs2
2324 1...0 opcode */
2325
2326 gen_le16(opcode | C_ENCODE_RS1(rd->reg) | C_ENCODE_RS2(rs2->reg));
2327 }
2328
2329 /* caller: Add funct3 into opcode */
2330 static void asm_emit_cs(int token, uint16_t opcode, const Operand *rs2, const Operand *rs1, const Operand *imm)
2331 {
2332 uint32_t offset;
2333 uint8_t base, src;
2334
2335 if (rs2->type != OP_REG) {
2336 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2337 }
2338
2339 if (rs1->type != OP_REG) {
2340 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2341 }
2342
2343 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2344 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2345 }
2346
2347 base = rs1->reg - 8;
2348 src = rs2->reg - 8;
2349
2350 if (base > 7) {
2351 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2352 }
2353
2354 if (src > 7) {
2355 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2356 }
2357
2358 offset = imm->e.v;
2359
2360 if (offset > 0xff) {
2361 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token, NULL));
2362 }
2363
2364 if (offset & 3) {
2365 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token, NULL));
2366 }
2367
2368 /* CS-type instruction:
2369 15...13 funct3
2370 12...10 imm
2371 9...7 rs1'
2372 6...5 imm
2373 4...2 rs2'
2374 1...0 opcode */
2375 switch (token) {
2376 /* imm variant 1 */
2377 case TOK_ASM_c_fsw:
2378 case TOK_ASM_c_sw:
2379 gen_le16(opcode | C_ENCODE_RS2(base) | C_ENCODE_RS1(src) | (NTH_BIT(offset, 6) << 5) | (NTH_BIT(offset, 2) << 6) | (((offset >> 3) & 7) << 10));
2380 return;
2381 /* imm variant 2 */
2382 case TOK_ASM_c_fsd:
2383 case TOK_ASM_c_sd:
2384 gen_le16(opcode | C_ENCODE_RS2(base) | C_ENCODE_RS1(src) | (((offset >> 6) & 3) << 5) | (((offset >> 3) & 7) << 10));
2385 return;
2386 default:
2387 expect("known instruction");
2388 }
2389 }
2390
2391 /* caller: Add funct3 into opcode */
2392 static void asm_emit_css(int token, uint16_t opcode, const Operand *rs2, const Operand *imm)
2393 {
2394 uint32_t offset;
2395
2396 if (rs2->type != OP_REG) {
2397 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2398 }
2399
2400 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2401 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2402 }
2403
2404 offset = imm->e.v;
2405
2406 if (offset > 0xff) {
2407 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token, NULL));
2408 }
2409
2410 if (offset & 3) {
2411 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token, NULL));
2412 }
2413
2414 /* CSS-type instruction:
2415 15...13 funct3
2416 12...7 imm
2417 6...2 rs2
2418 1...0 opcode */
2419
2420 switch (token) {
2421 /* imm variant 1 */
2422 case TOK_ASM_c_fswsp:
2423 case TOK_ASM_c_swsp:
2424 gen_le16(opcode | ENCODE_RS2(rs2->reg) | (((offset >> 6) & 3) << 7) | (((offset >> 2) & 0xf) << 9));
2425 return;
2426 /* imm variant 2 */
2427 case TOK_ASM_c_fsdsp:
2428 case TOK_ASM_c_sdsp:
2429 gen_le16(opcode | ENCODE_RS2(rs2->reg) | (((offset >> 6) & 7) << 7) | (((offset >> 3) & 7) << 10));
2430 return;
2431 default:
2432 expect("known instruction");
2433 }
2434 }
2435
2436 /*************************************************************/
2437 #endif /* ndef TARGET_DEFS_ONLY */
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