2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "i386-asm-config.h"
23 #define MAX_OPERANDS 3
25 typedef struct ASMInstr
{
29 #define OPC_JMP 0x01 /* jmp operand */
30 #define OPC_B 0x02 /* only used zith OPC_WL */
31 #define OPC_WL 0x04 /* accepts w, l or no suffix */
32 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
33 #define OPC_REG 0x08 /* register is added to opcode */
34 #define OPC_MODRM 0x10 /* modrm encoding */
35 #define OPC_FWAIT 0x20 /* add fwait opcode */
36 #define OPC_TEST 0x40 /* test opcodes */
37 #define OPC_SHIFT 0x80 /* shift opcodes */
38 #define OPC_D16 0x0100 /* generate data16 prefix */
39 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
40 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
41 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
42 #define OPC_GROUP_SHIFT 13
44 /* in order to compress the operand type, we use specific operands and
46 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
52 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
53 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
60 #define OPT_EAX 14 /* %al, %ax or %eax register */
61 #define OPT_ST0 15 /* %st(0) register */
62 #define OPT_CL 16 /* %cl register */
63 #define OPT_DX 17 /* %dx register */
64 #define OPT_ADDR 18 /* OP_EA with only offset */
65 #define OPT_INDIR 19 /* *(expr) */
68 #define OPT_COMPOSITE_FIRST 20
69 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
70 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
71 #define OPT_REGW 22 /* REG16 | REG32 */
72 #define OPT_IMW 23 /* IM16 | IM32 */
74 /* can be ored with any OPT_xxx */
78 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
81 typedef struct Operand
{
83 #define OP_REG8 (1 << OPT_REG8)
84 #define OP_REG16 (1 << OPT_REG16)
85 #define OP_REG32 (1 << OPT_REG32)
86 #define OP_MMX (1 << OPT_MMX)
87 #define OP_SSE (1 << OPT_SSE)
88 #define OP_CR (1 << OPT_CR)
89 #define OP_TR (1 << OPT_TR)
90 #define OP_DB (1 << OPT_DB)
91 #define OP_SEG (1 << OPT_SEG)
92 #define OP_ST (1 << OPT_ST)
93 #define OP_IM8 (1 << OPT_IM8)
94 #define OP_IM8S (1 << OPT_IM8S)
95 #define OP_IM16 (1 << OPT_IM16)
96 #define OP_IM32 (1 << OPT_IM32)
97 #define OP_EAX (1 << OPT_EAX)
98 #define OP_ST0 (1 << OPT_ST0)
99 #define OP_CL (1 << OPT_CL)
100 #define OP_DX (1 << OPT_DX)
101 #define OP_ADDR (1 << OPT_ADDR)
102 #define OP_INDIR (1 << OPT_INDIR)
104 #define OP_EA 0x40000000
105 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
106 #define OP_IM OP_IM32
107 int8_t reg
; /* register, -1 if none */
108 int8_t reg2
; /* second register, -1 if none */
113 static const uint8_t reg_to_size
[5] = {
122 #define NB_TEST_OPCODES 30
124 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
157 static const uint8_t segment_prefixes
[] = {
166 static const ASMInstr asm_instrs
[] = {
168 #define DEF_ASM_OP0(name, opcode)
169 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
170 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
171 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
172 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
173 #include "i386-asm.h"
179 static const uint16_t op0_codes
[] = {
181 #define DEF_ASM_OP0(x, opcode) opcode,
182 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
183 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
184 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
185 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
186 #include "i386-asm.h"
189 static inline int get_reg_shift(TCCState
*s1
)
193 if (s1
->seg_size
== 16) {
194 error("invalid effective address");
197 v
= asm_int_expr(s1
);
212 expect("1, 2, 4 or 8 constant");
219 static int asm_parse_reg(void)
225 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
226 reg
= tok
- TOK_ASM_eax
;
229 } else if (tok
>= TOK_ASM_ax
&& tok
<= TOK_ASM_di
) {
230 reg
= tok
- TOK_ASM_ax
;
240 static void parse_operand(TCCState
*s1
, Operand
*op
)
254 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
255 reg
= tok
- TOK_ASM_al
;
256 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
258 if ((op
->type
& OP_REG
) && op
->reg
== TREG_EAX
)
260 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_ECX
)
262 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_EDX
)
264 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
266 op
->reg
= tok
- TOK_ASM_dr0
;
267 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
269 op
->reg
= tok
- TOK_ASM_es
;
270 } else if (tok
== TOK_ASM_st
) {
276 if (tok
!= TOK_PPNUM
)
280 if ((unsigned)reg
>= 8 || p
[1] != '\0')
291 error("unknown register");
295 } else if (tok
== '$') {
303 if (op
->e
.v
== (uint8_t)op
->e
.v
)
305 if (op
->e
.v
== (int8_t)op
->e
.v
)
307 if (op
->e
.v
== (uint16_t)op
->e
.v
)
311 /* address(reg,reg2,shift) with all variants */
327 op
->reg
= asm_parse_reg();
332 op
->reg2
= asm_parse_reg();
336 op
->shift
= get_reg_shift(s1
);
341 if (op
->reg
== -1 && op
->reg2
== -1)
353 /* XXX: unify with C code output ? */
354 void gen_expr32(ExprValue
*pe
)
357 greloc(cur_text_section
, pe
->sym
, ind
, R_386_32
);
361 static void gen_expr16(ExprValue
*pe
)
364 greloc(cur_text_section
, pe
->sym
, ind
, R_386_16
);
368 /* XXX: unify with C code output ? */
369 static void gen_disp32(ExprValue
*pe
)
374 if (sym
->r
== cur_text_section
->sh_num
) {
375 /* same section: we can output an absolute value. Note
376 that the TCC compiler behaves differently here because
377 it always outputs a relocation to ease (future) code
378 elimination in the linker */
379 gen_le32(pe
->v
+ sym
->jnext
- ind
- 4);
381 greloc(cur_text_section
, sym
, ind
, R_386_PC32
);
385 /* put an empty PC32 relocation */
386 put_elf_reloc(symtab_section
, cur_text_section
,
392 static void gen_disp16(ExprValue
*pe
)
397 if (sym
->r
== cur_text_section
->sh_num
) {
398 /* same section: we can output an absolute value. Note
399 that the TCC compiler behaves differently here because
400 it always outputs a relocation to ease (future) code
401 elimination in the linker */
402 gen_le16(pe
->v
+ sym
->jnext
- ind
- 2);
404 greloc(cur_text_section
, sym
, ind
, R_386_PC16
);
408 /* put an empty PC32 relocation */
409 put_elf_reloc(symtab_section
, cur_text_section
,
415 /* generate the modrm operand */
416 static inline void asm_modrm(int reg
, Operand
*op
)
418 int mod
, reg1
, reg2
, sib_reg1
;
420 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
421 g(0xc0 + (reg
<< 3) + op
->reg
);
422 } else if (op
->reg
== -1 && op
->reg2
== -1) {
423 /* displacement only */
424 if (tcc_state
->seg_size
== 16) {
425 g(0x06 + (reg
<< 3));
427 } else if (tcc_state
->seg_size
== 32) {
428 g(0x05 + (reg
<< 3));
433 /* fist compute displacement encoding */
434 if (sib_reg1
== -1) {
437 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
439 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
444 /* compute if sib byte needed */
448 if (tcc_state
->seg_size
== 32) {
449 g(mod
+ (reg
<< 3) + reg1
);
454 reg2
= 4; /* indicate no index */
455 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
457 } else if (tcc_state
->seg_size
== 16) {
458 /* edi = 7, esi = 6 --> di = 5, si = 4 */
459 if ((reg1
== 6) || (reg1
== 7)) {
461 /* ebx = 3 --> bx = 7 */
462 } else if (reg1
== 3) {
464 /* o32 = 5 --> o16 = 6 */
465 } else if (reg1
== 5) {
467 /* sib not valid in 16-bit mode */
468 } else if (reg1
== 4) {
470 /* bp + si + offset */
471 if ((sib_reg1
== 5) && (reg2
== 6)) {
473 /* bp + di + offset */
474 } else if ((sib_reg1
== 5) && (reg2
== 7)) {
476 /* bx + si + offset */
477 } else if ((sib_reg1
== 3) && (reg2
== 6)) {
479 /* bx + di + offset */
480 } else if ((sib_reg1
== 3) && (reg2
== 7)) {
483 error("invalid effective address");
488 error("invalid register");
490 g(mod
+ (reg
<< 3) + reg1
);
496 } else if (mod
== 0x80 || op
->reg
== -1) {
497 if (tcc_state
->seg_size
== 16)
499 else if (tcc_state
->seg_size
== 32)
505 void asm_opcode(TCCState
*s1
, int opcode
)
508 int i
, modrm_index
, reg
, v
, op1
, is_short_jmp
, seg_prefix
;
510 Operand ops
[MAX_OPERANDS
], *pop
;
511 int op_type
[3]; /* decoded op type */
514 static int addr32
= 0, data32
= 0;
521 if (tok
== ';' || tok
== TOK_LINEFEED
)
523 if (nb_ops
>= MAX_OPERANDS
) {
524 error("incorrect number of operands");
526 parse_operand(s1
, pop
);
528 if (pop
->type
!= OP_SEG
|| seg_prefix
) {
530 error("incorrect prefix");
532 seg_prefix
= segment_prefixes
[pop
->reg
];
534 parse_operand(s1
, pop
);
536 if (!(pop
->type
& OP_EA
)) {
537 error("segment prefix must be followed by memory reference");
549 s
= 0; /* avoid warning */
551 /* optimize matching by using a lookup table (no hashing is needed
553 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
555 if (pa
->instr_type
& OPC_FARITH
) {
556 v
= opcode
- pa
->sym
;
557 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
559 } else if (pa
->instr_type
& OPC_ARITH
) {
560 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8 * 4))
563 } else if (pa
->instr_type
& OPC_SHIFT
) {
564 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7 * 4))
567 } else if (pa
->instr_type
& OPC_TEST
) {
568 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
570 } else if (pa
->instr_type
& OPC_B
) {
571 if (!(opcode
>= pa
->sym
&& opcode
<= pa
->sym
+ 3))
574 s
= (opcode
- pa
->sym
) & 3;
575 } else if (pa
->instr_type
& OPC_WL
) {
576 if (!(opcode
>= pa
->sym
&& opcode
<= pa
->sym
+ 2))
578 s
= opcode
- pa
->sym
+ 1;
580 if (pa
->sym
!= opcode
)
583 if (pa
->nb_ops
!= nb_ops
)
585 /* now decode and check each operand */
586 for(i
= 0; i
< nb_ops
; i
++) {
588 op1
= pa
->op_type
[i
];
592 v
= OP_IM8
| OP_IM16
| OP_IM32
;
595 v
= OP_REG8
| OP_REG16
| OP_REG32
;
598 v
= OP_REG16
| OP_REG32
;
601 v
= OP_IM16
| OP_IM32
;
610 if ((ops
[i
].type
& v
) == 0)
613 /* all is matching ! */
618 if (opcode
>= TOK_ASM_pusha
&& opcode
<= TOK_ASM_emms
) {
620 b
= op0_codes
[opcode
- TOK_ASM_pusha
];
621 if (opcode
== TOK_ASM_o32
) {
622 if (s1
->seg_size
== 32)
626 } else if (opcode
== TOK_ASM_a32
) {
627 if (s1
->seg_size
== 32)
637 error("unknown opcode '%s'",
638 get_tok_str(opcode
, NULL
));
641 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
643 for(i
= 0; s
== 3 && i
< nb_ops
; i
++) {
644 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
645 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
648 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
649 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
)))
652 error("cannot infer opcode suffix");
657 if (s
== 1 || (pa
->instr_type
& OPC_D16
)) {
658 if (s1
->seg_size
== 32)
660 } else if (s
== 2 && !(pa
->instr_type
& OPC_D16
)) {
661 if (s1
->seg_size
== 16)
665 /* generate a16/a32 prefix if needed */
666 if ((a32
== 1) && (addr32
== 0))
668 /* generate o16/o32 prefix if needed */
669 if ((o32
== 1) && (data32
== 0))
674 /* now generates the operation */
675 if (pa
->instr_type
& OPC_FWAIT
)
681 if (v
== 0x69 || v
== 0x69) {
682 /* kludge for imul $im, %reg */
685 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
686 v
--; /* int $3 case */
688 } else if ((v
== 0x06 || v
== 0x07)) {
689 if (ops
[0].reg
>= 4) {
690 /* push/pop %fs or %gs */
691 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
693 v
+= ops
[0].reg
<< 3;
696 } else if (v
<= 0x05) {
698 v
+= ((opcode
- TOK_ASM_addb
) >> 2) << 3;
699 } else if ((pa
->instr_type
& (OPC_FARITH
| OPC_MODRM
)) == OPC_FARITH
) {
701 v
+= ((opcode
- pa
->sym
) / 6) << 3;
703 if (pa
->instr_type
& OPC_REG
) {
704 for(i
= 0; i
< nb_ops
; i
++) {
705 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
710 /* mov $im, %reg case */
711 if (pa
->opcode
== 0xb0 && s
>= 1)
714 if (pa
->instr_type
& OPC_B
)
716 if (pa
->instr_type
& OPC_TEST
)
717 v
+= test_bits
[opcode
- pa
->sym
];
718 if (pa
->instr_type
& OPC_SHORTJMP
) {
722 /* see if we can really generate the jump with a byte offset */
726 if (sym
->r
!= cur_text_section
->sh_num
)
728 jmp_disp
= ops
[0].e
.v
+ sym
->jnext
- ind
- 2;
729 if (jmp_disp
== (int8_t)jmp_disp
) {
730 /* OK to generate jump */
732 ops
[0].e
.v
= jmp_disp
;
735 if (pa
->instr_type
& OPC_JMP
) {
736 /* long jump will be allowed. need to modify the
743 error("invalid displacement");
752 /* search which operand will used for modrm */
754 if (pa
->instr_type
& OPC_SHIFT
) {
755 reg
= (opcode
- pa
->sym
) >> 2;
758 } else if (pa
->instr_type
& OPC_ARITH
) {
759 reg
= (opcode
- pa
->sym
) >> 2;
760 } else if (pa
->instr_type
& OPC_FARITH
) {
761 reg
= (opcode
- pa
->sym
) / 6;
763 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
765 if (pa
->instr_type
& OPC_MODRM
) {
766 /* first look for an ea operand */
767 for(i
= 0;i
< nb_ops
; i
++) {
768 if (op_type
[i
] & OP_EA
)
771 /* then if not found, a register or indirection (shift instructions) */
772 for(i
= 0;i
< nb_ops
; i
++) {
773 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
777 error("bad op table");
781 /* if a register is used in another operand then it is
782 used instead of group */
783 for(i
= 0;i
< nb_ops
; i
++) {
785 if (i
!= modrm_index
&&
786 (v
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
792 asm_modrm(reg
, &ops
[modrm_index
]);
796 if (pa
->opcode
== 0x9a || pa
->opcode
== 0xea) {
797 /* ljmp or lcall kludge */
798 if (s1
->seg_size
== 16) {
800 gen_expr16(&ops
[1].e
);
802 gen_expr32(&ops
[1].e
);
804 gen_expr32(&ops
[1].e
);
807 error("cannot relocate");
809 gen_le16(ops
[0].e
.v
);
811 for(i
= 0;i
< nb_ops
; i
++) {
813 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM8S
| OP_ADDR
)) {
814 /* if multiple sizes are given it means we must look
816 if (v
== (OP_IM8
| OP_IM16
| OP_IM32
) ||
817 v
== (OP_IM16
| OP_IM32
)) {
825 if (v
& (OP_IM8
| OP_IM8S
)) {
829 } else if (v
& OP_IM16
) {
830 if (s1
->seg_size
== 16)
831 gen_expr16(&ops
[i
].e
);
835 gen_le16(ops
[i
].e
.v
);
838 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
842 if (s1
->seg_size
== 16)
843 gen_disp16(&ops
[i
].e
);
845 gen_disp32(&ops
[i
].e
);
848 if (s1
->seg_size
== 16) {
849 if ((o32
== 1) && (v
& OP_IM32
))
850 gen_expr32(&ops
[i
].e
);
852 gen_expr16(&ops
[i
].e
);
853 } else if (s1
->seg_size
== 32) {
855 gen_expr16(&ops
[i
].e
);
857 gen_expr32(&ops
[i
].e
);
861 } else if (v
& (OP_REG16
| OP_REG32
)) {
862 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
864 g(0xE0 + ops
[i
].reg
);
871 /* return the constraint priority (we allocate first the lowest
872 numbered constraints) */
873 static inline int constraint_priority(const char *str
)
877 /* we take the lowest priority */
911 error("unknown constraint '%c'", c
);
920 static const char *skip_constraint_modifiers(const char *p
)
922 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
927 #define REG_OUT_MASK 0x01
928 #define REG_IN_MASK 0x02
930 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
932 void asm_compute_constraints(ASMOperand
*operands
,
933 int nb_operands
, int nb_outputs
,
934 const uint8_t *clobber_regs
,
938 int sorted_op
[MAX_ASM_OPERANDS
];
939 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
941 uint8_t regs_allocated
[NB_ASM_REGS
];
944 for(i
=0;i
<nb_operands
;i
++) {
946 op
->input_index
= -1;
952 /* compute constraint priority and evaluate references to output
953 constraints if input constraints */
954 for(i
=0;i
<nb_operands
;i
++) {
956 str
= op
->constraint
;
957 str
= skip_constraint_modifiers(str
);
958 if (isnum(*str
) || *str
== '[') {
959 /* this is a reference to another constraint */
960 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
961 if ((unsigned)k
>= i
|| i
< nb_outputs
)
962 error("invalid reference in constraint %d ('%s')",
965 if (operands
[k
].input_index
>= 0)
966 error("cannot reference twice the same operand");
967 operands
[k
].input_index
= i
;
970 op
->priority
= constraint_priority(str
);
974 /* sort operands according to their priority */
975 for(i
=0;i
<nb_operands
;i
++)
977 for(i
=0;i
<nb_operands
- 1;i
++) {
978 for(j
=i
+1;j
<nb_operands
;j
++) {
979 p1
= operands
[sorted_op
[i
]].priority
;
980 p2
= operands
[sorted_op
[j
]].priority
;
983 sorted_op
[i
] = sorted_op
[j
];
989 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
991 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
993 regs_allocated
[i
] = 0;
995 /* esp cannot be used */
996 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
997 /* ebp cannot be used yet */
998 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
1000 /* allocate registers and generate corresponding asm moves */
1001 for(i
=0;i
<nb_operands
;i
++) {
1004 str
= op
->constraint
;
1005 /* no need to allocate references */
1006 if (op
->ref_index
>= 0)
1008 /* select if register is used for output, input or both */
1009 if (op
->input_index
>= 0) {
1010 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1011 } else if (j
< nb_outputs
) {
1012 reg_mask
= REG_OUT_MASK
;
1014 reg_mask
= REG_IN_MASK
;
1025 if (j
>= nb_outputs
)
1026 error("'%c' modifier can only be applied to outputs", c
);
1027 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1030 /* allocate both eax and edx */
1031 if (is_reg_allocated(TREG_EAX
) ||
1032 is_reg_allocated(TREG_EDX
))
1036 regs_allocated
[TREG_EAX
] |= reg_mask
;
1037 regs_allocated
[TREG_EDX
] |= reg_mask
;
1057 if (is_reg_allocated(reg
))
1061 /* eax, ebx, ecx or edx */
1062 for(reg
= 0; reg
< 4; reg
++) {
1063 if (!is_reg_allocated(reg
))
1068 /* any general register */
1069 for(reg
= 0; reg
< 8; reg
++) {
1070 if (!is_reg_allocated(reg
))
1075 /* now we can reload in the register */
1078 regs_allocated
[reg
] |= reg_mask
;
1081 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1087 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
1092 /* nothing special to do because the operand is already in
1093 memory, except if the pointer itself is stored in a
1094 memory variable (VT_LLOCAL case) */
1095 /* XXX: fix constant case */
1096 /* if it is a reference to a memory zone, it must lie
1097 in a register, so we reserve the register in the
1098 input registers and a load will be generated
1100 if (j
< nb_outputs
|| c
== 'm') {
1101 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1102 /* any general register */
1103 for(reg
= 0; reg
< 8; reg
++) {
1104 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1109 /* now we can reload in the register */
1110 regs_allocated
[reg
] |= REG_IN_MASK
;
1117 error("asm constraint %d ('%s') could not be satisfied",
1121 /* if a reference is present for that operand, we assign it too */
1122 if (op
->input_index
>= 0) {
1123 operands
[op
->input_index
].reg
= op
->reg
;
1124 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1128 /* compute out_reg. It is used to store outputs registers to memory
1129 locations references by pointers (VT_LLOCAL case) */
1131 for(i
=0;i
<nb_operands
;i
++) {
1134 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1136 for(reg
= 0; reg
< 8; reg
++) {
1137 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1140 error("could not find free output register for reloading");
1147 /* print sorted constraints */
1149 for(i
=0;i
<nb_operands
;i
++) {
1152 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1154 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1160 printf("out_reg=%d\n", *pout_reg
);
1164 void subst_asm_operand(CString
*add_str
,
1165 SValue
*sv
, int modifier
)
1167 int r
, reg
, size
, val
;
1171 if ((r
& VT_VALMASK
) == VT_CONST
) {
1172 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n')
1173 cstr_ccat(add_str
, '$');
1175 cstr_cat(add_str
, get_tok_str(sv
->sym
->v
, NULL
));
1177 cstr_ccat(add_str
, '+');
1183 if (modifier
== 'n')
1185 snprintf(buf
, sizeof(buf
), "%d", sv
->c
.i
);
1186 cstr_cat(add_str
, buf
);
1187 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1188 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", sv
->c
.i
);
1189 cstr_cat(add_str
, buf
);
1190 } else if (r
& VT_LVAL
) {
1191 reg
= r
& VT_VALMASK
;
1192 if (reg
>= VT_CONST
)
1193 error("internal compiler error");
1194 snprintf(buf
, sizeof(buf
), "(%%%s)",
1195 get_tok_str(TOK_ASM_eax
+ reg
, NULL
));
1196 cstr_cat(add_str
, buf
);
1199 reg
= r
& VT_VALMASK
;
1200 if (reg
>= VT_CONST
)
1201 error("internal compiler error");
1203 /* choose register operand size */
1204 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
)
1206 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1210 if (size
== 1 && reg
>= 4)
1213 if (modifier
== 'b') {
1215 error("cannot use byte register");
1217 } else if (modifier
== 'h') {
1219 error("cannot use byte register");
1221 } else if (modifier
== 'w') {
1227 reg
= TOK_ASM_ah
+ reg
;
1230 reg
= TOK_ASM_al
+ reg
;
1233 reg
= TOK_ASM_ax
+ reg
;
1236 reg
= TOK_ASM_eax
+ reg
;
1239 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1240 cstr_cat(add_str
, buf
);
1244 /* generate prolog and epilog code for asm statment */
1245 void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1246 int nb_outputs
, int is_output
,
1247 uint8_t *clobber_regs
,
1250 uint8_t regs_allocated
[NB_ASM_REGS
];
1253 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1255 /* mark all used registers */
1256 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1257 for(i
= 0; i
< nb_operands
;i
++) {
1260 regs_allocated
[op
->reg
] = 1;
1263 /* generate reg save code */
1264 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1266 if (regs_allocated
[reg
]) {
1267 if (tcc_state
->seg_size
== 16)
1273 /* generate load code */
1274 for(i
= 0; i
< nb_operands
; i
++) {
1277 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1279 /* memory reference case (for both input and
1283 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1285 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1286 /* load value in register */
1287 load(op
->reg
, op
->vt
);
1292 load(TREG_EDX
, &sv
);
1298 /* generate save code */
1299 for(i
= 0 ; i
< nb_outputs
; i
++) {
1302 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1303 if (!op
->is_memory
) {
1306 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1309 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1310 store(op
->reg
, &sv
);
1313 store(op
->reg
, op
->vt
);
1318 store(TREG_EDX
, &sv
);
1323 /* generate reg restore code */
1324 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1326 if (regs_allocated
[reg
]) {
1327 if (tcc_state
->seg_size
== 16)
1335 void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1340 if (!strcmp(str
, "memory") ||
1343 ts
= tok_alloc(str
, strlen(str
));
1345 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1347 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1350 error("invalid clobber register '%s'", str
);
1352 clobber_regs
[reg
] = 1;