release/src/include/pcicfg.h

   1 /*
   2  * pcicfg.h: PCI configuration  constants and structures.
   3  *
   4  * Copyright 2005, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: pcicfg.h,v 1.1.1.8 2005/03/07 07:31:12 kanki Exp $
  13  */
  14
  15 #ifndef _h_pci_
  16 #define _h_pci_
  17
  18 /* The following inside ifndef's so we don't collide with NTDDK.H */
  19 #ifndef PCI_MAX_BUS
  20 #define PCI_MAX_BUS             0x100
  21 #endif
  22 #ifndef PCI_MAX_DEVICES
  23 #define PCI_MAX_DEVICES         0x20
  24 #endif
  25 #ifndef PCI_MAX_FUNCTION
  26 #define PCI_MAX_FUNCTION        0x8
  27 #endif
  28
  29 #ifndef PCI_INVALID_VENDORID
  30 #define PCI_INVALID_VENDORID    0xffff
  31 #endif
  32 #ifndef PCI_INVALID_DEVICEID
  33 #define PCI_INVALID_DEVICEID    0xffff
  34 #endif
  35
  36
  37 /* Convert between bus-slot-function-register and config addresses */
  38
  39 #define PCICFG_BUS_SHIFT        16      /* Bus shift */
  40 #define PCICFG_SLOT_SHIFT       11      /* Slot shift */
  41 #define PCICFG_FUN_SHIFT        8       /* Function shift */
  42 #define PCICFG_OFF_SHIFT        0       /* Bus shift */
  43
  44 #define PCICFG_BUS_MASK         0xff    /* Bus mask */
  45 #define PCICFG_SLOT_MASK        0x1f    /* Slot mask */
  46 #define PCICFG_FUN_MASK         7       /* Function mask */
  47 #define PCICFG_OFF_MASK         0xff    /* Bus mask */
  48
  49 #define PCI_CONFIG_ADDR(b, s, f, o)                                     \
  50                 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT)          \
  51                  | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT)      \
  52                  | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT)        \
  53                  | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
  54
  55 #define PCI_CONFIG_BUS(a)       (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
  56 #define PCI_CONFIG_SLOT(a)      (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
  57 #define PCI_CONFIG_FUN(a)       (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
  58 #define PCI_CONFIG_OFF(a)       (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
  59
  60
  61 /* The actual config space */
  62
  63 #define PCI_BAR_MAX             6
  64
  65 #define PCI_ROM_BAR             8
  66
  67 #define PCR_RSVDA_MAX           2
  68
  69 typedef struct _pci_config_regs {
  70     unsigned short      vendor;
  71     unsigned short      device;
  72     unsigned short      command;
  73     unsigned short      status;
  74     unsigned char       rev_id;
  75     unsigned char       prog_if;
  76     unsigned char       sub_class;
  77     unsigned char       base_class;
  78     unsigned char       cache_line_size;
  79     unsigned char       latency_timer;
  80     unsigned char       header_type;
  81     unsigned char       bist;
  82     unsigned long       base[PCI_BAR_MAX];
  83     unsigned long       cardbus_cis;
  84     unsigned short      subsys_vendor;
  85     unsigned short      subsys_id;
  86     unsigned long       baserom;
  87     unsigned long       rsvd_a[PCR_RSVDA_MAX];
  88     unsigned char       int_line;
  89     unsigned char       int_pin;
  90     unsigned char       min_gnt;
  91     unsigned char       max_lat;
  92     unsigned char       dev_dep[192];
  93 } pci_config_regs;
  94
  95 #define SZPCR           (sizeof (pci_config_regs))
  96 #define MINSZPCR        64              /* offsetof (dev_dep[0] */
  97
  98 /* A structure for the config registers is nice, but in most
  99  * systems the config space is not memory mapped, so we need
 100  * filed offsetts. :-(
 101  */
 102 #define PCI_CFG_VID             0
 103 #define PCI_CFG_DID             2
 104 #define PCI_CFG_CMD             4
 105 #define PCI_CFG_STAT            6
 106 #define PCI_CFG_REV             8
 107 #define PCI_CFG_PROGIF          9
 108 #define PCI_CFG_SUBCL           0xa
 109 #define PCI_CFG_BASECL          0xb
 110 #define PCI_CFG_CLSZ            0xc
 111 #define PCI_CFG_LATTIM          0xd
 112 #define PCI_CFG_HDR             0xe
 113 #define PCI_CFG_BIST            0xf
 114 #define PCI_CFG_BAR0            0x10
 115 #define PCI_CFG_BAR1            0x14
 116 #define PCI_CFG_BAR2            0x18
 117 #define PCI_CFG_BAR3            0x1c
 118 #define PCI_CFG_BAR4            0x20
 119 #define PCI_CFG_BAR5            0x24
 120 #define PCI_CFG_CIS             0x28
 121 #define PCI_CFG_SVID            0x2c
 122 #define PCI_CFG_SSID            0x2e
 123 #define PCI_CFG_ROMBAR          0x30
 124 #define PCI_CFG_INT             0x3c
 125 #define PCI_CFG_PIN             0x3d
 126 #define PCI_CFG_MINGNT          0x3e
 127 #define PCI_CFG_MAXLAT          0x3f
 128
 129 /* Classes and subclasses */
 130
 131 typedef enum {
 132     PCI_CLASS_OLD = 0,
 133     PCI_CLASS_DASDI,
 134     PCI_CLASS_NET,
 135     PCI_CLASS_DISPLAY,
 136     PCI_CLASS_MMEDIA,
 137     PCI_CLASS_MEMORY,
 138     PCI_CLASS_BRIDGE,
 139     PCI_CLASS_COMM,
 140     PCI_CLASS_BASE,
 141     PCI_CLASS_INPUT,
 142     PCI_CLASS_DOCK,
 143     PCI_CLASS_CPU,
 144     PCI_CLASS_SERIAL,
 145     PCI_CLASS_INTELLIGENT = 0xe,
 146     PCI_CLASS_SATELLITE,
 147     PCI_CLASS_CRYPT,
 148     PCI_CLASS_DSP,
 149     PCI_CLASS_MAX
 150 } pci_classes;
 151
 152 typedef enum {
 153     PCI_DASDI_SCSI,
 154     PCI_DASDI_IDE,
 155     PCI_DASDI_FLOPPY,
 156     PCI_DASDI_IPI,
 157     PCI_DASDI_RAID,
 158     PCI_DASDI_OTHER = 0x80
 159 } pci_dasdi_subclasses;
 160
 161 typedef enum {
 162     PCI_NET_ETHER,
 163     PCI_NET_TOKEN,
 164     PCI_NET_FDDI,
 165     PCI_NET_ATM,
 166     PCI_NET_OTHER = 0x80
 167 } pci_net_subclasses;
 168
 169 typedef enum {
 170     PCI_DISPLAY_VGA,
 171     PCI_DISPLAY_XGA,
 172     PCI_DISPLAY_3D,
 173     PCI_DISPLAY_OTHER = 0x80
 174 } pci_display_subclasses;
 175
 176 typedef enum {
 177     PCI_MMEDIA_VIDEO,
 178     PCI_MMEDIA_AUDIO,
 179     PCI_MMEDIA_PHONE,
 180     PCI_MEDIA_OTHER = 0x80
 181 } pci_mmedia_subclasses;
 182
 183 typedef enum {
 184     PCI_MEMORY_RAM,
 185     PCI_MEMORY_FLASH,
 186     PCI_MEMORY_OTHER = 0x80
 187 } pci_memory_subclasses;
 188
 189 typedef enum {
 190     PCI_BRIDGE_HOST,
 191     PCI_BRIDGE_ISA,
 192     PCI_BRIDGE_EISA,
 193     PCI_BRIDGE_MC,
 194     PCI_BRIDGE_PCI,
 195     PCI_BRIDGE_PCMCIA,
 196     PCI_BRIDGE_NUBUS,
 197     PCI_BRIDGE_CARDBUS,
 198     PCI_BRIDGE_RACEWAY,
 199     PCI_BRIDGE_OTHER = 0x80
 200 } pci_bridge_subclasses;
 201
 202 typedef enum {
 203     PCI_COMM_UART,
 204     PCI_COMM_PARALLEL,
 205     PCI_COMM_MULTIUART,
 206     PCI_COMM_MODEM,
 207     PCI_COMM_OTHER = 0x80
 208 } pci_comm_subclasses;
 209
 210 typedef enum {
 211     PCI_BASE_PIC,
 212     PCI_BASE_DMA,
 213     PCI_BASE_TIMER,
 214     PCI_BASE_RTC,
 215     PCI_BASE_PCI_HOTPLUG,
 216     PCI_BASE_OTHER = 0x80
 217 } pci_base_subclasses;
 218
 219 typedef enum {
 220     PCI_INPUT_KBD,
 221     PCI_INPUT_PEN,
 222     PCI_INPUT_MOUSE,
 223     PCI_INPUT_SCANNER,
 224     PCI_INPUT_GAMEPORT,
 225     PCI_INPUT_OTHER = 0x80
 226 } pci_input_subclasses;
 227
 228 typedef enum {
 229     PCI_DOCK_GENERIC,
 230     PCI_DOCK_OTHER = 0x80
 231 } pci_dock_subclasses;
 232
 233 typedef enum {
 234     PCI_CPU_386,
 235     PCI_CPU_486,
 236     PCI_CPU_PENTIUM,
 237     PCI_CPU_ALPHA = 0x10,
 238     PCI_CPU_POWERPC = 0x20,
 239     PCI_CPU_MIPS = 0x30,
 240     PCI_CPU_COPROC = 0x40,
 241     PCI_CPU_OTHER = 0x80
 242 } pci_cpu_subclasses;
 243
 244 typedef enum {
 245     PCI_SERIAL_IEEE1394,
 246     PCI_SERIAL_ACCESS,
 247     PCI_SERIAL_SSA,
 248     PCI_SERIAL_USB,
 249     PCI_SERIAL_FIBER,
 250     PCI_SERIAL_SMBUS,
 251     PCI_SERIAL_OTHER = 0x80
 252 } pci_serial_subclasses;
 253
 254 typedef enum {
 255     PCI_INTELLIGENT_I2O,
 256 } pci_intelligent_subclasses;
 257
 258 typedef enum {
 259     PCI_SATELLITE_TV,
 260     PCI_SATELLITE_AUDIO,
 261     PCI_SATELLITE_VOICE,
 262     PCI_SATELLITE_DATA,
 263     PCI_SATELLITE_OTHER = 0x80
 264 } pci_satellite_subclasses;
 265
 266 typedef enum {
 267     PCI_CRYPT_NETWORK,
 268     PCI_CRYPT_ENTERTAINMENT,
 269     PCI_CRYPT_OTHER = 0x80
 270 } pci_crypt_subclasses;
 271
 272 typedef enum {
 273     PCI_DSP_DPIO,
 274     PCI_DSP_OTHER = 0x80
 275 } pci_dsp_subclasses;
 276
 277 /* Header types */
 278 typedef enum {
 279         PCI_HEADER_NORMAL,
 280         PCI_HEADER_BRIDGE,
 281         PCI_HEADER_CARDBUS
 282 } pci_header_types;
 283
 284
 285 /* Overlay for a PCI-to-PCI bridge */
 286
 287 #define PPB_RSVDA_MAX           2
 288 #define PPB_RSVDD_MAX           8
 289
 290 typedef struct _ppb_config_regs {
 291     unsigned short      vendor;
 292     unsigned short      device;
 293     unsigned short      command;
 294     unsigned short      status;
 295     unsigned char       rev_id;
 296     unsigned char       prog_if;
 297     unsigned char       sub_class;
 298     unsigned char       base_class;
 299     unsigned char       cache_line_size;
 300     unsigned char       latency_timer;
 301     unsigned char       header_type;
 302     unsigned char       bist;
 303     unsigned long       rsvd_a[PPB_RSVDA_MAX];
 304     unsigned char       prim_bus;
 305     unsigned char       sec_bus;
 306     unsigned char       sub_bus;
 307     unsigned char       sec_lat;
 308     unsigned char       io_base;
 309     unsigned char       io_lim;
 310     unsigned short      sec_status;
 311     unsigned short      mem_base;
 312     unsigned short      mem_lim;
 313     unsigned short      pf_mem_base;
 314     unsigned short      pf_mem_lim;
 315     unsigned long       pf_mem_base_hi;
 316     unsigned long       pf_mem_lim_hi;
 317     unsigned short      io_base_hi;
 318     unsigned short      io_lim_hi;
 319     unsigned short      subsys_vendor;
 320     unsigned short      subsys_id;
 321     unsigned long       rsvd_b;
 322     unsigned char       rsvd_c;
 323     unsigned char       int_pin;
 324     unsigned short      bridge_ctrl;
 325     unsigned char       chip_ctrl;
 326     unsigned char       diag_ctrl;
 327     unsigned short      arb_ctrl;
 328     unsigned long       rsvd_d[PPB_RSVDD_MAX];
 329     unsigned char       dev_dep[192];
 330 } ppb_config_regs;
 331
 332 /* Eveything below is BRCM HND proprietary */
 333
 334 #define PCI_BAR0_WIN            0x80    /* backplane addres space accessed by BAR0 */
 335 #define PCI_BAR1_WIN            0x84    /* backplane addres space accessed by BAR1 */
 336 #define PCI_SPROM_CONTROL       0x88    /* sprom property control */
 337 #define PCI_BAR1_CONTROL        0x8c    /* BAR1 region burst control */
 338 #define PCI_INT_STATUS          0x90    /* PCI and other cores interrupts */
 339 #define PCI_INT_MASK            0x94    /* mask of PCI and other cores interrupts */
 340 #define PCI_TO_SB_MB            0x98    /* signal backplane interrupts */
 341 #define PCI_BACKPLANE_ADDR      0xA0    /* address an arbitrary location on the system backplane */
 342 #define PCI_BACKPLANE_DATA      0xA4    /* data at the location specified by above address register */
 343 #define PCI_GPIO_IN             0xb0    /* pci config space gpio input (>=rev3) */
 344 #define PCI_GPIO_OUT            0xb4    /* pci config space gpio output (>=rev3) */
 345 #define PCI_GPIO_OUTEN          0xb8    /* pci config space gpio output enable (>=rev3) */
 346
 347 #define PCI_BAR0_SPROM_OFFSET   (4 * 1024)      /* bar0 + 4K accesses external sprom */
 348 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)      /* bar0 + 6K accesses pci core registers */
 349
 350 /* PCI_INT_STATUS */
 351 #define PCI_SBIM_STATUS_SERR    0x4     /* backplane SBErr interrupt status */
 352
 353 /* PCI_INT_MASK */
 354 #define PCI_SBIM_SHIFT          8       /* backplane core interrupt mask bits offset */
 355 #define PCI_SBIM_MASK           0xff00  /* backplane core interrupt mask */
 356 #define PCI_SBIM_MASK_SERR      0x4     /* backplane SBErr interrupt mask */
 357
 358 /* PCI_SPROM_CONTROL */
 359 #define SPROM_BLANK             0x04    /* indicating a blank sprom */
 360 #define SPROM_WRITEEN           0x10    /* sprom write enable */
 361 #define SPROM_BOOTROM_WE        0x20    /* external bootrom write enable */
 362
 363 #define SPROM_SIZE              256     /* sprom size in 16-bit */
 364 #define SPROM_CRC_RANGE         64      /* crc cover range in 16-bit */
 365
 366 /* PCI_CFG_CMD_STAT */
 367 #define PCI_CFG_CMD_STAT_TA     0x08000000      /* target abort status */
 368
 369 #endif