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Tomato 1.28
[tomato-rt-n10.git] / release / src / include / sbchipc.h
blob3c88fcaa6694a4f149cd1fae6b13ed88ec84eb7f
1 /*
2 * SiliconBackplane Chipcommon core hardware definitions.
3 *
4 * The chipcommon core provides chip identification, SB control,
5 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6 * gpio interface, extbus, and support for serial and parallel flashes.
7 *
8 * $Id: sbchipc.h,v 1.1.1.10 2005/03/07 07:31:12 kanki Exp $
9 * Copyright 2005, Broadcom Corporation
10 * All Rights Reserved.
11 *
12 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16 *
17 */
18
19 #ifndef _SBCHIPC_H
20 #define _SBCHIPC_H
21
22
23 #ifndef _LANGUAGE_ASSEMBLY
24
25 /* cpp contortions to concatenate w/arg prescan */
26 #ifndef PAD
27 #define _PADLINE(line) pad ## line
28 #define _XSTR(line) _PADLINE(line)
29 #define PAD _XSTR(__LINE__)
30 #endif /* PAD */
31
32 typedef volatile struct {
33 uint32 chipid; /* 0x0 */
34 uint32 capabilities;
35 uint32 corecontrol; /* corerev >= 1 */
36 uint32 bist;
37
38 /* OTP */
39 uint32 otpstatus; /* 0x10, corerev >= 10 */
40 uint32 otpcontrol;
41 uint32 otpprog;
42 uint32 PAD;
43
44 /* Interrupt control */
45 uint32 intstatus; /* 0x20 */
46 uint32 intmask;
47 uint32 chipcontrol; /* 0x28, rev >= 11 */
48 uint32 chipstatus; /* 0x2c, rev >= 11 */
49
50 /* Jtag Master */
51 uint32 jtagcmd; /* 0x30, rev >= 10 */
52 uint32 jtagir;
53 uint32 jtagdr;
54 uint32 jtagctrl;
55
56 /* serial flash interface registers */
57 uint32 flashcontrol; /* 0x40 */
58 uint32 flashaddress;
59 uint32 flashdata;
60 uint32 PAD[1];
61
62 /* Silicon backplane configuration broadcast control */
63 uint32 broadcastaddress; /* 0x50 */
64 uint32 broadcastdata;
65 uint32 PAD[2];
66
67 /* gpio - cleared only by power-on-reset */
68 uint32 gpioin; /* 0x60 */
69 uint32 gpioout;
70 uint32 gpioouten;
71 uint32 gpiocontrol;
72 uint32 gpiointpolarity;
73 uint32 gpiointmask;
74 uint32 PAD[2];
75
76 /* Watchdog timer */
77 uint32 watchdog; /* 0x80 */
78 uint32 PAD[3];
79
80 /* clock control */
81 uint32 clockcontrol_n; /* 0x90 */
82 uint32 clockcontrol_sb; /* aka m0 */
83 uint32 clockcontrol_pci; /* aka m1 */
84 uint32 clockcontrol_m2; /* mii/uart/mipsref */
85 uint32 clockcontrol_mips; /* aka m3 */
86 uint32 clkdiv; /* corerev >= 3 */
87 uint32 PAD[2];
88
89 /* pll delay registers (corerev >= 4) */
90 uint32 pll_on_delay; /* 0xb0 */
91 uint32 fref_sel_delay;
92 uint32 slow_clk_ctl; /* 5 < corerev < 10 */
93 uint32 PAD[1];
94
95 /* Instaclock registers (corerev >= 10) */
96 uint32 system_clk_ctl; /* 0xc0 */
97 uint32 clkstatestretch;
98 uint32 PAD[14];
99
100 /* ExtBus control registers (corerev >= 3) */
101 uint32 pcmcia_config; /* 0x100 */
102 uint32 pcmcia_memwait;
103 uint32 pcmcia_attrwait;
104 uint32 pcmcia_iowait;
105 uint32 ide_config;
106 uint32 ide_memwait;
107 uint32 ide_attrwait;
108 uint32 ide_iowait;
109 uint32 prog_config;
110 uint32 prog_waitcount;
111 uint32 flash_config;
112 uint32 flash_waitcount;
113 uint32 PAD[116];
114
115 /* uarts */
116 uint8 uart0data; /* 0x300 */
117 uint8 uart0imr;
118 uint8 uart0fcr;
119 uint8 uart0lcr;
120 uint8 uart0mcr;
121 uint8 uart0lsr;
122 uint8 uart0msr;
123 uint8 uart0scratch;
124 uint8 PAD[248]; /* corerev >= 1 */
125
126 uint8 uart1data; /* 0x400 */
127 uint8 uart1imr;
128 uint8 uart1fcr;
129 uint8 uart1lcr;
130 uint8 uart1mcr;
131 uint8 uart1lsr;
132 uint8 uart1msr;
133 uint8 uart1scratch;
134 } chipcregs_t;
135
136 #endif /* _LANGUAGE_ASSEMBLY */
137
138 #define CC_CHIPID 0
139 #define CC_CAPABILITIES 4
140 #define CC_JTAGCMD 0x30
141 #define CC_JTAGIR 0x34
142 #define CC_JTAGDR 0x38
143 #define CC_JTAGCTRL 0x3c
144 #define CC_CLKDIV 0xa4
145 #define CC_OTP 0x800
146
147 /* chipid */
148 #define CID_ID_MASK 0x0000ffff /* Chip Id mask */
149 #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
150 #define CID_REV_SHIFT 16 /* Chip Revision shift */
151 #define CID_PKG_MASK 0x00f00000 /* Package Option mask */
152 #define CID_PKG_SHIFT 20 /* Package Option shift */
153 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
154 #define CID_CC_SHIFT 24
155
156 /* capabilities */
157 #define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
158 #define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
159 #define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
160 #define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
161 #define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
162 #define CAP_EXTBUS 0x00000040 /* External bus present */
163 #define CAP_FLASH_MASK 0x00000700 /* Type of flash */
164 #define CAP_PLL_MASK 0x00038000 /* Type of PLL */
165 #define CAP_PWR_CTL 0x00040000 /* Power control */
166 #define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
167 #define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
168 #define CAP_JTAGP 0x00400000 /* JTAG Master Present */
169 #define CAP_ROM 0x00800000 /* Internal boot rom active */
170
171 /* PLL type */
172 #define PLL_NONE 0x00000000
173 #define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
174 #define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
175 #define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
176 #define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
177 #define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
178 #define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
179 #define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
180
181 /* corecontrol */
182 #define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
183 #define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
184
185 /* jtagcmd */
186 #define JCMD_START 0x80000000
187 #define JCMD_BUSY 0x80000000
188 #define JCMD_PAUSE 0x40000000
189 #define JCMD0_ACC_MASK 0x0000f000
190 #define JCMD0_ACC_IRDR 0x00000000
191 #define JCMD0_ACC_DR 0x00001000
192 #define JCMD0_ACC_IR 0x00002000
193 #define JCMD0_ACC_RESET 0x00003000
194 #define JCMD0_ACC_IRPDR 0x00004000
195 #define JCMD0_ACC_PDR 0x00005000
196 #define JCMD0_IRW_MASK 0x00000f00
197 #define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
198 #define JCMD_ACC_IRDR 0x00000000
199 #define JCMD_ACC_DR 0x00010000
200 #define JCMD_ACC_IR 0x00020000
201 #define JCMD_ACC_RESET 0x00030000
202 #define JCMD_ACC_IRPDR 0x00040000
203 #define JCMD_ACC_PDR 0x00050000
204 #define JCMD_IRW_MASK 0x00001f00
205 #define JCMD_IRW_SHIFT 8
206 #define JCMD_DRW_MASK 0x0000003f
207
208 /* jtagctrl */
209 #define JCTRL_FORCE_CLK 4 /* Force clock */
210 #define JCTRL_EXT_EN 2 /* Enable external targets */
211 #define JCTRL_EN 1 /* Enable Jtag master */
212
213 /* Fields in clkdiv */
214 #define CLKD_SFLASH 0x0f000000
215 #define CLKD_SFLASH_SHIFT 24
216 #define CLKD_OTP 0x000f0000
217 #define CLKD_OTP_SHIFT 16
218 #define CLKD_JTAG 0x00000f00
219 #define CLKD_JTAG_SHIFT 8
220 #define CLKD_UART 0x000000ff
221
222 /* intstatus/intmask */
223 #define CI_GPIO 0x00000001 /* gpio intr */
224 #define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
225 #define CI_WDRESET 0x80000000 /* watchdog reset occurred */
226
227 /* slow_clk_ctl */
228 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */
229 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
230 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
231 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
232 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
233 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
234 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
235 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
236 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
237 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
238 #define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
239 #define SCC_CD_SHF 16 /* CLockDivider shift */
240
241 /* sys_clk_ctl */
242 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
243 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
244 #define SYCC_FP 0x00000004 /* ForcePLLOn */
245 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
246 #define SYCC_HR 0x00000010 /* Force HT */
247 #define SYCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
248 #define SYCC_CD_SHF 16 /* CLockDivider shift */
249
250 /* clockcontrol_n */
251 #define CN_N1_MASK 0x3f /* n1 control */
252 #define CN_N2_MASK 0x3f00 /* n2 control */
253 #define CN_N2_SHIFT 8
254 #define CN_PLLC_MASK 0xf0000 /* pll control */
255 #define CN_PLLC_SHIFT 16
256
257 /* clockcontrol_sb/pci/uart */
258 #define CC_M1_MASK 0x3f /* m1 control */
259 #define CC_M2_MASK 0x3f00 /* m2 control */
260 #define CC_M2_SHIFT 8
261 #define CC_M3_MASK 0x3f0000 /* m3 control */
262 #define CC_M3_SHIFT 16
263 #define CC_MC_MASK 0x1f000000 /* mux control */
264 #define CC_MC_SHIFT 24
265
266 /* N3M Clock control values for 125Mhz */
267 #define CC_125_N 0x0802 /* Default values for bcm4310 */
268 #define CC_125_M 0x04020009
269 #define CC_125_M25 0x11090009
270 #define CC_125_M33 0x11090005
271
272 /* N3M Clock control magic field values */
273 #define CC_F6_2 0x02 /* A factor of 2 in */
274 #define CC_F6_3 0x03 /* 6-bit fields like */
275 #define CC_F6_4 0x05 /* N1, M1 or M3 */
276 #define CC_F6_5 0x09
277 #define CC_F6_6 0x11
278 #define CC_F6_7 0x21
279
280 #define CC_F5_BIAS 5 /* 5-bit fields get this added */
281
282 #define CC_MC_BYPASS 0x08
283 #define CC_MC_M1 0x04
284 #define CC_MC_M1M2 0x02
285 #define CC_MC_M1M2M3 0x01
286 #define CC_MC_M1M3 0x11
287
288 /* Type 2 Clock control magic field values */
289 #define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
290 #define CC_T2M2_BIAS 3 /* m2 bias */
291
292 #define CC_T2MC_M1BYP 1
293 #define CC_T2MC_M2BYP 2
294 #define CC_T2MC_M3BYP 4
295
296 /* Type 6 Clock control magic field values */
297 #define CC_T6_MMASK 1 /* bits of interest in m */
298 #define CC_T6_M0 120000000 /* sb clock for m = 0 */
299 #define CC_T6_M1 100000000 /* sb clock for m = 1 */
300 #define SB2MIPS_T6(sb) (2 * (sb))
301
302 /* Common clock base */
303 #define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
304 #define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
305
306 /* Flash types in the chipcommon capabilities register */
307 #define FLASH_NONE 0x000 /* No flash */
308 #define SFLASH_ST 0x100 /* ST serial flash */
309 #define SFLASH_AT 0x200 /* Atmel serial flash */
310 #define PFLASH 0x700 /* Parallel flash */
311
312 /* Bits in the config registers */
313 #define CC_CFG_EN 0x0001 /* Enable */
314 #define CC_CFG_EM_MASK 0x000e /* Extif Mode */
315 #define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
316 #define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
317 #define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
318 #define CC_CFG_EM_IDE 0x000a /* IDE */
319 #define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
320 #define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
321 #define CC_CFG_CE 0x0080 /* Sync: Clock enable */
322 #define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
323
324 /* Start/busy bit in flashcontrol */
325 #define SFLASH_START 0x80000000
326 #define SFLASH_BUSY SFLASH_START
327
328 /* flashcontrol opcodes for ST flashes */
329 #define SFLASH_ST_WREN 0x0006 /* Write Enable */
330 #define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
331 #define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
332 #define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
333 #define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
334 #define SFLASH_ST_PP 0x0302 /* Page Program */
335 #define SFLASH_ST_SE 0x02d8 /* Sector Erase */
336 #define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
337 #define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
338 #define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
339
340 /* Status register bits for ST flashes */
341 #define SFLASH_ST_WIP 0x01 /* Write In Progress */
342 #define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
343 #define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
344 #define SFLASH_ST_BP_SHIFT 2
345 #define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
346
347 /* flashcontrol opcodes for Atmel flashes */
348 #define SFLASH_AT_READ 0x07e8
349 #define SFLASH_AT_PAGE_READ 0x07d2
350 #define SFLASH_AT_BUF1_READ
351 #define SFLASH_AT_BUF2_READ
352 #define SFLASH_AT_STATUS 0x01d7
353 #define SFLASH_AT_BUF1_WRITE 0x0384
354 #define SFLASH_AT_BUF2_WRITE 0x0387
355 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
356 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
357 #define SFLASH_AT_BUF1_PROGRAM 0x0288
358 #define SFLASH_AT_BUF2_PROGRAM 0x0289
359 #define SFLASH_AT_PAGE_ERASE 0x0281
360 #define SFLASH_AT_BLOCK_ERASE 0x0250
361 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
362 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
363 #define SFLASH_AT_BUF1_LOAD 0x0253
364 #define SFLASH_AT_BUF2_LOAD 0x0255
365 #define SFLASH_AT_BUF1_COMPARE 0x0260
366 #define SFLASH_AT_BUF2_COMPARE 0x0261
367 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
368 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
369
370 /* Status register bits for Atmel flashes */
371 #define SFLASH_AT_READY 0x80
372 #define SFLASH_AT_MISMATCH 0x40
373 #define SFLASH_AT_ID_MASK 0x38
374 #define SFLASH_AT_ID_SHIFT 3
375
376 /* OTP conventions */
377 #define OTP_HWBASE 0
378 #define OTP_SWLIM 256
379 #define OTP_CIDBASE 256
380 #define OTP_CIDLIM 260
381
382 #define OTP_BOUNDARY 252
383 #define OTP_HWSIGN 253
384 #define OTP_SWSIGN 254
385 #define OTP_CIDSIGN 255
386
387 #define OTP_CID 256
388 #define OTP_PKG 257
389 #define OTP_FID 258
390
391 #define OTP_SIGNATURE 0x578a
392 #define OTP_MAGIC 0x4e56
393
394 #endif /* _SBCHIPC_H */
Tomato For Asus RT-N10 (BCM5356A Chip)