release/src/include/sbmips.h

   1 /*
   2  * Broadcom SiliconBackplane MIPS definitions
   3  *
   4  * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
   5  * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
   6  * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
   7  * interface. The core revision is stored in the SB ID register in SB
   8  * configuration space.
   9  *
  10  * Copyright 2005, Broadcom Corporation
  11  * All Rights Reserved.
  12  *
  13  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
  14  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  15  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  16  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  17  *
  18  * $Id: sbmips.h,v 1.1.1.9 2005/03/07 07:31:12 kanki Exp $
  19  */
  20
  21 #ifndef _SBMIPS_H
  22 #define _SBMIPS_H
  23
  24 #ifndef _LANGUAGE_ASSEMBLY
  25
  26 /* cpp contortions to concatenate w/arg prescan */
  27 #ifndef PAD
  28 #define _PADLINE(line)  pad ## line
  29 #define _XSTR(line)     _PADLINE(line)
  30 #define PAD             _XSTR(__LINE__)
  31 #endif  /* PAD */
  32
  33 typedef volatile struct {
  34         uint32  corecontrol;
  35         uint32  PAD[2];
  36         uint32  biststatus;
  37         uint32  PAD[4];
  38         uint32  intstatus;
  39         uint32  intmask;
  40         uint32  timer;
  41 } mipsregs_t;
  42
  43 extern uint32 sb_flag(void *sbh);
  44 extern uint sb_irq(void *sbh);
  45
  46 extern void BCMINIT(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
  47
  48 extern void *sb_jtagm_init(void *sbh, uint clkd, bool exttap);
  49 extern void sb_jtagm_disable(void *h);
  50 extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
  51 extern void BCMINIT(sb_mips_init)(void *sbh);
  52 extern uint32 BCMINIT(sb_mips_clock)(void *sbh);
  53 extern bool BCMINIT(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
  54
  55 extern uint32 BCMINIT(sb_memc_get_ncdl)(void *sbh);
  56 extern uint32 BCMINIT(sb_mips_get_pfc)(void *sbh);
  57
  58 #endif /* _LANGUAGE_ASSEMBLY */
  59
  60 #endif  /* _SBMIPS_H */