release/src/shared/hndgige.c

   1 /*
   2  * HND SiliconBackplane Gigabit Ethernet core software interface
   3  *
   4  * Copyright 2007, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id$
  13  */
  14
  15 #include <typedefs.h>
  16 #include <osl.h>
  17 #include <pcicfg.h>
  18 #include <sbconfig.h>
  19 #include <bcmutils.h>
  20 #include <sbutils.h>
  21 #include <sbgige.h>
  22 #include <hndpci.h>
  23 #include <hndgige.h>
  24
  25 /*
  26  * Setup the gige core.
  27  * Resetting the core will lose all settings.
  28  */
  29 void
  30 sb_gige_init(sb_t *sbh, uint32 unit, bool *rgmii)
  31 {
  32         volatile pci_config_regs *pci;
  33         sbgige_pcishim_t *ocp;
  34         sbconfig_t *sb;
  35         osl_t *osh;
  36         uint32 statelow;
  37         uint32 statehigh;
  38         uint32 base;
  39         uint32 idx;
  40         void *regs;
  41
  42         /* Sanity checks */
  43         ASSERT(sbh);
  44         ASSERT(rgmii);
  45
  46         idx = sb_coreidx(sbh);
  47
  48         /* point to the gige core registers */
  49         regs = sb_setcore(sbh, SB_GIGETH, unit);
  50         ASSERT(regs);
  51
  52         osh = sb_osh(sbh);
  53
  54         pci = &((sbgige_t *)regs)->pcicfg;
  55         ocp = &((sbgige_t *)regs)->pcishim;
  56         sb = &((sbgige_t *)regs)->sbconfig;
  57
  58         /* Enable the core clock and memory access */
  59         if (!sb_iscoreup(sbh))
  60                 sb_core_reset(sbh, 0, 0);
  61
  62         /*
  63          * Setup the 64K memory-mapped region base address through BAR0.
  64          * Leave the other BAR values alone.
  65          */
  66         base = sb_base(R_REG(osh, &sb->sbadmatch1));
  67         W_REG(osh, &pci->base[0], base);
  68         W_REG(osh, &pci->base[1], 0);
  69
  70         /*
  71          * Enable the PCI memory access anyway. Any PCI config commands
  72          * issued before the core is enabled will go to the emulation
  73          * only and will not go to the real PCI config registers.
  74          */
  75         OR_REG(osh, &pci->command, 2);
  76
  77         /*
  78          * Enable the posted write flush scheme as follows:
  79          *
  80          * - Enable flush on any core register read
  81          * - Enable timeout on the flush
  82          * - Disable the interrupt mask when flushing
  83          *
  84          * This differs from the default setting only in that interrupts are
  85          * not masked.  Since posted writes are not flushed on interrupt, the
  86          * driver must explicitly request a flush in its interrupt handling
  87          * by reading a core register.
  88          */
  89         W_REG(osh, &ocp->FlushStatusControl, 0x68);
  90
  91         /*
  92          * Determine whether the GbE is in GMII or RGMII mode.  This is
  93          * indicated in bit 16 of the SBTMStateHigh register, which is
  94          * part of the core-specific flags field.
  95          *
  96          * For GMII, bypass the Rx/Tx DLLs, i.e. add no delay to RXC/GTXC
  97          * within the core.  For RGMII, do not bypass the DLLs, resulting
  98          * in added delay for RXC/GTXC.  The SBTMStateLow register contains
  99          * the controls for doing this in the core-specific flags field:
 100          *
 101          *   bit 24 - Enable DLL controls
 102          *   bit 20 - Bypass Rx DLL
 103          *   bit 19 - Bypass Tx DLL
 104          */
 105         statelow = R_REG(osh, &sb->sbtmstatelow);       /* DLL controls */
 106         statehigh = R_REG(osh, &sb->sbtmstatehigh);     /* GMII/RGMII mode */
 107         if ((statehigh & (1 << 16)) != 0)       /* RGMII */
 108         {
 109                 statelow &= ~(1 << 20);         /* no Rx bypass (delay) */
 110                 statelow &= ~(1 << 19);         /* no Tx bypass (delay) */
 111                 *rgmii = TRUE;
 112         }
 113         else                                    /* GMII */
 114         {
 115                 statelow |= (1 << 20);          /* Rx bypass (no delay) */
 116                 statelow |= (1 << 19);          /* Tx bypass (no delay) */
 117                 *rgmii = FALSE;
 118         }
 119         statelow |= (1 << 24);                  /* enable DLL controls */
 120         W_REG(osh, &sb->sbtmstatelow, statelow);
 121
 122         sb_setcoreidx(sbh, idx);
 123 }