2 * Copyright (C) 2007 Anton Blad
3 * Copyright (C) 2007 Fredrik Kuivinen
4 * Copyright (C) 2007 Jakob Rosén
6 * This file is licensed under GPL v2.
13 // Configure MOTOR as input.
14 DDR_MOTOR
&= ~(1 << P_MOTOR
);
16 // Configure C64READ as output.
17 PORT_C64READ
|= (1 << P_C64READ
);
18 DDR_C64READ
|= (1 << P_C64READ
);
21 // Configure C64WRITE as input.
22 DDR_C64WRITE
&= ~(_BV(P_C64WRITE
));
24 // Configure C64SENSE as output.
25 PORT_C64SENSE
|= (1 << P_C64SENSE
);
26 DDR_C64SENSE
|= (1 << P_C64SENSE
);
28 // Configure TAPEREAD as input
29 DDR_TAPEREAD
&= ~(_BV(P_TAPEREAD
));
30 PORT_TAPEREAD
&= ~(_BV(P_TAPEREAD
));
32 // Configure TAPEWRITE as output
33 DDR_TAPEWRITE
|= _BV(P_TAPEWRITE
);
35 // Configure TAPESENSE as input.
36 DDR_TAPESENSE
&= ~(_BV(P_TAPESENSE
));
37 //PORT_TAPESENSE |= _BV(P_TAPESENSE);
38 PORT_TAPESENSE
&= ~(_BV(P_TAPESENSE
));
40 // Configure RSIGSEL as output.
41 DDR_RSIGSEL
|= _BV(P_RSIGSEL
);
42 PORT_RSIGSEL
|= _BV(P_RSIGSEL
);