board/netvia/netvia.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  26  * U-Boot port on NetVia board
  27  */
  28
  29 #include <common.h>
  30 #include "mpc8xx.h"
  31
  32 /****************************************************************/
  33
  34 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
  35 /* last value written to the external register; we cannot read back */
  36 unsigned int last_er_val;
  37 #endif
  38
  39 /****************************************************************/
  40
  41 /****************************************************************/
  42
  43 /* some sane bit macros */
  44 #define _BD(_b)                         (1U << (31-(_b)))
  45 #define _BDR(_l, _h)                    (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
  46
  47 #define _BW(_b)                         (1U << (15-(_b)))
  48 #define _BWR(_l, _h)                    (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
  49
  50 #define _BB(_b)                         (1U << (7-(_b)))
  51 #define _BBR(_l, _h)                    (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
  52
  53 #define _B(_b)                          _BD(_b)
  54 #define _BR(_l, _h)                     _BDR(_l, _h)
  55
  56 /****************************************************************/
  57
  58 #define _NOT_USED_      0xFFFFFFFF
  59
  60 /****************************************************************/
  61
  62 #define CS_0000         0x00000000
  63 #define CS_0001         0x10000000
  64 #define CS_0010         0x20000000
  65 #define CS_0011         0x30000000
  66 #define CS_0100         0x40000000
  67 #define CS_0101         0x50000000
  68 #define CS_0110         0x60000000
  69 #define CS_0111         0x70000000
  70 #define CS_1000         0x80000000
  71 #define CS_1001         0x90000000
  72 #define CS_1010         0xA0000000
  73 #define CS_1011         0xB0000000
  74 #define CS_1100         0xC0000000
  75 #define CS_1101         0xD0000000
  76 #define CS_1110         0xE0000000
  77 #define CS_1111         0xF0000000
  78
  79 #define BS_0000         0x00000000
  80 #define BS_0001         0x01000000
  81 #define BS_0010         0x02000000
  82 #define BS_0011         0x03000000
  83 #define BS_0100         0x04000000
  84 #define BS_0101         0x05000000
  85 #define BS_0110         0x06000000
  86 #define BS_0111         0x07000000
  87 #define BS_1000         0x08000000
  88 #define BS_1001         0x09000000
  89 #define BS_1010         0x0A000000
  90 #define BS_1011         0x0B000000
  91 #define BS_1100         0x0C000000
  92 #define BS_1101         0x0D000000
  93 #define BS_1110         0x0E000000
  94 #define BS_1111         0x0F000000
  95
  96 #define A10_AAAA        0x00000000
  97 #define A10_AAA0        0x00200000
  98 #define A10_AAA1        0x00300000
  99 #define A10_000A        0x00800000
 100 #define A10_0000        0x00A00000
 101 #define A10_0001        0x00B00000
 102 #define A10_111A        0x00C00000
 103 #define A10_1110        0x00E00000
 104 #define A10_1111        0x00F00000
 105
 106 #define RAS_0000        0x00000000
 107 #define RAS_0001        0x00040000
 108 #define RAS_1110        0x00080000
 109 #define RAS_1111        0x000C0000
 110
 111 #define CAS_0000        0x00000000
 112 #define CAS_0001        0x00010000
 113 #define CAS_1110        0x00020000
 114 #define CAS_1111        0x00030000
 115
 116 #define WE_0000         0x00000000
 117 #define WE_0001         0x00004000
 118 #define WE_1110         0x00008000
 119 #define WE_1111         0x0000C000
 120
 121 #define GPL4_0000       0x00000000
 122 #define GPL4_0001       0x00001000
 123 #define GPL4_1110       0x00002000
 124 #define GPL4_1111       0x00003000
 125
 126 #define GPL5_0000       0x00000000
 127 #define GPL5_0001       0x00000400
 128 #define GPL5_1110       0x00000800
 129 #define GPL5_1111       0x00000C00
 130 #define LOOP            0x00000080
 131
 132 #define EXEN            0x00000040
 133
 134 #define AMX_COL         0x00000000
 135 #define AMX_ROW         0x00000020
 136 #define AMX_MAR         0x00000030
 137
 138 #define NA              0x00000008
 139
 140 #define UTA             0x00000004
 141
 142 #define TODT            0x00000002
 143
 144 #define LAST            0x00000001
 145
 146 const uint sdram_table[0x40] = {
 147         /* RSS */
 148         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 149         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 150         CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 151         CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 152         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 153         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 154         _NOT_USED_, _NOT_USED_,
 155
 156         /* RBS */
 157         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 158         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 159         CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 160         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 161         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 162         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 163         CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
 164         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
 165         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 166         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 167
 168         /* WSS */
 169         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
 170         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
 171         CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
 172         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
 173         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 174
 175         /* WBS */
 176         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 177         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 178         CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
 179         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 180         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 181         CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 182         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 183         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 184         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 185         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 186         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 187
 188         /* UPT */
 189         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 190         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
 191         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
 192         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
 193         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
 194         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
 195         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 196         _NOT_USED_, _NOT_USED_,
 197
 198         /* EXC */
 199         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
 200         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
 201
 202         /* REG */
 203         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
 204         CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
 205 };
 206
 207 /* ------------------------------------------------------------------------- */
 208
 209
 210 /*
 211  * Check Board Identity:
 212  *
 213  * Test ETX ID string (ETX_xxx...)
 214  *
 215  * Return 1 always.
 216  */
 217
 218 int checkboard(void)
 219 {
 220 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
 221         printf ("NETVIA v1\n");
 222 #else
 223         printf ("NETVIA v2+\n");
 224 #endif
 225         return (0);
 226 }
 227
 228 /* ------------------------------------------------------------------------- */
 229
 230 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
 231 #define MAR_SDRAM_INIT          0x000000C8LU
 232
 233 #define MCR_OP(x)               ((unsigned long)((x) & 3) << (31-1))
 234 #define MCR_OP_MASK             MCR_OP(3)
 235
 236 #define MCR_UM(x)               ((unsigned long)((x) & 1) << (31 - 8))
 237 #define MCR_UM_MASK             MCR_UM(1)
 238 #define MCR_UM_UPMA             MCR_UM(0)
 239 #define MCR_UM_UPMB             MCR_UM(1)
 240
 241 #define MCR_MB(x)               ((unsigned long)((x) & 7) << (31 - 18))
 242 #define MCR_MB_MASK             MCR_MB(7)
 243 #define MCR_MB_CS(x)            MCR_MB(x)
 244
 245 #define MCR_MCLF(x)             ((unsigned long)((x) & 15) << (31 - 23))
 246 #define MCR_MCLF_MASK           MCR_MCLF(15)
 247
 248 phys_size_t initdram(int board_type)
 249 {
 250         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 251         volatile memctl8xx_t *memctl = &immap->im_memctl;
 252         long int size;
 253
 254         upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
 255
 256         /*
 257          * Preliminary prescaler for refresh
 258          */
 259         memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 260
 261         memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
 262
 263     /*
 264      * Map controller bank 3 to the SDRAM bank at preliminary address.
 265      */
 266         memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 267         memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 268
 269         memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE;  /* no refresh yet */
 270
 271         udelay(200);
 272
 273         /* perform SDRAM initialisation sequence */
 274         memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all                        */
 275         udelay(1);
 276         memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0)          */
 277         udelay(1);
 278         memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */
 279         udelay(1);
 280
 281         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 282
 283         udelay(1000);
 284
 285         memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
 286
 287         size = SDRAM_MAX_SIZE;
 288
 289         udelay(10000);
 290
 291         return (size);
 292 }
 293
 294 /* ------------------------------------------------------------------------- */
 295
 296 int misc_init_r(void)
 297 {
 298 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 299         last_er_val = 0xffffffff;
 300 #endif
 301         return(0);
 302 }
 303
 304 /* ------------------------------------------------------------------------- */
 305
 306 /* GP = general purpose, SP = special purpose (on chip peripheral) */
 307
 308 /* bits that can have a special purpose or can be configured as inputs/outputs */
 309 #define PA_GP_INMASK    0
 310 #define PA_GP_OUTMASK   (_BW(5) | _BWR(14, 15))
 311 #define PA_SP_MASK      (_BW(4) | _BWR(6, 13))
 312 #define PA_ODR_VAL      0
 313 #define PA_GP_OUTVAL    _BW(5)
 314 #define PA_SP_DIRVAL    0
 315
 316 #define PB_GP_INMASK    _B(28)
 317 #define PB_GP_OUTMASK   (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
 318 #define PB_SP_MASK      _BR(22, 25)
 319 #define PB_ODR_VAL      0
 320 #define PB_GP_OUTVAL    (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
 321 #define PB_SP_DIRVAL    0
 322
 323 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
 324
 325 #define PC_GP_INMASK    (_BWR(5, 7) | _BWR(9, 10) | _BW(13))
 326 #define PC_GP_OUTMASK   _BW(12)
 327 #define PC_SP_MASK      (_BW(4) | _BW(8))
 328 #define PC_SOVAL        0
 329 #define PC_INTVAL       0
 330 #define PC_GP_OUTVAL    0
 331 #define PC_SP_DIRVAL    0
 332
 333 #define PD_GP_INMASK    0
 334 #define PD_GP_OUTMASK   _BWR(3, 15)
 335 #define PD_SP_MASK      0
 336 #define PD_GP_OUTVAL    (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
 337 #define PD_SP_DIRVAL    0
 338
 339 #elif CONFIG_NETVIA_VERSION >= 2
 340
 341 #define PC_GP_INMASK    (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15))
 342 #define PC_GP_OUTMASK   (_BW(6) | _BW(12))
 343 #define PC_SP_MASK      (_BW(4) | _BW(8))
 344 #define PC_SOVAL        0
 345 #define PC_INTVAL       _BW(7)
 346 #define PC_GP_OUTVAL    (_BW(6) | _BW(12))
 347 #define PC_SP_DIRVAL    0
 348
 349 #define PD_GP_INMASK    0
 350 #define PD_GP_OUTMASK   _BWR(3, 15)
 351 #define PD_SP_MASK      0
 352 #define PD_GP_OUTVAL    (_BW(3) | _BW(5) | _BW(9) | _BW(11))
 353 #define PD_SP_DIRVAL    0
 354
 355 #else
 356 #error Unknown NETVIA board version.
 357 #endif
 358
 359 int board_early_init_f(void)
 360 {
 361         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 362         volatile iop8xx_t *ioport = &immap->im_ioport;
 363         volatile cpm8xx_t *cpm = &immap->im_cpm;
 364         volatile memctl8xx_t *memctl = &immap->im_memctl;
 365
 366         /* DSP0 chip select */
 367         memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
 368         memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 369
 370         /* DSP1 chip select */
 371         memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
 372         memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 373
 374         /* FPGA chip select */
 375         memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK);
 376         memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 377
 378 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 379         /* NAND chip select */
 380         memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
 381         memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 382
 383         /* kill this chip select */
 384         memctl->memc_br2 &= ~BR_V;      /* invalid */
 385
 386         /* external reg chip select */
 387         memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
 388         memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
 389 #endif
 390
 391         ioport->iop_padat       = PA_GP_OUTVAL;
 392         ioport->iop_paodr       = PA_ODR_VAL;
 393         ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
 394         ioport->iop_papar       = PA_SP_MASK;
 395
 396         cpm->cp_pbdat           = PB_GP_OUTVAL;
 397         cpm->cp_pbodr           = PB_ODR_VAL;
 398         cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
 399         cpm->cp_pbpar           = PB_SP_MASK;
 400
 401         ioport->iop_pcdat       = PC_GP_OUTVAL;
 402         ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
 403         ioport->iop_pcso        = PC_SOVAL;
 404         ioport->iop_pcint       = PC_INTVAL;
 405         ioport->iop_pcpar       = PC_SP_MASK;
 406
 407         ioport->iop_pddat       = PD_GP_OUTVAL;
 408         ioport->iop_pddir       = PD_GP_OUTMASK | PD_SP_DIRVAL;
 409         ioport->iop_pdpar       = PD_SP_MASK;
 410
 411 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 412         /* external register init */
 413         *(volatile uint *)ER_BASE = 0xFFFFFFFF;
 414 #endif
 415
 416         return 0;
 417 }