board/nx823/nx823.c

   1 /*
   2  * (C) Copyright 2001
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2001-2002
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <malloc.h>
  29 #include <mpc8xx.h>
  30 #include <net.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static long int dram_size (long int, long int *, long int);
  35
  36 #define _NOT_USED_      0xFFFFFFFF
  37
  38 const uint sdram_table[] = {
  39 #if (MPC8XX_SPEED <= 50000000L)
  40         /*
  41          * Single Read. (Offset 0 in UPMA RAM)
  42          */
  43         0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
  44         0xFFFFFFFF,
  45
  46         /*
  47          * SDRAM Initialization (offset 5 in UPMA RAM)
  48          *
  49          * This is no UPM entry point. The following definition uses
  50          * the remaining space to establish an initialization
  51          * sequence, which is executed by a RUN command.
  52          *
  53          */
  54         0x1FE7F434, 0xEFABE834, 0x1FA7D435,
  55
  56         /*
  57          * Burst Read. (Offset 8 in UPMA RAM)
  58          */
  59         0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
  60         0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
  61         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  62         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  63
  64         /*
  65          * Single Write. (Offset 18 in UPMA RAM)
  66          */
  67         0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
  68         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  69
  70         /*
  71          * Burst Write. (Offset 20 in UPMA RAM)
  72          */
  73         0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
  74         0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  75         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  76         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  77
  78         /*
  79          * Refresh  (Offset 30 in UPMA RAM)
  80          */
  81         0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
  82         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  83         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  84
  85         /*
  86          * Exception. (Offset 3c in UPMA RAM)
  87          */
  88         0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
  89 #else
  90
  91         /*
  92          * Single Read. (Offset 0 in UPMA RAM)
  93          */
  94         0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
  95         0x1FF7F447,
  96
  97         /*
  98          * SDRAM Initialization (offset 5 in UPMA RAM)
  99          *
 100          * This is no UPM entry point. The following definition uses
 101          * the remaining space to establish an initialization
 102          * sequence, which is executed by a RUN command.
 103          *
 104          */
 105         0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
 106
 107         /*
 108          * Burst Read. (Offset 8 in UPMA RAM)
 109          */
 110         0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
 111         0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
 112         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 113         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 114
 115         /*
 116          * Single Write. (Offset 18 in UPMA RAM)
 117          */
 118         0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
 119         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 120
 121         /*
 122          * Burst Write. (Offset 20 in UPMA RAM)
 123          */
 124         0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
 125         0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
 126         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 127         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 128
 129         /*
 130          * Refresh  (Offset 30 in UPMA RAM)
 131          */
 132         0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
 133         0xFFFFFC84, 0xFFFFFC07,
 134         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 135         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 136
 137         /*
 138          * Exception. (Offset 3c in UPMA RAM)
 139          */
 140         0x7FFFFC07,             /* last */
 141         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 142 #endif
 143 };
 144
 145 /* ------------------------------------------------------------------------- */
 146
 147
 148 /*
 149  * Check Board Identity:
 150  *
 151  */
 152
 153 int checkboard (void)
 154 {
 155         printf ("Board: Nexus NX823");
 156         return (0);
 157 }
 158
 159 /* ------------------------------------------------------------------------- */
 160
 161 phys_size_t initdram (int board_type)
 162 {
 163         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 164         volatile memctl8xx_t *memctl = &immap->im_memctl;
 165         long int size_b0, size_b1, size8, size9;
 166
 167         upmconfig (UPMA, (uint *) sdram_table,
 168                    sizeof (sdram_table) / sizeof (uint));
 169
 170         /*
 171          * Up to 2 Banks of 64Mbit x 2 devices
 172          * Initial builds only have 1
 173          */
 174         memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
 175         memctl->memc_mar = 0x00000088;
 176
 177         /*
 178          * Map controller SDRAM bank 0
 179          */
 180         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 181         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 182         memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 183         udelay (200);
 184
 185         /*
 186          * Map controller SDRAM bank 1
 187          */
 188         memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 189         memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 190
 191         /*
 192          * Perform SDRAM initializsation sequence
 193          */
 194         memctl->memc_mcr = 0x80002105;  /* SDRAM bank 0 */
 195         udelay (1);
 196         memctl->memc_mcr = 0x80002230;  /* SDRAM bank 0 - execute twice */
 197         udelay (1);
 198
 199         memctl->memc_mcr = 0x80004105;  /* SDRAM bank 1 */
 200         udelay (1);
 201         memctl->memc_mcr = 0x80004230;  /* SDRAM bank 1 - execute twice */
 202         udelay (1);
 203
 204         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 205         udelay (1000);
 206
 207         /*
 208          * Preliminary prescaler for refresh (depends on number of
 209          * banks): This value is selected for four cycles every 62.4 us
 210          * with two SDRAM banks or four cycles every 31.2 us with one
 211          * bank. It will be adjusted after memory sizing.
 212          */
 213         memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 214
 215         memctl->memc_mar = 0x00000088;
 216
 217
 218         /*
 219          * Check Bank 0 Memory Size for re-configuration
 220          *
 221          * try 8 column mode
 222          */
 223         size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
 224                            SDRAM_MAX_SIZE);
 225
 226         udelay (1000);
 227
 228         /*
 229          * try 9 column mode
 230          */
 231         size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
 232                            SDRAM_MAX_SIZE);
 233
 234         if (size8 < size9) {    /* leave configuration at 9 columns     */
 235                 size_b0 = size9;
 236 /*      debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
 237         } else {                /* back to 8 columns                    */
 238                 size_b0 = size8;
 239                 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 240                 udelay (500);
 241 /*      debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
 242         }
 243
 244         /*
 245          * Check Bank 1 Memory Size
 246          * use current column settings
 247          * [9 column SDRAM may also be used in 8 column mode,
 248          *  but then only half the real size will be used.]
 249          */
 250         size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
 251                              SDRAM_MAX_SIZE);
 252 /*      debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);  */
 253
 254         udelay (1000);
 255
 256         /*
 257          * Adjust refresh rate depending on SDRAM type, both banks
 258          * For types > 128 MBit leave it at the current (fast) rate
 259          */
 260         if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 261                 /* reduce to 15.6 us (62.4 us / quad) */
 262                 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 263                 udelay (1000);
 264         }
 265
 266         /*
 267          * Final mapping: map bigger bank first
 268          */
 269         if (size_b1 > size_b0) {        /* SDRAM Bank 1 is bigger - map first   */
 270
 271                 memctl->memc_or2 =
 272                         ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 273                 memctl->memc_br2 =
 274                         (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 275
 276                 if (size_b0 > 0) {
 277                         /*
 278                          * Position Bank 0 immediately above Bank 1
 279                          */
 280                         memctl->memc_or1 =
 281                                 ((-size_b0) & 0xFFFF0000) |
 282                                 CONFIG_SYS_OR_TIMING_SDRAM;
 283                         memctl->memc_br1 =
 284                                 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
 285                                  BR_V)
 286                                 + size_b1;
 287                 } else {
 288                         unsigned long reg;
 289
 290                         /*
 291                          * No bank 0
 292                          *
 293                          * invalidate bank
 294                          */
 295                         memctl->memc_br1 = 0;
 296
 297                         /* adjust refresh rate depending on SDRAM type, one bank */
 298                         reg = memctl->memc_mptpr;
 299                         reg >>= 1;      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 300                         memctl->memc_mptpr = reg;
 301                 }
 302
 303         } else {                /* SDRAM Bank 0 is bigger - map first   */
 304
 305                 memctl->memc_or1 =
 306                         ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 307                 memctl->memc_br1 =
 308                         (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 309
 310                 if (size_b1 > 0) {
 311                         /*
 312                          * Position Bank 1 immediately above Bank 0
 313                          */
 314                         memctl->memc_or2 =
 315                                 ((-size_b1) & 0xFFFF0000) |
 316                                 CONFIG_SYS_OR_TIMING_SDRAM;
 317                         memctl->memc_br2 =
 318                                 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
 319                                  BR_V)
 320                                 + size_b0;
 321                 } else {
 322                         unsigned long reg;
 323
 324                         /*
 325                          * No bank 1
 326                          *
 327                          * invalidate bank
 328                          */
 329                         memctl->memc_br2 = 0;
 330
 331                         /* adjust refresh rate depending on SDRAM type, one bank */
 332                         reg = memctl->memc_mptpr;
 333                         reg >>= 1;      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 334                         memctl->memc_mptpr = reg;
 335                 }
 336         }
 337
 338         udelay (10000);
 339
 340         return (size_b0 + size_b1);
 341 }
 342
 343 /* ------------------------------------------------------------------------- */
 344
 345 /*
 346  * Check memory range for valid RAM. A simple memory test determines
 347  * the actually available RAM size between addresses `base' and
 348  * `base + maxsize'. Some (not all) hardware errors are detected:
 349  * - short between address lines
 350  * - short between data lines
 351  */
 352
 353 static long int dram_size (long int mamr_value, long int *base,
 354                            long int maxsize)
 355 {
 356         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 357         volatile memctl8xx_t *memctl = &immap->im_memctl;
 358
 359         memctl->memc_mamr = mamr_value;
 360
 361         return (get_ram_size (base, maxsize));
 362 }
 363
 364 int misc_init_r (void)
 365 {
 366         int i;
 367         char tmp[50];
 368         uchar ethaddr[6];
 369         bd_t *bd = gd->bd;
 370         ulong *my_sernum = (unsigned long *)&bd->bi_sernum;
 371
 372         /* load unique serial number */
 373         for (i = 0; i < 8; ++i)
 374                 bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i);
 375
 376         /* save env variables according to sernum */
 377         sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
 378         setenv ("serial#", tmp);
 379
 380         if (!eth_getenv_enetaddr("ethaddr", ethaddr)) {
 381                 ethaddr[0] = 0x10;
 382                 ethaddr[1] = 0x20;
 383                 ethaddr[2] = 0x30;
 384                 ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
 385                 ethaddr[4] = bd->bi_sernum[5];
 386                 ethaddr[5] = bd->bi_sernum[6];
 387         }
 388
 389         return 0;
 390 }