4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 static void wait_for_bb (void);
29 static u16
wait_for_pin (void);
30 static void flush_fifo(void);
32 void i2c_init (int speed
, int slaveadd
)
34 int psc
, fsscll
, fssclh
;
35 int hsscll
= 0, hssclh
= 0;
38 /* Only handle standard, fast and high speeds */
39 if ((speed
!= OMAP_I2C_STANDARD
) &&
40 (speed
!= OMAP_I2C_FAST_MODE
) &&
41 (speed
!= OMAP_I2C_HIGH_SPEED
)) {
42 printf("Error : I2C unsupported speed %d\n", speed
);
46 psc
= I2C_IP_CLK
/ I2C_INTERNAL_SAMPLING_CLK
;
48 if (psc
< I2C_PSC_MIN
) {
49 printf("Error : I2C unsupported prescalar %d\n", psc
);
53 if (speed
== OMAP_I2C_HIGH_SPEED
) {
56 /* For first phase of HS mode */
57 fsscll
= fssclh
= I2C_INTERNAL_SAMPLING_CLK
/
58 (2 * OMAP_I2C_FAST_MODE
);
60 fsscll
-= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
;
61 fssclh
-= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
;
62 if (((fsscll
< 0) || (fssclh
< 0)) ||
63 ((fsscll
> 255) || (fssclh
> 255))) {
64 printf("Error : I2C initializing first phase clock\n");
68 /* For second phase of HS mode */
69 hsscll
= hssclh
= I2C_INTERNAL_SAMPLING_CLK
/ (2 * speed
);
71 hsscll
-= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
;
72 hssclh
-= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
;
73 if (((fsscll
< 0) || (fssclh
< 0)) ||
74 ((fsscll
> 255) || (fssclh
> 255))) {
75 printf("Error : I2C initializing second phase clock\n");
79 scll
= (unsigned int)hsscll
<< 8 | (unsigned int)fsscll
;
80 sclh
= (unsigned int)hssclh
<< 8 | (unsigned int)fssclh
;
83 /* Standard and fast speed */
84 fsscll
= fssclh
= I2C_INTERNAL_SAMPLING_CLK
/ (2 * speed
);
86 fsscll
-= I2C_FASTSPEED_SCLL_TRIM
;
87 fssclh
-= I2C_FASTSPEED_SCLH_TRIM
;
88 if (((fsscll
< 0) || (fssclh
< 0)) ||
89 ((fsscll
> 255) || (fssclh
> 255))) {
90 printf("Error : I2C initializing clock\n");
94 scll
= (unsigned int)fsscll
;
95 sclh
= (unsigned int)fssclh
;
98 writew(0x2, I2C_SYSC
); /* for ES2 after soft reset */
100 writew(0x0, I2C_SYSC
); /* will probably self clear but */
102 if (readw (I2C_CON
) & I2C_CON_EN
) {
107 writew(psc
, I2C_PSC
);
108 writew(scll
, I2C_SCLL
);
109 writew(sclh
, I2C_SCLH
);
112 writew (slaveadd
, I2C_OA
);
113 writew (I2C_CON_EN
, I2C_CON
);
115 /* have to enable intrrupts or OMAP i2c module doesn't work */
116 writew (I2C_IE_XRDY_IE
| I2C_IE_RRDY_IE
| I2C_IE_ARDY_IE
|
117 I2C_IE_NACK_IE
| I2C_IE_AL_IE
, I2C_IE
);
120 writew (0xFFFF, I2C_STAT
);
124 static int i2c_read_byte (u8 devaddr
, u8 regoffset
, u8
* value
)
129 /* wait until bus not busy */
134 /* set slave address */
135 writew (devaddr
, I2C_SA
);
136 /* no stop bit needed here */
137 writew (I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_TRX
, I2C_CON
);
139 status
= wait_for_pin ();
141 if (status
& I2C_STAT_XRDY
) {
142 /* Important: have to use byte access */
143 writeb (regoffset
, I2C_DATA
);
145 if (readw (I2C_STAT
) & I2C_STAT_NACK
) {
153 /* free bus, otherwise we can't use a combined transction */
155 while (readw (I2C_STAT
) || (readw (I2C_CON
) & I2C_CON_MST
)) {
157 /* Have to clear pending interrupt to clear I2C_STAT */
158 writew (0xFFFF, I2C_STAT
);
162 /* set slave address */
163 writew (devaddr
, I2C_SA
);
164 /* read one byte from slave */
166 /* need stop bit here */
167 writew (I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_STP
,
170 status
= wait_for_pin ();
171 if (status
& I2C_STAT_RRDY
) {
172 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
173 *value
= readb (I2C_DATA
);
175 *value
= readw (I2C_DATA
);
183 writew (I2C_CON_EN
, I2C_CON
);
184 while (readw (I2C_STAT
)
185 || (readw (I2C_CON
) & I2C_CON_MST
)) {
187 writew (0xFFFF, I2C_STAT
);
192 writew (0xFFFF, I2C_STAT
);
197 static int i2c_write_byte (u8 devaddr
, u8 regoffset
, u8 value
)
202 /* wait until bus not busy */
207 /* set slave address */
208 writew (devaddr
, I2C_SA
);
209 /* stop bit needed here */
210 writew (I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_TRX
|
211 I2C_CON_STP
, I2C_CON
);
213 /* wait until state change */
214 status
= wait_for_pin ();
216 if (status
& I2C_STAT_XRDY
) {
217 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
218 /* send out 1 byte */
219 writeb (regoffset
, I2C_DATA
);
220 writew (I2C_STAT_XRDY
, I2C_STAT
);
222 status
= wait_for_pin ();
223 if ((status
& I2C_STAT_XRDY
)) {
224 /* send out next 1 byte */
225 writeb (value
, I2C_DATA
);
226 writew (I2C_STAT_XRDY
, I2C_STAT
);
231 /* send out two bytes */
232 writew ((value
<< 8) + regoffset
, I2C_DATA
);
234 /* must have enough delay to allow BB bit to go low */
236 if (readw (I2C_STAT
) & I2C_STAT_NACK
) {
246 writew (I2C_CON_EN
, I2C_CON
);
247 while ((stat
= readw (I2C_STAT
)) || (readw (I2C_CON
) & I2C_CON_MST
)) {
249 /* have to read to clear intrrupt */
250 writew (0xFFFF, I2C_STAT
);
251 if(--eout
== 0) /* better leave with error than hang */
256 writew (0xFFFF, I2C_STAT
);
261 static void flush_fifo(void)
264 /* note: if you try and read data when its not there or ready
265 * you get a bus error
268 stat
= readw(I2C_STAT
);
269 if(stat
== I2C_STAT_RRDY
){
270 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
275 writew(I2C_STAT_RRDY
,I2C_STAT
);
282 int i2c_probe (uchar chip
)
284 int res
= 1; /* default = fail */
286 if (chip
== readw (I2C_OA
)) {
290 /* wait until bus not busy */
293 /* try to read one byte */
295 /* set slave address */
296 writew (chip
, I2C_SA
);
297 /* stop bit needed here */
298 writew (I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_STP
, I2C_CON
);
299 /* enough delay for the NACK bit set */
302 if (!(readw (I2C_STAT
) & I2C_STAT_NACK
)) {
303 res
= 0; /* success case */
305 writew(0xFFFF, I2C_STAT
);
307 writew(0xFFFF, I2C_STAT
); /* failue, clear sources*/
308 writew (readw (I2C_CON
) | I2C_CON_STP
, I2C_CON
); /* finish up xfer */
313 writew (0, I2C_CNT
); /* don't allow any more data in...we don't want it.*/
314 writew(0xFFFF, I2C_STAT
);
318 int i2c_read (uchar chip
, uint addr
, int alen
, uchar
* buffer
, int len
)
323 printf ("I2C read: addr len %d not supported\n", alen
);
327 if (addr
+ len
> 256) {
328 printf ("I2C read: address out of range\n");
332 for (i
= 0; i
< len
; i
++) {
333 if (i2c_read_byte (chip
, addr
+ i
, &buffer
[i
])) {
334 printf ("I2C read: I/O error\n");
335 i2c_init (CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
343 int i2c_write (uchar chip
, uint addr
, int alen
, uchar
* buffer
, int len
)
348 printf ("I2C read: addr len %d not supported\n", alen
);
352 if (addr
+ len
> 256) {
353 printf ("I2C read: address out of range\n");
357 for (i
= 0; i
< len
; i
++) {
358 if (i2c_write_byte (chip
, addr
+ i
, buffer
[i
])) {
359 printf ("I2C read: I/O error\n");
360 i2c_init (CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
368 static void wait_for_bb (void)
373 writew(0xFFFF, I2C_STAT
); /* clear current interruts...*/
374 while ((stat
= readw (I2C_STAT
) & I2C_STAT_BB
) && timeout
--) {
375 writew (stat
, I2C_STAT
);
380 printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
383 writew(0xFFFF, I2C_STAT
); /* clear delayed stuff*/
386 static u16
wait_for_pin (void)
393 status
= readw (I2C_STAT
);
395 (I2C_STAT_ROVR
| I2C_STAT_XUDF
| I2C_STAT_XRDY
|
396 I2C_STAT_RRDY
| I2C_STAT_ARDY
| I2C_STAT_NACK
|
397 I2C_STAT_AL
)) && timeout
--);
400 printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
402 writew(0xFFFF, I2C_STAT
);