board/amcc/sequoia/cmd_sequoia.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <command.h>
  27 #include <i2c.h>
  28 #include <asm/io.h>
  29
  30 /*
  31  * There are 2 versions of production Sequoia & Rainier platforms.
  32  * The primary difference is the reference clock. Those with
  33  * 33333333 reference clocks will also have 667MHz rated
  34  * processors. Not enough differences to have unique clock
  35  * settings.
  36  *
  37  * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
  38  * values are independent of the rest of the clock settings.
  39  *
  40  * All Sequoias & Rainiers select from two possible EEPROMs in Boot
  41  * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
  42  * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
  43  * the only value affected for a 33MHz PCI and simply needs a | 0x08.
  44  */
  45
  46 #define NAND_COMPATIBLE 0x01
  47 #define NOR_COMPATIBLE  0x02
  48
  49 /* check with Stefan on CFG_I2C_EEPROM_ADDR */
  50 #define I2C_EEPROM_ADDR 0x52
  51
  52 static char *config_labels[] = {
  53         "CPU: 333 PLB: 133 OPB: 66 EBC: 66",
  54         "CPU: 333 PLB: 166 OPB: 83 EBC: 55",
  55         "CPU: 400 PLB: 133 OPB: 66 EBC: 66",
  56         "CPU: 400 PLB: 160 OPB: 80 EBC: 53",
  57         "CPU: 416 PLB: 166 OPB: 83 EBC: 55",
  58         "CPU: 500 PLB: 166 OPB: 83 EBC: 55",
  59         "CPU: 533 PLB: 133 OPB: 66 EBC: 66",
  60         "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
  61         "CPU: 667 PLB: 166 OPB: 83 EBC: 55",
  62         NULL
  63 };
  64
  65 static u8 boot_configs[][17] = {
  66         {
  67                 (NOR_COMPATIBLE),
  68                 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
  69                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  70         },
  71         {
  72                 (NAND_COMPATIBLE | NOR_COMPATIBLE),
  73                 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
  74                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  75         },
  76         {
  77                 (NOR_COMPATIBLE),
  78                 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
  79                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  80         },
  81         {
  82                 (NOR_COMPATIBLE),
  83                 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
  84                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  85         },
  86         {
  87                 (NAND_COMPATIBLE | NOR_COMPATIBLE),
  88                 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
  89                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  90         },
  91         {
  92                 (NAND_COMPATIBLE | NOR_COMPATIBLE),
  93                 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
  94                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  95         },
  96         {
  97                 (NOR_COMPATIBLE),
  98                 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
  99                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 100         },
 101         {
 102                 (NOR_COMPATIBLE),
 103                 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
 104                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 105         },
 106         {
 107                 (NAND_COMPATIBLE | NOR_COMPATIBLE),
 108                 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
 109                 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 110         },
 111         {
 112                 0,
 113                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 114         }
 115 };
 116
 117 /*
 118  * Bytes 6,8,9,11 change for NAND boot
 119  */
 120 static u8 nand_boot[] = {
 121         0xd0,  0xa0, 0x68, 0x58
 122 };
 123
 124 static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 125 {
 126         u8 *buf, bNAND;
 127         int x, y, nbytes, selcfg;
 128         extern char console_buffer[];
 129
 130         if (argc < 2) {
 131                 printf("Usage:\n%s\n", cmdtp->usage);
 132                 return 1;
 133         }
 134
 135         if ((strcmp(argv[1], "nor") != 0) &&
 136             (strcmp(argv[1], "nand") != 0)) {
 137                 printf("Unsupported boot-device - only nor|nand support\n");
 138                 return 1;
 139         }
 140
 141         /* set the nand flag based on provided input */
 142         if ((strcmp(argv[1], "nand") == 0))
 143                 bNAND = 1;
 144         else
 145                 bNAND = 0;
 146
 147         printf("Available configurations: \n\n");
 148
 149         if (bNAND) {
 150                 for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
 151                         /* filter on nand compatible */
 152                         if (boot_configs[x][0] & NAND_COMPATIBLE) {
 153                                 printf(" %d - %s\n", (y+1), config_labels[x]);
 154                                 y++;
 155                         }
 156                 }
 157         } else {
 158                 for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
 159                         /* filter on nor compatible */
 160                         if (boot_configs[x][0] & NOR_COMPATIBLE) {
 161                                 printf(" %d - %s\n", (y+1), config_labels[x]);
 162                                 y++;
 163                         }
 164                 }
 165         }
 166
 167         do {
 168                 nbytes = readline(" Selection [1-x / quit]: ");
 169
 170                 if (nbytes) {
 171                         if (strcmp(console_buffer, "quit") == 0)
 172                                 return 0;
 173                         selcfg = simple_strtol(console_buffer, NULL, 10);
 174                         if ((selcfg < 1) || (selcfg > y))
 175                                 nbytes = 0;
 176                 }
 177         } while (nbytes == 0);
 178
 179
 180         y = (selcfg - 1);
 181
 182         for (x = 0; boot_configs[x][0] != 0; x++) {
 183                 if (bNAND) {
 184                         if (boot_configs[x][0] & NAND_COMPATIBLE) {
 185                                 if (y > 0)
 186                                         y--;
 187                                 else if (y < 1)
 188                                         break;
 189                         }
 190                 } else {
 191                         if (boot_configs[x][0] & NOR_COMPATIBLE) {
 192                                 if (y > 0)
 193                                         y--;
 194                                 else if (y < 1)
 195                                         break;
 196                         }
 197                 }
 198         }
 199
 200         buf = &boot_configs[x][1];
 201
 202         if (bNAND) {
 203                 buf[6] = nand_boot[0];
 204                 buf[8] = nand_boot[1];
 205                 buf[9] = nand_boot[2];
 206                 buf[11] = nand_boot[3];
 207         }
 208
 209         /* check CPLD register +5 for PCI 66MHz flag */
 210         if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
 211                 /*
 212                  * PLB-to-PCI divisor = 3 for 33MHz sync PCI
 213                  * instead of 2 for 66MHz systems
 214                  */
 215                 buf[5] |= 0x08;
 216
 217         if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
 218                 printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
 219         udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 220
 221         printf("Done\n");
 222         printf("Please power-cycle the board for the changes to take effect\n");
 223
 224         return 0;
 225 }
 226
 227 U_BOOT_CMD(
 228         bootstrap,      2,      0,      do_bootstrap,
 229         "bootstrap - program the I2C bootstrap EEPROM\n",
 230         "<nand|nor> - strap to boot from NAND or NOR flash\n"
 231         );