board/atmel/at91cap9adk/nand.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <asm/arch/at91cap9.h>
  29 #include <asm/arch/gpio.h>
  30 #include <asm/arch/at91_pio.h>
  31
  32 #include <nand.h>
  33
  34 /*
  35  *      hardware specific access to control-lines
  36  */
  37 #define MASK_ALE        (1 << 21)       /* our ALE is AD21 */
  38 #define MASK_CLE        (1 << 22)       /* our CLE is AD22 */
  39
  40 static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
  41 {
  42         struct nand_chip *this = mtd->priv;
  43         ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  44
  45         IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
  46         switch (cmd) {
  47         case NAND_CTL_SETCLE:
  48                 IO_ADDR_W |= MASK_CLE;
  49                 break;
  50         case NAND_CTL_SETALE:
  51                 IO_ADDR_W |= MASK_ALE;
  52                 break;
  53         case NAND_CTL_CLRNCE:
  54                 at91_set_gpio_value(AT91_PIN_PD15, 1);
  55                 break;
  56         case NAND_CTL_SETNCE:
  57                 at91_set_gpio_value(AT91_PIN_PD15, 0);
  58                 break;
  59         }
  60         this->IO_ADDR_W = (void *) IO_ADDR_W;
  61 }
  62
  63 int board_nand_init(struct nand_chip *nand)
  64 {
  65         nand->eccmode = NAND_ECC_SOFT;
  66 #ifdef CFG_NAND_DBW_16
  67         nand->options = NAND_BUSWIDTH_16;
  68 #endif
  69         nand->hwcontrol = at91cap9adk_nand_hwcontrol;
  70         nand->chip_delay = 20;
  71
  72         return 0;
  73 }