board/pcippc2/cpc710_init_ram.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <asm/io.h>
  27
  28 #include "pcippc2.h"
  29 #include "i2c.h"
  30
  31 typedef struct cpc710_mem_org_s {
  32         u8 rows;
  33         u8 cols;
  34         u8 banks2;
  35         u8 org;
  36 } cpc710_mem_org_t;
  37
  38 static int cpc710_compute_mcer (u32 * mcer,
  39                                 unsigned long *size, unsigned int sdram);
  40 static int cpc710_eeprom_checksum (unsigned int sdram);
  41 static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset);
  42
  43 static u32 cpc710_mcer_mem[] = {
  44         0x000003f3,             /* 18 lines,    4 Mb */
  45         0x000003e3,             /* 19 lines,    8 Mb */
  46         0x000003c3,             /* 20 lines,   16 Mb */
  47         0x00000383,             /* 21 lines,   32 Mb */
  48         0x00000303,             /* 22 lines,   64 Mb */
  49         0x00000203,             /* 23 lines,  128 Mb */
  50         0x00000003,             /* 24 lines,  256 Mb */
  51         0x00000002,             /* 25 lines,  512 Mb */
  52         0x00000001              /* 26 lines, 1024 Mb */
  53 };
  54 static cpc710_mem_org_t cpc710_mem_org[] = {
  55         {0x0c, 0x09, 0x02, 0x00},       /* 0000: 12/ 9/2 */
  56         {0x0d, 0x09, 0x02, 0x00},       /* 0000: 13/ 9/2 */
  57         {0x0d, 0x0a, 0x02, 0x00},       /* 0000: 13/10/2 */
  58         {0x0d, 0x0b, 0x02, 0x00},       /* 0000: 13/11/2 */
  59         {0x0d, 0x0c, 0x02, 0x00},       /* 0000: 13/12/2 */
  60         {0x0e, 0x0c, 0x02, 0x00},       /* 0000: 14/12/2 */
  61         {0x0b, 0x08, 0x02, 0x01},       /* 0001: 11/ 8/2 */
  62         {0x0b, 0x09, 0x01, 0x02},       /* 0010: 11/ 9/1 */
  63         {0x0b, 0x0a, 0x01, 0x03},       /* 0011: 11/10/1 */
  64         {0x0c, 0x08, 0x02, 0x04},       /* 0100: 12/ 8/2 */
  65         {0x0c, 0x0a, 0x02, 0x05},       /* 0101: 12/10/2 */
  66         {0x0d, 0x08, 0x01, 0x06},       /* 0110: 13/ 8/1 */
  67         {0x0d, 0x08, 0x02, 0x07},       /* 0111: 13/ 8/2 */
  68         {0x0d, 0x09, 0x01, 0x08},       /* 1000: 13/ 9/1 */
  69         {0x0d, 0x0a, 0x01, 0x09},       /* 1001: 13/10/1 */
  70         {0x0b, 0x08, 0x01, 0x0a},       /* 1010: 11/ 8/1 */
  71         {0x0c, 0x08, 0x01, 0x0b},       /* 1011: 12/ 8/1 */
  72         {0x0c, 0x09, 0x01, 0x0c},       /* 1100: 12/ 9/1 */
  73         {0x0e, 0x09, 0x02, 0x0d},       /* 1101: 14/ 9/2 */
  74         {0x0e, 0x0a, 0x02, 0x0e},       /* 1110: 14/10/2 */
  75         {0x0e, 0x0b, 0x02, 0x0f}        /* 1111: 14/11/2 */
  76 };
  77
  78 unsigned long cpc710_ram_init (void)
  79 {
  80         unsigned long memsize = 0;
  81         unsigned long bank_size;
  82         u32 mcer;
  83
  84 #ifndef CFG_RAMBOOT
  85         /* Clear memory banks
  86          */
  87         out32 (REG (SDRAM0, MCER0), 0);
  88         out32 (REG (SDRAM0, MCER1), 0);
  89         out32 (REG (SDRAM0, MCER2), 0);
  90         out32 (REG (SDRAM0, MCER3), 0);
  91         out32 (REG (SDRAM0, MCER4), 0);
  92         out32 (REG (SDRAM0, MCER5), 0);
  93         out32 (REG (SDRAM0, MCER6), 0);
  94         out32 (REG (SDRAM0, MCER7), 0);
  95         iobarrier_rw ();
  96
  97         /* Disable memory
  98          */
  99         out32 (REG (SDRAM0, MCCR), 0x13b06000);
 100         iobarrier_rw ();
 101 #endif
 102
 103         /* Only the first memory bank is initialised now
 104          */
 105         if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) {
 106                 puts ("Unsupported SDRAM type !\n");
 107                 hang ();
 108         }
 109         memsize += bank_size;
 110 #ifndef CFG_RAMBOOT
 111         /* Enable bank, zero start
 112          */
 113         out32 (REG (SDRAM0, MCER0), mcer | 0x80000000);
 114         iobarrier_rw ();
 115 #endif
 116
 117 #ifndef CFG_RAMBOOT
 118         /* Enable memory
 119          */
 120         out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000);
 121
 122         /* Wait until initialisation finished
 123          */
 124         while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) {
 125                 iobarrier_rw ();
 126         }
 127
 128         /* Clear Memory Error Status and Address registers
 129          */
 130         out32 (REG (SDRAM0, MESR), 0);
 131         out32 (REG (SDRAM0, MEAR), 0);
 132         iobarrier_rw ();
 133
 134         /* ECC is not configured now
 135          */
 136 #endif
 137
 138         /* Memory size counter
 139          */
 140         out32 (REG (CPC0, RGBAN1), memsize);
 141
 142         return memsize;
 143 }
 144
 145 static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram)
 146 {
 147         u8 rows;
 148         u8 cols;
 149         u8 banks2;
 150         unsigned int lines;
 151         u32 mc = 0;
 152         unsigned int i;
 153         cpc710_mem_org_t *org = 0;
 154
 155         if (!i2c_reset ()) {
 156                 puts ("Can't reset I2C!\n");
 157                 hang ();
 158         }
 159
 160         if (!cpc710_eeprom_checksum (sdram)) {
 161                 puts ("Invalid EEPROM checksum !\n");
 162                 hang ();
 163         }
 164
 165         rows = cpc710_eeprom_read (sdram, 3);
 166         cols = cpc710_eeprom_read (sdram, 4);
 167         /* Can be 2 or 4 banks; divide by 2
 168          */
 169         banks2 = cpc710_eeprom_read (sdram, 17) / 2;
 170
 171         lines = rows + cols + banks2;
 172
 173         if (lines < 18 || lines > 26) {
 174                 /* Unsupported configuration
 175                  */
 176                 return 0;
 177         }
 178
 179         mc |= cpc710_mcer_mem[lines - 18] << 6;
 180
 181         for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t);
 182              i++) {
 183                 cpc710_mem_org_t *corg = cpc710_mem_org + i;
 184
 185                 if (corg->rows == rows && corg->cols == cols
 186                     && corg->banks2 == banks2) {
 187                         org = corg;
 188
 189                         break;
 190                 }
 191         }
 192
 193         if (!org) {
 194                 /* Unsupported configuration
 195                  */
 196                 return 0;
 197         }
 198
 199         mc |= (u32) org->org << 2;
 200
 201         /* Supported configuration
 202          */
 203         *mcer = mc;
 204         *size = 1l << (lines + 4);
 205
 206         return 1;
 207 }
 208
 209 static int cpc710_eeprom_checksum (unsigned int sdram)
 210 {
 211         u8 sum = 0;
 212         unsigned int i;
 213
 214         for (i = 0; i < 63; i++) {
 215                 sum += cpc710_eeprom_read (sdram, i);
 216         }
 217
 218         return sum == cpc710_eeprom_read (sdram, 63);
 219 }
 220
 221 static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset)
 222 {
 223         u8 dev = (sdram << 1) | 0xa0;
 224         u8 data;
 225
 226         if (!i2c_read_byte (&data, dev, offset)) {
 227                 puts ("I2C error !\n");
 228                 hang ();
 229         }
 230
 231         return data;
 232 }