board/pcippc2/cpc710_pci.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <pci.h>
  28
  29 #include "hardware.h"
  30 #include "pcippc2.h"
  31
  32 struct pci_controller local_hose, cpci_hose;
  33
  34 static u32      cpc710_mapped_ram;
  35
  36   /* Enable PCI retry timeouts
  37    */
  38 void cpc710_pci_enable_timeout (void)
  39 {
  40   out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
  41   iobarrier_rw();
  42   out32(BRIDGE(LOCAL, CFGDATA), 0x32000000);
  43   iobarrier_rw();
  44
  45   out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
  46   iobarrier_rw();
  47   out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
  48   iobarrier_rw();
  49 }
  50
  51 void cpc710_pci_init (void)
  52 {
  53   u32                   sdram_size = pcippc2_sdram_size();
  54
  55   cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ?
  56                       sdram_size : PCI_MEMORY_MAXSIZE;
  57
  58     /* Select the local PCI
  59      */
  60   out32(REG(CPC0, PCICNFR), 0x80000002);
  61   iobarrier_rw();
  62
  63   out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS);
  64   iobarrier_rw();
  65
  66     /* Enable PCI bridge address decoding
  67      */
  68   out32(REG(CPC0, PCIENB), 0x80000000);
  69   iobarrier_rw();
  70
  71     /* Select the CPCI bridge
  72      */
  73   out32(REG(CPC0, PCICNFR), 0x80000003);
  74   iobarrier_rw();
  75
  76   out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS);
  77   iobarrier_rw();
  78
  79     /* Enable PCI bridge address decoding
  80      */
  81   out32(REG(CPC0, PCIENB), 0x80000000);
  82   iobarrier_rw();
  83
  84     /* Disable configuration accesses
  85      */
  86   out32(REG(CPC0, PCICNFR), 0x80000000);
  87   iobarrier_rw();
  88
  89     /* Initialise the local PCI
  90      */
  91   out32(BRIDGE(LOCAL, CRR), 0x7c000000);
  92   iobarrier_rw();
  93   out32(BRIDGE(LOCAL, PCIDG), 0x40000000);
  94   iobarrier_rw();
  95   out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS);
  96   out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS);
  97   out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE);
  98   iobarrier_rw();
  99   out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS);
 100   out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS);
 101   out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE);
 102   iobarrier_rw();
 103   out32(BRIDGE(LOCAL, PR), 0x00ffe000);
 104   iobarrier_rw();
 105   out32(BRIDGE(LOCAL, ACR), 0xfe000000);
 106   iobarrier_rw();
 107   out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24);
 108   out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24);
 109   out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
 110   iobarrier_rw();
 111
 112     /* Initialise the CPCI bridge
 113      */
 114   out32(BRIDGE(CPCI, CRR), 0x7c000000);
 115   iobarrier_rw();
 116   out32(BRIDGE(CPCI, PCIDG), 0xC0000000);
 117   iobarrier_rw();
 118   out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS);
 119   out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS);
 120   out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE);
 121   iobarrier_rw();
 122   out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS);
 123   out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS);
 124   out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE);
 125   iobarrier_rw();
 126   out32(BRIDGE(CPCI, PR), 0x80ffe000);
 127   iobarrier_rw();
 128   out32(BRIDGE(CPCI, ACR), 0xdf000000);
 129   iobarrier_rw();
 130   out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24);
 131   out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24);
 132   out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
 133   iobarrier_rw();
 134
 135     /* Local PCI
 136      */
 137
 138   out32(BRIDGE(LOCAL, CFGADDR), 0x04000080);
 139   iobarrier_rw();
 140   out32(BRIDGE(LOCAL, CFGDATA), 0x56010000);
 141   iobarrier_rw();
 142
 143   out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080);
 144   iobarrier_rw();
 145   out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
 146   iobarrier_rw();
 147
 148     /* Set bus and subbus numbers
 149      */
 150   out32(BRIDGE(LOCAL, CFGADDR), 0x40000080);
 151   iobarrier_rw();
 152   out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
 153   iobarrier_rw();
 154
 155   out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
 156   iobarrier_rw();
 157     /* PCI retry timeouts will be enabled later
 158      */
 159   out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
 160   iobarrier_rw();
 161
 162     /* CPCI
 163      */
 164
 165     /* Set bus and subbus numbers
 166      */
 167   out32(BRIDGE(CPCI, CFGADDR), 0x40000080);
 168   iobarrier_rw();
 169   out32(BRIDGE(CPCI, CFGDATA), 0x01010000);
 170   iobarrier_rw();
 171
 172   out32(BRIDGE(CPCI, CFGADDR), 0x04000180);
 173   iobarrier_rw();
 174   out32(BRIDGE(CPCI, CFGDATA), 0x56010000);
 175   iobarrier_rw();
 176
 177   out32(BRIDGE(CPCI, CFGADDR), 0x0c000180);
 178   iobarrier_rw();
 179   out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
 180   iobarrier_rw();
 181
 182     /* Write to the PSBAR */
 183   out32(BRIDGE(CPCI, CFGADDR), 0x10000180);
 184   iobarrier_rw();
 185   out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS));
 186   iobarrier_rw();
 187
 188     /* Set bus and subbus numbers
 189      */
 190   out32(BRIDGE(CPCI, CFGADDR), 0x40000180);
 191   iobarrier_rw();
 192   out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000);
 193   iobarrier_rw();
 194
 195   out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
 196   iobarrier_rw();
 197   out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
 198     /* PCI retry timeouts will be enabled later
 199      */
 200   out32(BRIDGE(CPCI, CFGDATA), 0x00000000);
 201   iobarrier_rw();
 202
 203     /* Remove reset on the PCI buses
 204      */
 205   out32(BRIDGE(LOCAL, CRR), 0xfc000000);
 206   iobarrier_rw();
 207   out32(BRIDGE(CPCI, CRR), 0xfc000000);
 208   iobarrier_rw();
 209
 210   local_hose.first_busno = 0;
 211   local_hose.last_busno = 0xff;
 212
 213   /* System memory space */
 214   pci_set_region(local_hose.regions + 0,
 215                  PCI_MEMORY_BUS,
 216                  PCI_MEMORY_PHYS,
 217                  PCI_MEMORY_MAXSIZE,
 218                  PCI_REGION_MEM | PCI_REGION_MEMORY);
 219
 220   /* PCI memory space */
 221   pci_set_region(local_hose.regions + 1,
 222                  BRIDGE_LOCAL_MEM_BUS,
 223                  BRIDGE_LOCAL_MEM_PHYS,
 224                  BRIDGE_LOCAL_MEM_SIZE,
 225                  PCI_REGION_MEM);
 226
 227   /* PCI I/O space */
 228   pci_set_region(local_hose.regions + 2,
 229                  BRIDGE_LOCAL_IO_BUS,
 230                  BRIDGE_LOCAL_IO_PHYS,
 231                  BRIDGE_LOCAL_IO_SIZE,
 232                  PCI_REGION_IO);
 233
 234   local_hose.region_count = 3;
 235
 236   pci_setup_indirect(&local_hose,
 237                      BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR,
 238                      BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA);
 239
 240   pci_register_hose(&local_hose);
 241
 242   /* Initialize PCI32 bus registers */
 243   pci_hose_write_config_byte(&local_hose,
 244                           PCI_BDF(local_hose.first_busno,0,0),
 245                           CPC710_BUS_NUMBER,
 246                           local_hose.first_busno);
 247   pci_hose_write_config_byte(&local_hose,
 248                           PCI_BDF(local_hose.first_busno,0,0),
 249                           CPC710_SUB_BUS_NUMBER,
 250                           local_hose.last_busno);
 251
 252   local_hose.last_busno = pci_hose_scan(&local_hose);
 253
 254   /* Write out correct max subordinate bus number for local hose */
 255   pci_hose_write_config_byte(&local_hose,
 256                           PCI_BDF(local_hose.first_busno,0,0),
 257                           CPC710_SUB_BUS_NUMBER,
 258                           local_hose.last_busno);
 259
 260   cpci_hose.first_busno = local_hose.last_busno + 1;
 261   cpci_hose.last_busno = 0xff;
 262
 263   /* System memory space */
 264   pci_set_region(cpci_hose.regions + 0,
 265                  PCI_MEMORY_BUS,
 266                  PCI_MEMORY_PHYS,
 267                  PCI_MEMORY_MAXSIZE,
 268                  PCI_REGION_MEMORY);
 269
 270   /* PCI memory space */
 271   pci_set_region(cpci_hose.regions + 1,
 272                  BRIDGE_CPCI_MEM_BUS,
 273                  BRIDGE_CPCI_MEM_PHYS,
 274                  BRIDGE_CPCI_MEM_SIZE,
 275                  PCI_REGION_MEM);
 276
 277   /* PCI I/O space */
 278   pci_set_region(cpci_hose.regions + 2,
 279                  BRIDGE_CPCI_IO_BUS,
 280                  BRIDGE_CPCI_IO_PHYS,
 281                  BRIDGE_CPCI_IO_SIZE,
 282                  PCI_REGION_IO);
 283
 284   cpci_hose.region_count = 3;
 285
 286   pci_setup_indirect(&cpci_hose,
 287                      BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR,
 288                      BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA);
 289
 290   pci_register_hose(&cpci_hose);
 291
 292   /* Initialize PCI64 bus registers */
 293   pci_hose_write_config_byte(&cpci_hose,
 294                           PCI_BDF(cpci_hose.first_busno,0,0),
 295                           CPC710_BUS_NUMBER,
 296                           cpci_hose.first_busno);
 297   pci_hose_write_config_byte(&cpci_hose,
 298                           PCI_BDF(cpci_hose.first_busno,0,0),
 299                           CPC710_SUB_BUS_NUMBER,
 300                           cpci_hose.last_busno);
 301
 302   cpci_hose.last_busno = pci_hose_scan(&cpci_hose);
 303
 304   /* Write out correct max subordinate bus number for cpci hose */
 305   pci_hose_write_config_byte(&cpci_hose,
 306                           PCI_BDF(cpci_hose.first_busno,0,0),
 307                           CPC710_SUB_BUS_NUMBER,
 308                           cpci_hose.last_busno);
 309 }