Change boot command to boot kernel from 0xc1028380
[u-boot-m93030.git] / board / pcippc2 / pcippc2.c
blobc1917c11b44abc206a0b5794eb4e4b2d5a6656ff
1 /*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
6 * project.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
24 #include <config.h>
25 #include <common.h>
26 #include <command.h>
27 #include <asm/io.h>
28 #include <linux/mtd/doc2000.h>
29 #include <watchdog.h>
30 #include <pci.h>
32 #include "hardware.h"
33 #include "pcippc2.h"
34 #include "sconsole.h"
35 #include "fpga_serial.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_WATCHDOG)
41 static int pcippc2_wdt_init_done = 0;
43 void pcippc2_wdt_init (void);
45 #endif
47 /* Check board identity
49 int checkboard (void)
51 #ifdef CONFIG_PCIPPC2
52 puts ("Board: Gespac PCIPPC-2\n");
53 #else
54 puts ("Board: Gespac PCIPPC-6\n");
55 #endif
56 return 0;
59 /* RAM size is stored in CPC0_RGBAN1
61 u32 pcippc2_sdram_size (void)
63 return in32 (REG (CPC0, RGBAN1));
66 phys_size_t initdram (int board_type)
68 return cpc710_ram_init ();
71 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
73 out32 (REG (CPC0, SPOR), 0);
74 iobarrier_rw ();
75 while (1);
76 /* notreached */
77 return (-1);
80 int board_early_init_f (void)
82 out32 (REG (CPC0, RSTR), 0xC0000000);
83 iobarrier_rw ();
85 out32 (REG (CPC0, RSTR), 0xF0000000);
86 iobarrier_rw ();
88 out32 (REG (CPC0, UCTL), 0x00F80000);
90 out32 (REG (CPC0, SIOC0), 0x30000000);
92 out32 (REG (CPC0, ABCNTL), 0x00000000);
94 out32 (REG (CPC0, SESR), 0x00000000);
95 out32 (REG (CPC0, SEAR), 0x00000000);
97 /* Detect IBM Avignon CPC710 Revision */
98 if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
99 out32 (REG (CPC0, PGCHP), 0xA0000040);
100 else
101 out32 (REG (CPC0, PGCHP), 0x80800040);
104 out32 (REG (CPC0, ATAS), 0x709C2508);
106 iobarrier_rw ();
108 return 0;
111 void after_reloc (ulong dest_addr)
113 /* Jump to the main U-Boot board init code
115 board_init_r ((gd_t *)gd, dest_addr);
118 int misc_init_r (void)
120 pcippc2_fpga_init ();
122 pcippc2_cpci3264_init ();
124 #if defined(CONFIG_WATCHDOG)
125 pcippc2_wdt_init ();
126 #endif
128 fpga_serial_init (sconsole_get_baudrate ());
130 sconsole_putc = fpga_serial_putc;
131 sconsole_puts = fpga_serial_puts;
132 sconsole_getc = fpga_serial_getc;
133 sconsole_tstc = fpga_serial_tstc;
134 sconsole_setbrg = fpga_serial_setbrg;
136 sconsole_flush ();
137 return (0);
140 void pci_init_board (void)
142 cpc710_pci_init ();
144 /* FPGA requires no retry timeouts to be enabled
146 cpc710_pci_enable_timeout ();
149 void doc_init (void)
151 doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
154 void pcippc2_cpci3264_init (void)
156 pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
158 if (bdf == -1)
160 puts("Unable to find FPGA !\n");
161 hang();
164 if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
165 /* 32-bits Compact PCI bus - LSB bit */
167 iobarrier_rw();
168 out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */
169 iobarrier_rw();
173 #if defined(CONFIG_WATCHDOG)
175 void pcippc2_wdt_init (void)
177 out16r (FPGA (WDT, PROG), 0xffff);
178 out8 (FPGA (WDT, CTRL), 0x1);
180 pcippc2_wdt_init_done = 1;
183 void pcippc2_wdt_done (void)
185 out8 (FPGA (WDT, CTRL), 0x0);
187 pcippc2_wdt_init_done = 0;
190 void pcippc2_wdt_reset (void)
192 if (pcippc2_wdt_init_done == 1)
193 out8 (FPGA (WDT, REFRESH), 0x56);
196 void watchdog_reset (void)
198 int re_enable = disable_interrupts ();
200 pcippc2_wdt_reset ();
201 if (re_enable)
202 enable_interrupts ();
205 #if defined(CONFIG_CMD_BSP)
206 int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
208 switch (argc) {
209 case 1:
210 printf ("Watchdog timer status is %s\n",
211 pcippc2_wdt_init_done == 1 ? "on" : "off");
213 return 0;
214 case 2:
215 if (!strcmp(argv[1],"on")) {
216 pcippc2_wdt_init();
217 printf("Watchdog timer now is on\n");
219 return 0;
221 } else if (!strcmp(argv[1],"off")) {
222 pcippc2_wdt_done();
223 printf("Watchdog timer now is off\n");
225 return 0;
227 } else
228 break;
229 default:
230 break;
232 printf ("Usage:\n%s\n", cmdtp->usage);
233 return 1;
236 U_BOOT_CMD(
237 wd, 2, 1, do_wd,
238 "wd - check and set watchdog\n",
239 "on - switch watchDog on\n"
240 "wd off - switch watchdog off\n"
241 "wd - print current status\n"
244 #endif
245 #endif /* CONFIG_WATCHDOG */