board/pm520/pm520.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30
  31 #if defined(CONFIG_MPC5200_DDR)
  32 #include "mt46v16m16-75.h"
  33 #else
  34 #include "mt48lc16m16a2-75.h"
  35 #endif
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifndef CFG_RAMBOOT
  40 static void sdram_start (int hi_addr)
  41 {
  42         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  43
  44         /* unlock mode register */
  45         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  46         __asm__ volatile ("sync");
  47
  48         /* precharge all banks */
  49         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  50         __asm__ volatile ("sync");
  51
  52 #if SDRAM_DDR
  53         /* set mode register: extended mode */
  54         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  55         __asm__ volatile ("sync");
  56
  57         /* set mode register: reset DLL */
  58         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  59         __asm__ volatile ("sync");
  60 #endif
  61
  62         /* precharge all banks */
  63         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  64         __asm__ volatile ("sync");
  65
  66         /* auto refresh */
  67         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  68         __asm__ volatile ("sync");
  69
  70         /* set mode register */
  71         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  72         __asm__ volatile ("sync");
  73
  74         /* normal operation */
  75         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  76         __asm__ volatile ("sync");
  77 }
  78 #endif
  79
  80 /*
  81  * ATTENTION: Although partially referenced initdram does NOT make real use
  82  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  83  *            is something else than 0x00000000.
  84  */
  85
  86 #if defined(CONFIG_MPC5200)
  87 phys_size_t initdram (int board_type)
  88 {
  89         ulong dramsize = 0;
  90         ulong dramsize2 = 0;
  91 #ifndef CFG_RAMBOOT
  92         ulong test1, test2;
  93
  94         /* setup SDRAM chip selects */
  95         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  96         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  97         __asm__ volatile ("sync");
  98
  99         /* setup config registers */
 100         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 101         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 102         __asm__ volatile ("sync");
 103
 104 #if SDRAM_DDR
 105         /* set tap delay */
 106         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 107         __asm__ volatile ("sync");
 108 #endif
 109
 110         /* find RAM size using SDRAM CS0 only */
 111         sdram_start(0);
 112         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 113         sdram_start(1);
 114         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 115         if (test1 > test2) {
 116                 sdram_start(0);
 117                 dramsize = test1;
 118         } else {
 119                 dramsize = test2;
 120         }
 121
 122         /* memory smaller than 1MB is impossible */
 123         if (dramsize < (1 << 20)) {
 124                 dramsize = 0;
 125         }
 126
 127         /* set SDRAM CS0 size according to the amount of RAM found */
 128         if (dramsize > 0) {
 129                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 130         } else {
 131                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 132         }
 133
 134         /* let SDRAM CS1 start right after CS0 */
 135         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 136
 137         /* find RAM size using SDRAM CS1 only */
 138         if (!dramsize)
 139                 sdram_start(0);
 140         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 141         if (!dramsize) {
 142                 sdram_start(1);
 143                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 144         }
 145         if (test1 > test2) {
 146                 sdram_start(0);
 147                 dramsize2 = test1;
 148         } else {
 149                 dramsize2 = test2;
 150         }
 151
 152         /* memory smaller than 1MB is impossible */
 153         if (dramsize2 < (1 << 20)) {
 154                 dramsize2 = 0;
 155         }
 156
 157         /* set SDRAM CS1 size according to the amount of RAM found */
 158         if (dramsize2 > 0) {
 159                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 160                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 161         } else {
 162                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 163         }
 164
 165 #else /* CFG_RAMBOOT */
 166
 167         /* retrieve size of memory connected to SDRAM CS0 */
 168         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 169         if (dramsize >= 0x13) {
 170                 dramsize = (1 << (dramsize - 0x13)) << 20;
 171         } else {
 172                 dramsize = 0;
 173         }
 174
 175         /* retrieve size of memory connected to SDRAM CS1 */
 176         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 177         if (dramsize2 >= 0x13) {
 178                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 179         } else {
 180                 dramsize2 = 0;
 181         }
 182
 183 #endif /* CFG_RAMBOOT */
 184
 185         return dramsize + dramsize2;
 186 }
 187
 188 #elif defined(CONFIG_MGT5100)
 189
 190 phys_size_t initdram (int board_type)
 191 {
 192         ulong dramsize = 0;
 193 #ifndef CFG_RAMBOOT
 194         ulong test1, test2;
 195
 196         /* setup and enable SDRAM chip selects */
 197         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 198         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 199         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 200         __asm__ volatile ("sync");
 201
 202         /* setup config registers */
 203         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 204         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 205
 206         /* address select register */
 207         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 208         __asm__ volatile ("sync");
 209
 210         /* find RAM size */
 211         sdram_start(0);
 212         test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 213         sdram_start(1);
 214         test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 215         if (test1 > test2) {
 216                 sdram_start(0);
 217                 dramsize = test1;
 218         } else {
 219                 dramsize = test2;
 220         }
 221
 222         /* set SDRAM end address according to size */
 223         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 224
 225 #else /* CFG_RAMBOOT */
 226
 227         /* Retrieve amount of SDRAM available */
 228         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 229
 230 #endif /* CFG_RAMBOOT */
 231
 232         return dramsize;
 233 }
 234
 235 #else
 236 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 237 #endif
 238
 239 int checkboard (void)
 240 {
 241 #if defined(CONFIG_MPC5200)
 242         puts ("Board: MicroSys PM520 \n");
 243 #elif defined(CONFIG_MGT5100)
 244         puts ("Board: MicroSys PM510 \n");
 245 #endif
 246         return 0;
 247 }
 248
 249 void flash_preinit(void)
 250 {
 251         /*
 252          * Now, when we are in RAM, enable flash write
 253          * access for detection process.
 254          * Note that CS_BOOT cannot be cleared when
 255          * executing in flash.
 256          */
 257 #if defined(CONFIG_MGT5100)
 258         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 259         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 260 #endif
 261         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 262 }
 263
 264 void flash_afterinit(ulong start, ulong size)
 265 {
 266 #if defined(CONFIG_BOOT_ROM)
 267         /* adjust mapping */
 268         *(vu_long *)MPC5XXX_CS1_START =
 269                         START_REG(start);
 270         *(vu_long *)MPC5XXX_CS1_STOP =
 271                         STOP_REG(start, size);
 272 #else
 273         /* adjust mapping */
 274         *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 275                         START_REG(start);
 276         *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 277                         STOP_REG(start, size);
 278 #endif
 279 }
 280
 281
 282 extern flash_info_t flash_info[];       /* info for FLASH chips */
 283
 284 int misc_init_r (void)
 285 {
 286         /* adjust flash start */
 287         gd->bd->bi_flashstart = flash_info[0].start[0];
 288         return (0);
 289 }
 290
 291 #ifdef  CONFIG_PCI
 292 static struct pci_controller hose;
 293
 294 extern void pci_mpc5xxx_init(struct pci_controller *);
 295
 296 void pci_init_board(void)
 297 {
 298         pci_mpc5xxx_init(&hose);
 299 }
 300 #endif
 301
 302 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 303
 304 void init_ide_reset (void)
 305 {
 306         debug ("init_ide_reset\n");
 307
 308 }
 309
 310 void ide_set_reset (int idereset)
 311 {
 312         debug ("ide_reset(%d)\n", idereset);
 313
 314 }
 315 #endif
 316
 317 #if defined(CONFIG_CMD_DOC)
 318 extern void doc_probe (ulong physadr);
 319 void doc_init (void)
 320 {
 321         doc_probe (CFG_DOC_BASE);
 322 }
 323 #endif