board/pm854/pm854.c

   1  /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003, Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <common.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31 #include <asm/immap_85xx.h>
  32 #include <spd_sdram.h>
  33
  34 #if defined(CONFIG_DDR_ECC)
  35 extern void ddr_enable_ecc(unsigned int dram_size);
  36 #endif
  37
  38 void local_bus_init(void);
  39 void sdram_init(void);
  40 long int fixed_sdram(void);
  41
  42
  43 int board_early_init_f (void)
  44 {
  45 #if defined(CONFIG_PCI)
  46     volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
  47
  48     pci->peer &= 0xffffffdf; /* disable master abort */
  49 #endif
  50
  51     return 0;
  52 }
  53
  54 int checkboard (void)
  55 {
  56         puts("Board: MicroSys PM854\n");
  57
  58 #ifdef CONFIG_PCI
  59         printf("    PCI1: 32 bit, %d MHz (compiled)\n",
  60                CONFIG_SYS_CLK_FREQ / 1000000);
  61 #else
  62         printf("    PCI1: disabled\n");
  63 #endif
  64
  65         /*
  66          * Initialize local bus.
  67          */
  68         local_bus_init();
  69
  70         return 0;
  71 }
  72
  73
  74 phys_size_t
  75 initdram(int board_type)
  76 {
  77         long dram_size = 0;
  78
  79         puts("Initializing\n");
  80
  81 #if defined(CONFIG_DDR_DLL)
  82         {
  83             volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  84             int i,x;
  85
  86             x = 10;
  87
  88             /*
  89              * Work around to stabilize DDR DLL
  90              */
  91             gur->ddrdllcr = 0x81000000;
  92             asm("sync;isync;msync");
  93             udelay (200);
  94             while (gur->ddrdllcr != 0x81000100)
  95             {
  96                 gur->devdisr = gur->devdisr | 0x00010000;
  97                 asm("sync;isync;msync");
  98                 for (i=0; i<x; i++)
  99                     ;
 100                 gur->devdisr = gur->devdisr & 0xfff7ffff;
 101                 asm("sync;isync;msync");
 102                 x++;
 103             }
 104         }
 105 #endif
 106
 107 #if defined(CONFIG_SPD_EEPROM)
 108         dram_size = spd_sdram ();
 109 #else
 110         dram_size = fixed_sdram ();
 111 #endif
 112
 113 #if defined(CONFIG_DDR_ECC)
 114         /*
 115          * Initialize and enable DDR ECC.
 116          */
 117         ddr_enable_ecc(dram_size);
 118 #endif
 119         puts("    DDR: ");
 120         return dram_size;
 121 }
 122
 123
 124 /*
 125  * Initialize Local Bus
 126  */
 127
 128 void
 129 local_bus_init(void)
 130 {
 131         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 132         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 133
 134         uint clkdiv;
 135         uint lbc_hz;
 136         sys_info_t sysinfo;
 137
 138         /*
 139          * Errata LBC11.
 140          * Fix Local Bus clock glitch when DLL is enabled.
 141          *
 142          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 143          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 144          * Between 66 and 133, the DLL is enabled with an override workaround.
 145          */
 146
 147         get_sys_info(&sysinfo);
 148         clkdiv = lbc->lcrr & 0x0f;
 149         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 150
 151         if (lbc_hz < 66) {
 152                 lbc->lcrr = CFG_LBC_LCRR | 0x80000000;  /* DLL Bypass */
 153
 154         } else if (lbc_hz >= 133) {
 155                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 156
 157         } else {
 158                 /*
 159                  * On REV1 boards, need to change CLKDIV before enable DLL.
 160                  * Default CLKDIV is 8, change it to 4 temporarily.
 161                  */
 162                 uint pvr = get_pvr();
 163                 uint temp_lbcdll = 0;
 164
 165                 if (pvr == PVR_85xx_REV1) {
 166                         /* FIXME: Justify the high bit here. */
 167                         lbc->lcrr = 0x10000004;
 168                 }
 169
 170                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 171                 udelay(200);
 172
 173                 /*
 174                  * Sample LBC DLL ctrl reg, upshift it to set the
 175                  * override bits.
 176                  */
 177                 temp_lbcdll = gur->lbcdllcr;
 178                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 179                 asm("sync;isync;msync");
 180         }
 181 }
 182
 183
 184 #if defined(CFG_DRAM_TEST)
 185 int testdram (void)
 186 {
 187         uint *pstart = (uint *) CFG_MEMTEST_START;
 188         uint *pend = (uint *) CFG_MEMTEST_END;
 189         uint *p;
 190
 191         printf("SDRAM test phase 1:\n");
 192         for (p = pstart; p < pend; p++)
 193                 *p = 0xaaaaaaaa;
 194
 195         for (p = pstart; p < pend; p++) {
 196                 if (*p != 0xaaaaaaaa) {
 197                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 198                         return 1;
 199                 }
 200         }
 201
 202         printf("SDRAM test phase 2:\n");
 203         for (p = pstart; p < pend; p++)
 204                 *p = 0x55555555;
 205
 206         for (p = pstart; p < pend; p++) {
 207                 if (*p != 0x55555555) {
 208                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 209                         return 1;
 210                 }
 211         }
 212
 213         printf("SDRAM test passed.\n");
 214         return 0;
 215 }
 216 #endif
 217
 218
 219 #if !defined(CONFIG_SPD_EEPROM)
 220 /*************************************************************************
 221  *  fixed sdram init -- doesn't use serial presence detect.
 222  ************************************************************************/
 223 long int fixed_sdram (void)
 224 {
 225   #ifndef CFG_RAMBOOT
 226         volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 227
 228         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 229         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 230         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 231         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 232         ddr->sdram_mode = CFG_DDR_MODE;
 233         ddr->sdram_interval = CFG_DDR_INTERVAL;
 234     #if defined (CONFIG_DDR_ECC)
 235         ddr->err_disable = 0x0000000D;
 236         ddr->err_sbe = 0x00ff0000;
 237     #endif
 238         asm("sync;isync;msync");
 239         udelay(500);
 240     #if defined (CONFIG_DDR_ECC)
 241         /* Enable ECC checking */
 242         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
 243     #else
 244         ddr->sdram_cfg = CFG_DDR_CONTROL;
 245     #endif
 246         asm("sync; isync; msync");
 247         udelay(500);
 248   #endif
 249         return CFG_SDRAM_SIZE * 1024 * 1024;
 250 }
 251 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 252
 253
 254 #if defined(CONFIG_PCI)
 255 /*
 256  * Initialize PCI Devices, report devices found.
 257  */
 258
 259 #ifndef CONFIG_PCI_PNP
 260 static struct pci_config_table pci_pm854_config_table[] = {
 261     { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 262       PCI_IDSEL_NUMBER, PCI_ANY_ID,
 263       pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 264                                    PCI_ENET0_MEMADDR,
 265                                    PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 266       } },
 267     { }
 268 };
 269 #endif
 270
 271
 272 static struct pci_controller hose = {
 273 #ifndef CONFIG_PCI_PNP
 274         config_table: pci_pm854_config_table,
 275 #endif
 276 };
 277
 278 #endif  /* CONFIG_PCI */
 279
 280
 281 void
 282 pci_init_board(void)
 283 {
 284 #ifdef CONFIG_PCI
 285         pci_mpc85xx_init(&hose);
 286 #endif /* CONFIG_PCI */
 287 }