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Change boot command to boot kernel from 0xc1028380
[u-boot-m93030.git] / cpu / mpc8260 / i2c.c
blobc3af7b6d839ee6f9f21f137beff5c9775d222e95
1 /*
2 * (C) Copyright 2000
3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4 *
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #include <common.h>
28
29 #if defined(CONFIG_HARD_I2C)
30
31 #include <asm/cpm_8260.h>
32 #include <i2c.h>
33
34 /* define to enable debug messages */
35 #undef DEBUG_I2C
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 /* uSec to wait between polls of the i2c */
40 #define DELAY_US 100
41 /* uSec to wait for the CPM to start processing the buffer */
42 #define START_DELAY_US 1000
43
44 /*
45 * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
46 * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
47 */
48 #define TOUT_LOOP 5
49
50 /*-----------------------------------------------------------------------
51 * Set default values
52 */
53 #ifndef CFG_I2C_SPEED
54 #define CFG_I2C_SPEED 50000
55 #endif
56
57 #ifndef CFG_I2C_SLAVE
58 #define CFG_I2C_SLAVE 0xFE
59 #endif
60 /*-----------------------------------------------------------------------
61 */
62
63 typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */
64
65 /* This structure keeps track of the bd and buffer space usage. */
66 typedef struct i2c_state {
67 int rx_idx; /* index to next free Rx BD */
68 int tx_idx; /* index to next free Tx BD */
69 void *rxbd; /* pointer to next free Rx BD */
70 void *txbd; /* pointer to next free Tx BD */
71 int tx_space; /* number of Tx bytes left */
72 unsigned char *tx_buf; /* pointer to free Tx area */
73 i2c_ecb_t err_cb; /* error callback function */
74 void *cb_data; /* private data to be passed */
75 } i2c_state_t;
76
77 /* flags for i2c_send() and i2c_receive() */
78 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
79 #define I2CF_START_COND 0x02 /* tx: generate start condition */
80 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
81
82 /* return codes */
83 #define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
84 #define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
85 #define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
86 #define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */
87 #define I2CERR_IO_ERROR 5 /* had an error during comms */
88
89 /* error callback flags */
90 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
91 #define I2CECB_RX_OV 0x02 /* receive overrun error */
92 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
93 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
94 #define I2CECB_TX_CL 0x01 /* transmit collision error */
95 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
96 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
97 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
98 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
99
100 #define ERROR_I2C_NONE 0
101 #define ERROR_I2C_LENGTH 1
102
103 #define I2C_WRITE_BIT 0x00
104 #define I2C_READ_BIT 0x01
105
106 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
107
108
109 #define NUM_RX_BDS 4
110 #define NUM_TX_BDS 4
111 #define MAX_TX_SPACE 256
112
113 typedef struct I2C_BD
114 {
115 unsigned short status;
116 unsigned short length;
117 unsigned char *addr;
118 } I2C_BD;
119 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
120
121 #define BD_I2C_TX_CL 0x0001 /* collision error */
122 #define BD_I2C_TX_UN 0x0002 /* underflow error */
123 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
124 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
125
126 #define BD_I2C_RX_ERR BD_SC_OV
127
128 #ifdef DEBUG_I2C
129 #define PRINTD(x) printf x
130 #else
131 #define PRINTD(x)
132 #endif
133
134 /*
135 * Returns the best value of I2BRG to meet desired clock speed of I2C with
136 * input parameters (clock speed, filter, and predivider value).
137 * It returns computer speed value and the difference between it and desired
138 * speed.
139 */
140 static inline int
141 i2c_roundrate(int hz, int speed, int filter, int modval,
142 int *brgval, int *totspeed)
143 {
144 int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
145
146 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
147 hz, speed, filter, modval));
148
149 div = moddiv * speed;
150 brgdiv = (hz + div - 1) / div;
151
152 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
153
154 *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
155
156 if ((*brgval < 0) || (*brgval > 255)) {
157 PRINTD(("\t\trejected brgval=%d\n", *brgval));
158 return -1;
159 }
160
161 brgdiv = 2 * (*brgval + 3 + (2 * filter));
162 div = moddiv * brgdiv ;
163 *totspeed = hz / div;
164
165 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
166
167 return 0;
168 }
169
170 /*
171 * Sets the I2C clock predivider and divider to meet required clock speed.
172 */
173 static int i2c_setrate(int hz, int speed)
174 {
175 immap_t *immap = (immap_t *)CFG_IMMR ;
176 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
177 int brgval,
178 modval, /* 0-3 */
179 bestspeed_diff = speed,
180 bestspeed_brgval=0,
181 bestspeed_modval=0,
182 bestspeed_filter=0,
183 totspeed,
184 filter = 0; /* Use this fixed value */
185
186 for (modval = 0; modval < 4; modval++)
187 {
188 if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
189 {
190 int diff = speed - totspeed ;
191
192 if ((diff >= 0) && (diff < bestspeed_diff))
193 {
194 bestspeed_diff = diff ;
195 bestspeed_modval = modval;
196 bestspeed_brgval = brgval;
197 bestspeed_filter = filter;
198 }
199 }
200 }
201
202 PRINTD(("[I2C] Best is:\n"));
203 PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
204 hz, speed,
205 bestspeed_filter, bestspeed_modval, bestspeed_brgval,
206 bestspeed_diff));
207
208 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
209 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
210
211 PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
212
213 return 1 ;
214 }
215
216 void i2c_init(int speed, int slaveadd)
217 {
218 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
219 volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
220 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
221 volatile iic_t *iip;
222 ulong rbase, tbase;
223 volatile I2C_BD *rxbd, *txbd;
224 uint dpaddr;
225
226 #ifdef CFG_I2C_INIT_BOARD
227 /* call board specific i2c bus reset routine before accessing the */
228 /* environment, which might be in a chip on that bus. For details */
229 /* about this problem see doc/I2C_Edge_Conditions. */
230 i2c_init_board();
231 #endif
232
233 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
234 if (dpaddr == 0) {
235 /* need to allocate dual port ram */
236 dpaddr = m8260_cpm_dpalloc(64 +
237 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
238 MAX_TX_SPACE, 64);
239 *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
240 }
241
242 /*
243 * initialise data in dual port ram:
244 *
245 * dpaddr -> parameter ram (64 bytes)
246 * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
247 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
248 * tx buffer (MAX_TX_SPACE bytes)
249 */
250
251 iip = (iic_t *)&immap->im_dprambase[dpaddr];
252 memset((void*)iip, 0, sizeof(iic_t));
253
254 rbase = dpaddr + 64;
255 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
256
257 /* Disable interrupts */
258 i2c->i2c_i2mod = 0x00;
259 i2c->i2c_i2cmr = 0x00;
260 i2c->i2c_i2cer = 0xff;
261 i2c->i2c_i2add = slaveadd;
262
263 /*
264 * Set the I2C BRG Clock division factor from desired i2c rate
265 * and current CPU rate (we assume sccr dfbgr field is 0;
266 * divide BRGCLK by 1)
267 */
268 PRINTD(("[I2C] Setting rate...\n"));
269 i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ;
270
271 /* Set I2C controller in master mode */
272 i2c->i2c_i2com = 0x01;
273
274 /* Initialize Tx/Rx parameters */
275 iip->iic_rbase = rbase;
276 iip->iic_tbase = tbase;
277 rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
278 txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
279
280 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
281 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
282 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
283 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
284
285 /* Set big endian byte order */
286 iip->iic_tfcr = 0x10;
287 iip->iic_rfcr = 0x10;
288
289 /* Set maximum receive size. */
290 iip->iic_mrblr = I2C_RXTX_LEN;
291
292 cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
293 CPM_CR_I2C_SBLOCK,
294 0x00,
295 CPM_CR_INIT_TRX) | CPM_CR_FLG;
296 do {
297 __asm__ __volatile__ ("eieio");
298 } while (cp->cp_cpcr & CPM_CR_FLG);
299
300 /* Clear events and interrupts */
301 i2c->i2c_i2cer = 0xff;
302 i2c->i2c_i2cmr = 0x00;
303 }
304
305 static
306 void i2c_newio(i2c_state_t *state)
307 {
308 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
309 volatile iic_t *iip;
310 uint dpaddr;
311
312 PRINTD(("[I2C] i2c_newio\n"));
313
314 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
315 iip = (iic_t *)&immap->im_dprambase[dpaddr];
316 state->rx_idx = 0;
317 state->tx_idx = 0;
318 state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
319 state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
320 state->tx_space = MAX_TX_SPACE;
321 state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
322 state->err_cb = NULL;
323 state->cb_data = NULL;
324
325 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
326 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
327 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
328
329 /* clear the buffer memory */
330 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
331 }
332
333 static
334 int i2c_send(i2c_state_t *state,
335 unsigned char address,
336 unsigned char secondary_address,
337 unsigned int flags,
338 unsigned short size,
339 unsigned char *dataout)
340 {
341 volatile I2C_BD *txbd;
342 int i,j;
343
344 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
345 address, secondary_address, flags, size));
346
347 /* trying to send message larger than BD */
348 if (size > I2C_RXTX_LEN)
349 return I2CERR_MSG_TOO_LONG;
350
351 /* no more free bds */
352 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
353 return I2CERR_NO_BUFFERS;
354
355 txbd = (I2C_BD *)state->txbd;
356 txbd->addr = state->tx_buf;
357
358 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
359
360 if (flags & I2CF_START_COND)
361 {
362 PRINTD(("[I2C] Formatting addresses...\n"));
363 if (flags & I2CF_ENABLE_SECONDARY)
364 {
365 txbd->length = size + 2; /* Length of message plus dest addresses */
366 txbd->addr[0] = address << 1;
367 txbd->addr[1] = secondary_address;
368 i = 2;
369 }
370 else
371 {
372 txbd->length = size + 1; /* Length of message plus dest address */
373 txbd->addr[0] = address << 1; /* Write destination address to BD */
374 i = 1;
375 }
376 }
377 else
378 {
379 txbd->length = size; /* Length of message */
380 i = 0;
381 }
382
383 /* set up txbd */
384 txbd->status = BD_SC_READY;
385 if (flags & I2CF_START_COND)
386 txbd->status |= BD_I2C_TX_START;
387 if (flags & I2CF_STOP_COND)
388 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
389
390 /* Copy data to send into buffer */
391 PRINTD(("[I2C] copy data...\n"));
392 for(j = 0; j < size; i++, j++)
393 txbd->addr[i] = dataout[j];
394
395 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
396 txbd->length,
397 txbd->status,
398 txbd->addr[0],
399 txbd->addr[1]));
400
401 /* advance state */
402 state->tx_buf += txbd->length;
403 state->tx_space -= txbd->length;
404 state->tx_idx++;
405 state->txbd = (void*)(txbd + 1);
406
407 return 0;
408 }
409
410 static
411 int i2c_receive(i2c_state_t *state,
412 unsigned char address,
413 unsigned char secondary_address,
414 unsigned int flags,
415 unsigned short size_to_expect,
416 unsigned char *datain)
417 {
418 volatile I2C_BD *rxbd, *txbd;
419
420 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
421
422 /* Expected to receive too much */
423 if (size_to_expect > I2C_RXTX_LEN)
424 return I2CERR_MSG_TOO_LONG;
425
426 /* no more free bds */
427 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
428 || state->tx_space < 2)
429 return I2CERR_NO_BUFFERS;
430
431 rxbd = (I2C_BD *)state->rxbd;
432 txbd = (I2C_BD *)state->txbd;
433
434 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
435 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
436
437 txbd->addr = state->tx_buf;
438
439 /* set up TXBD for destination address */
440 if (flags & I2CF_ENABLE_SECONDARY)
441 {
442 txbd->length = 2;
443 txbd->addr[0] = address << 1; /* Write data */
444 txbd->addr[1] = secondary_address; /* Internal address */
445 txbd->status = BD_SC_READY;
446 }
447 else
448 {
449 txbd->length = 1 + size_to_expect;
450 txbd->addr[0] = (address << 1) | 0x01;
451 txbd->status = BD_SC_READY;
452 memset(&txbd->addr[1], 0, txbd->length);
453 }
454
455 /* set up rxbd for reception */
456 rxbd->status = BD_SC_EMPTY;
457 rxbd->length = size_to_expect;
458 rxbd->addr = datain;
459
460 txbd->status |= BD_I2C_TX_START;
461 if (flags & I2CF_STOP_COND)
462 {
463 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
464 rxbd->status |= BD_SC_WRAP;
465 }
466
467 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
468 txbd->length,
469 txbd->status,
470 txbd->addr[0],
471 txbd->addr[1]));
472 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
473 rxbd->length,
474 rxbd->status,
475 rxbd->addr[0],
476 rxbd->addr[1]));
477
478 /* advance state */
479 state->tx_buf += txbd->length;
480 state->tx_space -= txbd->length;
481 state->tx_idx++;
482 state->txbd = (void*)(txbd + 1);
483 state->rx_idx++;
484 state->rxbd = (void*)(rxbd + 1);
485
486 return 0;
487 }
488
489
490 static
491 int i2c_doio(i2c_state_t *state)
492 {
493 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
494 volatile iic_t *iip;
495 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
496 volatile I2C_BD *txbd, *rxbd;
497 int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
498 uint dpaddr;
499
500 PRINTD(("[I2C] i2c_doio\n"));
501
502 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
503 PRINTD(("[I2C] No I/O is queued\n"));
504 return I2CERR_QUEUE_EMPTY;
505 }
506
507 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
508 iip = (iic_t *)&immap->im_dprambase[dpaddr];
509 iip->iic_rbptr = iip->iic_rbase;
510 iip->iic_tbptr = iip->iic_tbase;
511
512 /* Enable I2C */
513 PRINTD(("[I2C] Enabling I2C...\n"));
514 i2c->i2c_i2mod |= 0x01;
515
516 /* Begin transmission */
517 i2c->i2c_i2com |= 0x80;
518
519 /* Loop until transmit & receive completed */
520
521 if ((n = state->tx_idx) > 0) {
522
523 txbd = ((I2C_BD*)state->txbd) - n;
524 for (i = 0; i < n; i++) {
525 txtimeo += TOUT_LOOP * txbd->length;
526 txbd++;
527 }
528
529 txbd--; /* wait until last in list is done */
530
531 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
532
533 udelay(START_DELAY_US); /* give it time to start */
534 while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
535 udelay(DELAY_US);
536 if (ctrlc())
537 return (-1);
538 __asm__ __volatile__ ("eieio");
539 }
540 }
541
542 if (txcnt < txtimeo && (n = state->rx_idx) > 0) {
543
544 rxbd = ((I2C_BD*)state->rxbd) - n;
545 for (i = 0; i < n; i++) {
546 rxtimeo += TOUT_LOOP * rxbd->length;
547 rxbd++;
548 }
549
550 rxbd--; /* wait until last in list is done */
551
552 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
553
554 udelay(START_DELAY_US); /* give it time to start */
555 while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
556 udelay(DELAY_US);
557 if (ctrlc())
558 return (-1);
559 __asm__ __volatile__ ("eieio");
560 }
561 }
562
563 /* Turn off I2C */
564 i2c->i2c_i2mod &= ~0x01;
565
566 if ((n = state->tx_idx) > 0) {
567 for (i = 0; i < n; i++) {
568 txbd = ((I2C_BD*)state->txbd) - (n - i);
569 if ((b = txbd->status & BD_I2C_TX_ERR) != 0) {
570 if (state->err_cb != NULL)
571 (*state->err_cb)(I2CECB_TX_ERR|b, i,
572 state->cb_data);
573 if (rc == 0)
574 rc = I2CERR_IO_ERROR;
575 }
576 }
577 }
578
579 if ((n = state->rx_idx) > 0) {
580 for (i = 0; i < n; i++) {
581 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
582 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) {
583 if (state->err_cb != NULL)
584 (*state->err_cb)(I2CECB_RX_ERR|b, i,
585 state->cb_data);
586 if (rc == 0)
587 rc = I2CERR_IO_ERROR;
588 }
589 }
590 }
591
592 if ((txtimeo > 0 && txcnt >= txtimeo) || \
593 (rxtimeo > 0 && rxcnt >= rxtimeo)) {
594 if (state->err_cb != NULL)
595 (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data);
596 if (rc == 0)
597 rc = I2CERR_TIMEOUT;
598 }
599
600 return (rc);
601 }
602
603 static void
604 i2c_probe_callback(int flags, int xnum, void *data)
605 {
606 /*
607 * the only acceptable errors are a transmit NAK or a receive
608 * overrun - tx NAK means the device does not exist, rx OV
609 * means the device must have responded to the slave address
610 * even though the transfer failed
611 */
612 if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK))
613 *(int *)data |= 1;
614 if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV))
615 *(int *)data |= 2;
616 }
617
618 int
619 i2c_probe(uchar chip)
620 {
621 i2c_state_t state;
622 int rc, err_flag;
623 uchar buf[1];
624
625 i2c_newio(&state);
626
627 state.err_cb = i2c_probe_callback;
628 state.cb_data = (void *) &err_flag;
629 err_flag = 0;
630
631 rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
632
633 if (rc != 0)
634 return (rc); /* probe failed */
635
636 rc = i2c_doio(&state);
637
638 if (rc == 0)
639 return (0); /* device exists - read succeeded */
640
641 if (rc == I2CERR_TIMEOUT)
642 return (-1); /* device does not exist - timeout */
643
644 if (rc != I2CERR_IO_ERROR || err_flag == 0)
645 return (rc); /* probe failed */
646
647 if (err_flag & 1)
648 return (-1); /* device does not exist - had transmit NAK */
649
650 return (0); /* device exists - had receive overrun */
651 }
652
653
654 int
655 i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
656 {
657 i2c_state_t state;
658 uchar xaddr[4];
659 int rc;
660
661 xaddr[0] = (addr >> 24) & 0xFF;
662 xaddr[1] = (addr >> 16) & 0xFF;
663 xaddr[2] = (addr >> 8) & 0xFF;
664 xaddr[3] = addr & 0xFF;
665
666 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
667 /*
668 * EEPROM chips that implement "address overflow" are ones
669 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
670 * and the extra bits end up in the "chip address" bit slots.
671 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
672 * chips.
673 *
674 * Note that we consider the length of the address field to still
675 * be one byte because the extra address bits are hidden in the
676 * chip address.
677 */
678 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
679 #endif
680
681 i2c_newio(&state);
682
683 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
684 if (rc != 0) {
685 printf("i2c_read: i2c_send failed (%d)\n", rc);
686 return 1;
687 }
688
689 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
690 if (rc != 0) {
691 printf("i2c_read: i2c_receive failed (%d)\n", rc);
692 return 1;
693 }
694
695 rc = i2c_doio(&state);
696 if (rc != 0) {
697 printf("i2c_read: i2c_doio failed (%d)\n", rc);
698 return 1;
699 }
700 return 0;
701 }
702
703 int
704 i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
705 {
706 i2c_state_t state;
707 uchar xaddr[4];
708 int rc;
709
710 xaddr[0] = (addr >> 24) & 0xFF;
711 xaddr[1] = (addr >> 16) & 0xFF;
712 xaddr[2] = (addr >> 8) & 0xFF;
713 xaddr[3] = addr & 0xFF;
714
715 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
716 /*
717 * EEPROM chips that implement "address overflow" are ones
718 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
719 * and the extra bits end up in the "chip address" bit slots.
720 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
721 * chips.
722 *
723 * Note that we consider the length of the address field to still
724 * be one byte because the extra address bits are hidden in the
725 * chip address.
726 */
727 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
728 #endif
729
730 i2c_newio(&state);
731
732 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
733 if (rc != 0) {
734 printf("i2c_write: first i2c_send failed (%d)\n", rc);
735 return 1;
736 }
737
738 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
739 if (rc != 0) {
740 printf("i2c_write: second i2c_send failed (%d)\n", rc);
741 return 1;
742 }
743
744 rc = i2c_doio(&state);
745 if (rc != 0) {
746 printf("i2c_write: i2c_doio failed (%d)\n", rc);
747 return 1;
748 }
749 return 0;
750 }
751
752 uchar
753 i2c_reg_read(uchar chip, uchar reg)
754 {
755 uchar buf;
756
757 i2c_read(chip, reg, 1, &buf, 1);
758
759 return (buf);
760 }
761
762 void
763 i2c_reg_write(uchar chip, uchar reg, uchar val)
764 {
765 i2c_write(chip, reg, 1, &val, 1);
766 }
767
768 #endif /* CONFIG_HARD_I2C */
u-boot for m93030