cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <asm/processor.h>
  32 #include <ioports.h>
  33 #include <asm/io.h>
  34 #include <asm/mmu.h>
  35 #include <asm/fsl_law.h>
  36 #include "mp.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #ifdef CONFIG_QE
  41 extern qe_iop_conf_t qe_iop_conf_tab[];
  42 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  43                                 int open_drain, int assign);
  44 extern void qe_init(uint qe_base);
  45 extern void qe_reset(void);
  46
  47 static void config_qe_ioports(void)
  48 {
  49         u8      port, pin;
  50         int     dir, open_drain, assign;
  51         int     i;
  52
  53         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  54                 port            = qe_iop_conf_tab[i].port;
  55                 pin             = qe_iop_conf_tab[i].pin;
  56                 dir             = qe_iop_conf_tab[i].dir;
  57                 open_drain      = qe_iop_conf_tab[i].open_drain;
  58                 assign          = qe_iop_conf_tab[i].assign;
  59                 qe_config_iopin(port, pin, dir, open_drain, assign);
  60         }
  61 }
  62 #endif
  63
  64 #ifdef CONFIG_CPM2
  65 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  66 {
  67         int portnum;
  68
  69         for (portnum = 0; portnum < 4; portnum++) {
  70                 uint pmsk = 0,
  71                      ppar = 0,
  72                      psor = 0,
  73                      pdir = 0,
  74                      podr = 0,
  75                      pdat = 0;
  76                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  77                 iop_conf_t *eiopc = iopc + 32;
  78                 uint msk = 1;
  79
  80                 /*
  81                  * NOTE:
  82                  * index 0 refers to pin 31,
  83                  * index 31 refers to pin 0
  84                  */
  85                 while (iopc < eiopc) {
  86                         if (iopc->conf) {
  87                                 pmsk |= msk;
  88                                 if (iopc->ppar)
  89                                         ppar |= msk;
  90                                 if (iopc->psor)
  91                                         psor |= msk;
  92                                 if (iopc->pdir)
  93                                         pdir |= msk;
  94                                 if (iopc->podr)
  95                                         podr |= msk;
  96                                 if (iopc->pdat)
  97                                         pdat |= msk;
  98                         }
  99
 100                         msk <<= 1;
 101                         iopc++;
 102                 }
 103
 104                 if (pmsk != 0) {
 105                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 106                         uint tpmsk = ~pmsk;
 107
 108                         /*
 109                          * the (somewhat confused) paragraph at the
 110                          * bottom of page 35-5 warns that there might
 111                          * be "unknown behaviour" when programming
 112                          * PSORx and PDIRx, if PPARx = 1, so I
 113                          * decided this meant I had to disable the
 114                          * dedicated function first, and enable it
 115                          * last.
 116                          */
 117                         iop->ppar &= tpmsk;
 118                         iop->psor = (iop->psor & tpmsk) | psor;
 119                         iop->podr = (iop->podr & tpmsk) | podr;
 120                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 121                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 122                         iop->ppar |= ppar;
 123                 }
 124         }
 125 }
 126 #endif
 127
 128 /* We run cpu_init_early_f in AS = 1 */
 129 void cpu_init_early_f(void)
 130 {
 131         set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
 132                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 133                 1, 0, BOOKE_PAGESZ_4K, 0);
 134
 135         /* set up CCSR if we want it moved */
 136 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
 137         {
 138                 u32 temp;
 139
 140                 set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
 141                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 142                         1, 1, BOOKE_PAGESZ_4K, 0);
 143
 144                 temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
 145                 out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
 146
 147                 temp = in_be32((volatile u32 *)CFG_CCSRBAR);
 148         }
 149 #endif
 150
 151         /* Pointer is writable since we allocated a register for it */
 152         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 153
 154         /* Clear initial global data */
 155         memset ((void *) gd, 0, sizeof (gd_t));
 156
 157         init_laws();
 158         invalidate_tlb(0);
 159         init_tlbs();
 160 }
 161
 162 /*
 163  * Breathe some life into the CPU...
 164  *
 165  * Set up the memory map
 166  * initialize a bunch of registers
 167  */
 168
 169 void cpu_init_f (void)
 170 {
 171         volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
 172         extern void m8560_cpm_reset (void);
 173
 174         disable_tlb(14);
 175         disable_tlb(15);
 176
 177 #ifdef CONFIG_CPM2
 178         config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 179 #endif
 180
 181         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 182          * addresses - these have to be modified later when FLASH size
 183          * has been determined
 184          */
 185 #if defined(CFG_OR0_REMAP)
 186         memctl->or0 = CFG_OR0_REMAP;
 187 #endif
 188 #if defined(CFG_OR1_REMAP)
 189         memctl->or1 = CFG_OR1_REMAP;
 190 #endif
 191
 192         /* now restrict to preliminary range */
 193         /* if cs1 is already set via debugger, leave cs0/cs1 alone */
 194         if (! memctl->br1 & 1) {
 195 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
 196                 memctl->br0 = CFG_BR0_PRELIM;
 197                 memctl->or0 = CFG_OR0_PRELIM;
 198 #endif
 199
 200 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
 201                 memctl->or1 = CFG_OR1_PRELIM;
 202                 memctl->br1 = CFG_BR1_PRELIM;
 203 #endif
 204         }
 205
 206 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
 207         memctl->or2 = CFG_OR2_PRELIM;
 208         memctl->br2 = CFG_BR2_PRELIM;
 209 #endif
 210
 211 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
 212         memctl->or3 = CFG_OR3_PRELIM;
 213         memctl->br3 = CFG_BR3_PRELIM;
 214 #endif
 215
 216 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
 217         memctl->or4 = CFG_OR4_PRELIM;
 218         memctl->br4 = CFG_BR4_PRELIM;
 219 #endif
 220
 221 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
 222         memctl->or5 = CFG_OR5_PRELIM;
 223         memctl->br5 = CFG_BR5_PRELIM;
 224 #endif
 225
 226 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
 227         memctl->or6 = CFG_OR6_PRELIM;
 228         memctl->br6 = CFG_BR6_PRELIM;
 229 #endif
 230
 231 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
 232         memctl->or7 = CFG_OR7_PRELIM;
 233         memctl->br7 = CFG_BR7_PRELIM;
 234 #endif
 235
 236 #if defined(CONFIG_CPM2)
 237         m8560_cpm_reset();
 238 #endif
 239 #ifdef CONFIG_QE
 240         /* Config QE ioports */
 241         config_qe_ioports();
 242 #endif
 243
 244 }
 245
 246
 247 /*
 248  * Initialize L2 as cache.
 249  *
 250  * The newer 8548, etc, parts have twice as much cache, but
 251  * use the same bit-encoding as the older 8555, etc, parts.
 252  *
 253  */
 254
 255 int cpu_init_r(void)
 256 {
 257         puts ("L2:    ");
 258
 259 #if defined(CONFIG_L2_CACHE)
 260         volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
 261         volatile uint cache_ctl;
 262         uint svr, ver;
 263         uint l2srbar;
 264
 265         svr = get_svr();
 266         ver = SVR_SOC_VER(svr);
 267
 268         asm("msync;isync");
 269         cache_ctl = l2cache->l2ctl;
 270
 271         switch (cache_ctl & 0x30000000) {
 272         case 0x20000000:
 273                 if (ver == SVR_8548 || ver == SVR_8548_E ||
 274                     ver == SVR_8544 || ver == SVR_8568_E) {
 275                         puts ("512 KB ");
 276                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 277                         cache_ctl = 0xc0000000;
 278                 } else {
 279                         puts("256 KB ");
 280                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 281                         cache_ctl = 0xc8000000;
 282                 }
 283                 break;
 284         case 0x10000000:
 285                 puts("256 KB ");
 286                 if (ver == SVR_8544 || ver == SVR_8544_E) {
 287                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 288                 }
 289                 break;
 290         case 0x30000000:
 291         case 0x00000000:
 292         default:
 293                 printf(" unknown size (0x%08x)\n", cache_ctl);
 294                 return -1;
 295         }
 296
 297         if (l2cache->l2ctl & 0x80000000) {
 298                 puts("already enabled");
 299                 l2srbar = l2cache->l2srbar0;
 300 #ifdef CFG_INIT_L2_ADDR
 301                 if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
 302                         l2srbar = CFG_INIT_L2_ADDR;
 303                         l2cache->l2srbar0 = l2srbar;
 304                         printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
 305                 }
 306 #endif /* CFG_INIT_L2_ADDR */
 307                 puts("\n");
 308         } else {
 309                 asm("msync;isync");
 310                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 311                 asm("msync;isync");
 312                 puts("enabled\n");
 313         }
 314 #else
 315         puts("disabled\n");
 316 #endif
 317 #ifdef CONFIG_QE
 318         uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
 319         qe_init(qe_base);
 320         qe_reset();
 321 #endif
 322
 323 #if defined(CONFIG_MP)
 324         setup_mp();
 325 #endif
 326         return 0;
 327 }