cpu/ppc4xx/ecc.h

   1 /*
   2  *    Copyright (c) 2008 Nuovation System Designs, LLC
   3  *      Grant Erickson <gerickson@nuovations.com>
   4  *
   5  *    Copyright (c) 2007 DENX Software Engineering, GmbH
   6  *      Stefan Roese <sr@denx.de>
   7  *
   8  *    See file CREDITS for list of people who contributed to this
   9  *    project.
  10  *
  11  *    This program is free software; you can redistribute it and/or
  12  *    modify it under the terms of the GNU General Public License as
  13  *    published by the Free Software Foundation; either version 2 of
  14  *    the License, or (at your option) any later version.
  15  *
  16  *    This program is distributed in the hope that it will abe useful,
  17  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  *    GNU General Public License for more details.
  20  *
  21  *    You should have received a copy of the GNU General Public License
  22  *    along with this program; if not, write to the Free Software
  23  *    Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  *    MA 02111-1307 USA
  25  *
  26  *    Description:
  27  *      This file implements ECC initialization for PowerPC processors
  28  *      using the SDRAM DDR2 controller, including the 405EX(r),
  29  *      440SP(E), 460EX and 460GT.
  30  *
  31  */
  32
  33 #ifndef _ECC_H_
  34 #define _ECC_H_
  35
  36 #if !defined(CFG_ECC_PATTERN)
  37 #define CFG_ECC_PATTERN 0x00000000
  38 #endif /* !defined(CFG_ECC_PATTERN) */
  39
  40 /*
  41  * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
  42  * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
  43  * we need to make some processor dependant defines used later on by the
  44  * driver.
  45  */
  46
  47 /* For 440GP/GX/EP/GR */
  48 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
  49 #define SDRAM_ECC_CFG           SDRAM_CFG0
  50 #define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK
  51 #define SDRAM_ECC_CFG_MCHK_GEN  SDRAM_CFG0_MCHK_GEN
  52 #define SDRAM_ECC_CFG_MCHK_CHK  SDRAM_CFG0_MCHK_CHK
  53 #define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK
  54 #define SDRAM_ECC_CFG_DMWD_32   SDRAM_CFG0_DMWD_32
  55 #endif
  56
  57 /* For 405EX/440SP/SPe/460EX/GT */
  58 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  59 #define SDRAM_ECC_CFG           SDRAM_MCOPT1
  60 #define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK
  61 #define SDRAM_ECC_CFG_MCHK_GEN  SDRAM_MCOPT1_MCHK_GEN
  62 #define SDRAM_ECC_CFG_MCHK_CHK  SDRAM_MCOPT1_MCHK_CHK
  63 #define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK
  64 #define SDRAM_ECC_CFG_DMWD_32   SDRAM_MCOPT1_DMWD_32
  65 #endif
  66
  67 extern void ecc_init(unsigned long * const start, unsigned long size);
  68
  69 #endif /* _ECC_H_ */