cpu/ppc4xx/i2c.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
   6  *
   7  * (C) Copyright 2001
   8  * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <ppc4xx.h>
  31 #include <4xx_i2c.h>
  32 #include <i2c.h>
  33 #include <asm-ppc/io.h>
  34
  35 #ifdef CONFIG_HARD_I2C
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #if defined(CONFIG_I2C_MULTI_BUS)
  40 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
  41  * Default is bus 0.  This is necessary because the DDR initialization
  42  * runs from ROM, and we can't switch buses because we can't modify
  43  * the global variables.
  44  */
  45 #ifdef CFG_SPD_BUS_NUM
  46 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
  47 #else
  48 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
  49 #endif
  50 #endif /* CONFIG_I2C_MULTI_BUS */
  51
  52 static void _i2c_bus_reset(void)
  53 {
  54         int i;
  55         u8 dc;
  56
  57         /* Reset status register */
  58         /* write 1 in SCMP and IRQA to clear these fields */
  59         out_8((u8 *)IIC_STS, 0x0A);
  60
  61         /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
  62         out_8((u8 *)IIC_EXTSTS, 0x8F);
  63
  64         /* Place chip in the reset state */
  65         out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
  66
  67         /* Check if bus is free */
  68         dc = in_8((u8 *)IIC_DIRECTCNTL);
  69         if (!DIRCTNL_FREE(dc)){
  70                 /* Try to set bus free state */
  71                 out_8((u8 *)IIC_DIRECTCNTL, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
  72
  73                 /* Wait until we regain bus control */
  74                 for (i = 0; i < 100; ++i) {
  75                         dc = in_8((u8 *)IIC_DIRECTCNTL);
  76                         if (DIRCTNL_FREE(dc))
  77                                 break;
  78
  79                         /* Toggle SCL line */
  80                         dc ^= IIC_DIRCNTL_SCC;
  81                         out_8((u8 *)IIC_DIRECTCNTL, dc);
  82                         udelay(10);
  83                         dc ^= IIC_DIRCNTL_SCC;
  84                         out_8((u8 *)IIC_DIRECTCNTL, dc);
  85                 }
  86         }
  87
  88         /* Remove reset */
  89         out_8((u8 *)IIC_XTCNTLSS, 0);
  90 }
  91
  92 void i2c_init(int speed, int slaveadd)
  93 {
  94         unsigned long freqOPB;
  95         int val, divisor;
  96         int bus;
  97
  98 #ifdef CFG_I2C_INIT_BOARD
  99         /* call board specific i2c bus reset routine before accessing the   */
 100         /* environment, which might be in a chip on that bus. For details   */
 101         /* about this problem see doc/I2C_Edge_Conditions.                  */
 102         i2c_init_board();
 103 #endif
 104
 105         for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) {
 106                 I2C_SET_BUS(bus);
 107
 108                 /* Handle possible failed I2C state */
 109                 /* FIXME: put this into i2c_init_board()? */
 110                 _i2c_bus_reset();
 111
 112                 /* clear lo master address */
 113                 out_8((u8 *)IIC_LMADR, 0);
 114
 115                 /* clear hi master address */
 116                 out_8((u8 *)IIC_HMADR, 0);
 117
 118                 /* clear lo slave address */
 119                 out_8((u8 *)IIC_LSADR, 0);
 120
 121                 /* clear hi slave address */
 122                 out_8((u8 *)IIC_HSADR, 0);
 123
 124                 /* Clock divide Register */
 125                 /* get OPB frequency */
 126                 freqOPB = get_OPB_freq();
 127                 /* set divisor according to freqOPB */
 128                 divisor = (freqOPB - 1) / 10000000;
 129                 if (divisor == 0)
 130                         divisor = 1;
 131                 out_8((u8 *)IIC_CLKDIV, divisor);
 132
 133                 /* no interrupts */
 134                 out_8((u8 *)IIC_INTRMSK, 0);
 135
 136                 /* clear transfer count */
 137                 out_8((u8 *)IIC_XFRCNT, 0);
 138
 139                 /* clear extended control & stat */
 140                 /* write 1 in SRC SRS SWC SWS to clear these fields */
 141                 out_8((u8 *)IIC_XTCNTLSS, 0xF0);
 142
 143                 /* Mode Control Register
 144                    Flush Slave/Master data buffer */
 145                 out_8((u8 *)IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
 146
 147                 val = in_8((u8 *)IIC_MDCNTL);
 148
 149                 /* Ignore General Call, slave transfers are ignored,
 150                  * disable interrupts, exit unknown bus state, enable hold
 151                  * SCL 100kHz normaly or FastMode for 400kHz and above
 152                  */
 153
 154                 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
 155                 if (speed >= 400000)
 156                         val |= IIC_MDCNTL_FSM;
 157                 out_8((u8 *)IIC_MDCNTL, val);
 158
 159                 /* clear control reg */
 160                 out_8((u8 *)IIC_CNTL, 0x00);
 161         }
 162
 163         /* set to SPD bus as default bus upon powerup */
 164         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 165 }
 166
 167 /*
 168  * This code tries to use the features of the 405GP i2c
 169  * controller. It will transfer up to 4 bytes in one pass
 170  * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
 171  * is possible to do out16(lhz) transfers.
 172  *
 173  * cmd_type is 0 for write 1 for read.
 174  *
 175  * addr_len can take any value from 0-255, it is only limited
 176  * by the char, we could make it larger if needed. If it is
 177  * 0 we skip the address write cycle.
 178  *
 179  * Typical case is a Write of an addr followd by a Read. The
 180  * IBM FAQ does not cover this. On the last byte of the write
 181  * we don't set the creg CHT bit, and on the first bytes of the
 182  * read we set the RPST bit.
 183  *
 184  * It does not support address only transfers, there must be
 185  * a data part. If you want to write the address yourself, put
 186  * it in the data pointer.
 187  *
 188  * It does not support transfer to/from address 0.
 189  *
 190  * It does not check XFRCNT.
 191  */
 192 static int i2c_transfer(unsigned char cmd_type,
 193                         unsigned char chip,
 194                         unsigned char addr[],
 195                         unsigned char addr_len,
 196                         unsigned char data[],
 197                         unsigned short data_len)
 198 {
 199         unsigned char* ptr;
 200         int reading;
 201         int tran,cnt;
 202         int result;
 203         int status;
 204         int i;
 205         uchar creg;
 206
 207         if (data == 0 || data_len == 0) {
 208                 /* Don't support data transfer of no length or to address 0 */
 209                 printf( "i2c_transfer: bad call\n" );
 210                 return IIC_NOK;
 211         }
 212         if (addr && addr_len) {
 213                 ptr = addr;
 214                 cnt = addr_len;
 215                 reading = 0;
 216         } else {
 217                 ptr = data;
 218                 cnt = data_len;
 219                 reading = cmd_type;
 220         }
 221
 222         /* Clear Stop Complete Bit */
 223         out_8((u8 *)IIC_STS, IIC_STS_SCMP);
 224         /* Check init */
 225         i = 10;
 226         do {
 227                 /* Get status */
 228                 status = in_8((u8 *)IIC_STS);
 229                 i--;
 230         } while ((status & IIC_STS_PT) && (i > 0));
 231
 232         if (status & IIC_STS_PT) {
 233                 result = IIC_NOK_TOUT;
 234                 return(result);
 235         }
 236         /* flush the Master/Slave Databuffers */
 237         out_8((u8 *)IIC_MDCNTL, ((in_8((u8 *)IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
 238         /* need to wait 4 OPB clocks? code below should take that long */
 239
 240         /* 7-bit adressing */
 241         out_8((u8 *)IIC_HMADR, 0);
 242         out_8((u8 *)IIC_LMADR, chip);
 243
 244         tran = 0;
 245         result = IIC_OK;
 246         creg = 0;
 247
 248         while (tran != cnt && (result == IIC_OK)) {
 249                 int  bc,j;
 250
 251                 /* Control register =
 252                  * Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
 253                  * Transfer is a sequence of transfers
 254                  */
 255                 creg |= IIC_CNTL_PT;
 256
 257                 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
 258                 creg |= (bc - 1) << 4;
 259                 /* if the real cmd type is write continue trans */
 260                 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
 261                         creg |= IIC_CNTL_CHT;
 262
 263                 if (reading)
 264                         creg |= IIC_CNTL_READ;
 265                 else
 266                         for(j=0; j < bc; j++)
 267                                 /* Set buffer */
 268                                 out_8((u8 *)IIC_MDBUF, ptr[tran+j]);
 269                 out_8((u8 *)IIC_CNTL, creg);
 270
 271                 /* Transfer is in progress
 272                  * we have to wait for upto 5 bytes of data
 273                  * 1 byte chip address+r/w bit then bc bytes
 274                  * of data.
 275                  * udelay(10) is 1 bit time at 100khz
 276                  * Doubled for slop. 20 is too small.
 277                  */
 278                 i = 2*5*8;
 279                 do {
 280                         /* Get status */
 281                         status = in_8((u8 *)IIC_STS);
 282                         udelay(10);
 283                         i--;
 284                 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && (i > 0));
 285
 286                 if (status & IIC_STS_ERR) {
 287                         result = IIC_NOK;
 288                         status = in_8((u8 *)IIC_EXTSTS);
 289                         /* Lost arbitration? */
 290                         if (status & IIC_EXTSTS_LA)
 291                                 result = IIC_NOK_LA;
 292                         /* Incomplete transfer? */
 293                         if (status & IIC_EXTSTS_ICT)
 294                                 result = IIC_NOK_ICT;
 295                         /* Transfer aborted? */
 296                         if (status & IIC_EXTSTS_XFRA)
 297                                 result = IIC_NOK_XFRA;
 298                 } else if ( status & IIC_STS_PT) {
 299                         result = IIC_NOK_TOUT;
 300                 }
 301                 /* Command is reading => get buffer */
 302                 if ((reading) && (result == IIC_OK)) {
 303                         /* Are there data in buffer */
 304                         if (status & IIC_STS_MDBS) {
 305                                 /*
 306                                  * even if we have data we have to wait 4OPB clocks
 307                                  * for it to hit the front of the FIFO, after that
 308                                  * we can just read. We should check XFCNT here and
 309                                  * if the FIFO is full there is no need to wait.
 310                                  */
 311                                 udelay(1);
 312                                 for (j=0; j<bc; j++)
 313                                         ptr[tran+j] = in_8((u8 *)IIC_MDBUF);
 314                         } else
 315                                 result = IIC_NOK_DATA;
 316                 }
 317                 creg = 0;
 318                 tran += bc;
 319                 if (ptr == addr && tran == cnt) {
 320                         ptr = data;
 321                         cnt = data_len;
 322                         tran = 0;
 323                         reading = cmd_type;
 324                         if (reading)
 325                                 creg = IIC_CNTL_RPST;
 326                 }
 327         }
 328         return (result);
 329 }
 330
 331 int i2c_probe(uchar chip)
 332 {
 333         uchar buf[1];
 334
 335         buf[0] = 0;
 336
 337         /*
 338          * What is needed is to send the chip address and verify that the
 339          * address was <ACK>ed (i.e. there was a chip at that address which
 340          * drove the data line low).
 341          */
 342         return (i2c_transfer(1, chip << 1, 0,0, buf, 1) != 0);
 343 }
 344
 345
 346 int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 347 {
 348         uchar xaddr[4];
 349         int ret;
 350
 351         if (alen > 4) {
 352                 printf ("I2C read: addr len %d not supported\n", alen);
 353                 return 1;
 354         }
 355
 356         if (alen > 0) {
 357                 xaddr[0] = (addr >> 24) & 0xFF;
 358                 xaddr[1] = (addr >> 16) & 0xFF;
 359                 xaddr[2] = (addr >> 8) & 0xFF;
 360                 xaddr[3] = addr & 0xFF;
 361         }
 362
 363
 364 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 365         /*
 366          * EEPROM chips that implement "address overflow" are ones
 367          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 368          * address and the extra bits end up in the "chip address"
 369          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 370          * four 256 byte chips.
 371          *
 372          * Note that we consider the length of the address field to
 373          * still be one byte because the extra address bits are
 374          * hidden in the chip address.
 375          */
 376         if (alen > 0)
 377                 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 378 #endif
 379         if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
 380                 if (gd->have_console)
 381                         printf( "I2c read: failed %d\n", ret);
 382                 return 1;
 383         }
 384         return 0;
 385 }
 386
 387 int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 388 {
 389         uchar xaddr[4];
 390
 391         if (alen > 4) {
 392                 printf ("I2C write: addr len %d not supported\n", alen);
 393                 return 1;
 394
 395         }
 396
 397         if (alen > 0) {
 398                 xaddr[0] = (addr >> 24) & 0xFF;
 399                 xaddr[1] = (addr >> 16) & 0xFF;
 400                 xaddr[2] = (addr >> 8) & 0xFF;
 401                 xaddr[3] = addr & 0xFF;
 402         }
 403
 404 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 405         /*
 406          * EEPROM chips that implement "address overflow" are ones
 407          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 408          * address and the extra bits end up in the "chip address"
 409          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 410          * four 256 byte chips.
 411          *
 412          * Note that we consider the length of the address field to
 413          * still be one byte because the extra address bits are
 414          * hidden in the chip address.
 415          */
 416         if (alen > 0)
 417                 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 418 #endif
 419
 420         return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 421 }
 422
 423 /*-----------------------------------------------------------------------
 424  * Read a register
 425  */
 426 uchar i2c_reg_read(uchar i2c_addr, uchar reg)
 427 {
 428         uchar buf;
 429
 430         i2c_read(i2c_addr, reg, 1, &buf, 1);
 431
 432         return (buf);
 433 }
 434
 435 /*-----------------------------------------------------------------------
 436  * Write a register
 437  */
 438 void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 439 {
 440         i2c_write(i2c_addr, reg, 1, &val, 1);
 441 }
 442
 443 #if defined(CONFIG_I2C_MULTI_BUS)
 444 /*
 445  * Functions for multiple I2C bus handling
 446  */
 447 unsigned int i2c_get_bus_num(void)
 448 {
 449         return i2c_bus_num;
 450 }
 451
 452 int i2c_set_bus_num(unsigned int bus)
 453 {
 454         if (bus >= CFG_MAX_I2C_BUS)
 455                 return -1;
 456
 457         i2c_bus_num = bus;
 458
 459         return 0;
 460 }
 461 #endif  /* CONFIG_I2C_MULTI_BUS */
 462
 463 /* TODO: add 100/400k switching */
 464 unsigned int i2c_get_bus_speed(void)
 465 {
 466         return CFG_I2C_SPEED;
 467 }
 468
 469 int i2c_set_bus_speed(unsigned int speed)
 470 {
 471         if (speed != CFG_I2C_SPEED)
 472                 return -1;
 473
 474         return 0;
 475 }
 476 #endif  /* CONFIG_HARD_I2C */