| blob | 426bf3c6f9a966b21917e4d2348b56dfc5b3c9cf |
1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27 /*------------------------------------------------------------------------------+
28 *
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
35 *
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
39 *
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
43 *
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
46 *-------------------------------------------------------------------------------
47 */
49 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
50 *
51 *
52 * The processor starts at 0xfffffffc and the code is executed
53 * from flash/rom.
54 * in memory, but as long we don't jump around before relocating.
55 * board_init lies at a quite high address and when the cpu has
56 * jumped there, everything is ok.
57 * This works because the cpu gives the FLASH (CS0) the whole
58 * address space at startup, and board_init lies as a echo of
59 * the flash somewhere up there in the memorymap.
60 *
61 * board_init will change CS0 to be positioned at the correct
62 * address and (s)dram will be positioned at address 0
63 */
64 #include <config.h>
65 #include <ppc4xx.h>
66 #include <version.h>
68 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
70 #include <ppc_asm.tmpl>
71 #include <ppc_defs.h>
73 #include <asm/cache.h>
74 #include <asm/mmu.h>
76 #ifndef CONFIG_IDENT_STRING
77 #define CONFIG_IDENT_STRING ""
78 #endif
80 #ifdef CFG_INIT_DCACHE_CS
81 # if (CFG_INIT_DCACHE_CS == 0)
82 # define PBxAP pb0ap
83 # define PBxCR pb0cr
84 # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
85 # define PBxAP_VAL CFG_EBC_PB0AP
86 # define PBxCR_VAL CFG_EBC_PB0CR
87 # endif
88 # endif
89 # if (CFG_INIT_DCACHE_CS == 1)
90 # define PBxAP pb1ap
91 # define PBxCR pb1cr
92 # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
93 # define PBxAP_VAL CFG_EBC_PB1AP
94 # define PBxCR_VAL CFG_EBC_PB1CR
95 # endif
96 # endif
97 # if (CFG_INIT_DCACHE_CS == 2)
98 # define PBxAP pb2ap
99 # define PBxCR pb2cr
100 # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
101 # define PBxAP_VAL CFG_EBC_PB2AP
102 # define PBxCR_VAL CFG_EBC_PB2CR
103 # endif
104 # endif
105 # if (CFG_INIT_DCACHE_CS == 3)
106 # define PBxAP pb3ap
107 # define PBxCR pb3cr
108 # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
109 # define PBxAP_VAL CFG_EBC_PB3AP
110 # define PBxCR_VAL CFG_EBC_PB3CR
111 # endif
112 # endif
113 # if (CFG_INIT_DCACHE_CS == 4)
114 # define PBxAP pb4ap
115 # define PBxCR pb4cr
116 # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
117 # define PBxAP_VAL CFG_EBC_PB4AP
118 # define PBxCR_VAL CFG_EBC_PB4CR
119 # endif
120 # endif
121 # if (CFG_INIT_DCACHE_CS == 5)
122 # define PBxAP pb5ap
123 # define PBxCR pb5cr
124 # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
125 # define PBxAP_VAL CFG_EBC_PB5AP
126 # define PBxCR_VAL CFG_EBC_PB5CR
127 # endif
128 # endif
129 # if (CFG_INIT_DCACHE_CS == 6)
130 # define PBxAP pb6ap
131 # define PBxCR pb6cr
132 # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
133 # define PBxAP_VAL CFG_EBC_PB6AP
134 # define PBxCR_VAL CFG_EBC_PB6CR
135 # endif
136 # endif
137 # if (CFG_INIT_DCACHE_CS == 7)
138 # define PBxAP pb7ap
139 # define PBxCR pb7cr
140 # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
141 # define PBxAP_VAL CFG_EBC_PB7AP
142 # define PBxCR_VAL CFG_EBC_PB7CR
143 # endif
144 # endif
145 # ifndef PBxAP_VAL
146 # define PBxAP_VAL 0
147 # endif
148 # ifndef PBxCR_VAL
149 # define PBxCR_VAL 0
150 # endif
151 /*
152 * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
153 * used as temporary stack pointer for the primordial stack
154 */
155 # ifndef CFG_INIT_DCACHE_PBxAR
156 # define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
157 EBC_BXAP_TWT_ENCODE(7) | \
158 EBC_BXAP_BCE_DISABLE | \
159 EBC_BXAP_BCT_2TRANS | \
160 EBC_BXAP_CSN_ENCODE(0) | \
161 EBC_BXAP_OEN_ENCODE(0) | \
162 EBC_BXAP_WBN_ENCODE(0) | \
163 EBC_BXAP_WBF_ENCODE(0) | \
164 EBC_BXAP_TH_ENCODE(2) | \
165 EBC_BXAP_RE_DISABLED | \
166 EBC_BXAP_SOR_NONDELAYED | \
167 EBC_BXAP_BEM_WRITEONLY | \
168 EBC_BXAP_PEN_DISABLED)
169 # endif /* CFG_INIT_DCACHE_PBxAR */
170 # ifndef CFG_INIT_DCACHE_PBxCR
171 # define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \
172 EBC_BXCR_BS_64MB | \
173 EBC_BXCR_BU_RW | \
174 EBC_BXCR_BW_16BIT)
175 # endif /* CFG_INIT_DCACHE_PBxCR */
176 # ifndef CFG_INIT_RAM_PATTERN
177 # define CFG_INIT_RAM_PATTERN 0xDEADDEAD
178 # endif
179 #endif /* CFG_INIT_DCACHE_CS */
181 #if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
182 #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
183 #endif
185 /*
186 * Unless otherwise overriden, enable two 128MB cachable instruction regions
187 * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
188 * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
189 */
190 #if !defined(CFG_FLASH_BASE)
191 /* If not already defined, set it to the "last" 128MByte region */
192 # define CFG_FLASH_BASE 0xf8000000
193 #endif
194 #if !defined(CFG_ICACHE_SACR_VALUE)
195 # define CFG_ICACHE_SACR_VALUE \
196 (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \
197 PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \
198 PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
199 #endif /* !defined(CFG_ICACHE_SACR_VALUE) */
201 #if !defined(CFG_DCACHE_SACR_VALUE)
202 # define CFG_DCACHE_SACR_VALUE \
203 (0x00000000)
204 #endif /* !defined(CFG_DCACHE_SACR_VALUE) */
206 #define function_prolog(func_name) .text; \
207 .align 2; \
208 .globl func_name; \
209 func_name:
210 #define function_epilog(func_name) .type func_name,@function; \
211 .size func_name,.-func_name
213 /* We don't want the MMU yet.
214 */
215 #undef MSR_KERNEL
216 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
219 .extern ext_bus_cntlr_init
220 #ifdef CONFIG_NAND_U_BOOT
221 .extern reconfig_tlb0
222 #endif
224 /*
225 * Set up GOT: Global Offset Table
226 *
227 * Use r14 to access the GOT
228 */
229 #if !defined(CONFIG_NAND_SPL)
230 START_GOT
231 GOT_ENTRY(_GOT2_TABLE_)
232 GOT_ENTRY(_FIXUP_TABLE_)
234 GOT_ENTRY(_start)
235 GOT_ENTRY(_start_of_vectors)
236 GOT_ENTRY(_end_of_vectors)
237 GOT_ENTRY(transfer_to_handler)
239 GOT_ENTRY(__init_end)
240 GOT_ENTRY(_end)
241 GOT_ENTRY(__bss_start)
242 END_GOT
243 #endif /* CONFIG_NAND_SPL */
245 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
246 /*
247 * NAND U-Boot image is started from offset 0
248 */
249 .text
250 #if defined(CONFIG_440)
251 bl reconfig_tlb0
252 #endif
253 GET_GOT
254 bl cpu_init_f /* run low-level CPU init code (from Flash) */
255 bl board_init_f
256 #endif
258 /*
259 * 440 Startup -- on reset only the top 4k of the effective
260 * address space is mapped in by an entry in the instruction
261 * and data shadow TLB. The .bootpg section is located in the
262 * top 4k & does only what's necessary to map in the the rest
263 * of the boot rom. Once the boot rom is mapped in we can
264 * proceed with normal startup.
265 *
266 * NOTE: CS0 only covers the top 2MB of the effective address
267 * space after reset.
268 */
270 #if defined(CONFIG_440)
271 #if !defined(CONFIG_NAND_SPL)
272 .section .bootpg,"ax"
273 #endif
274 .globl _start_440
276 /**************************************************************************/
277 _start_440:
278 /*--------------------------------------------------------------------+
279 | 440EPX BUP Change - Hardware team request
280 +--------------------------------------------------------------------*/
281 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
282 sync
283 nop
284 nop
285 #endif
286 /*----------------------------------------------------------------+
287 | Core bug fix. Clear the esr
288 +-----------------------------------------------------------------*/
289 li r0,0
290 mtspr esr,r0
291 /*----------------------------------------------------------------*/
292 /* Clear and set up some registers. */
293 /*----------------------------------------------------------------*/
294 iccci r0,r0 /* NOTE: operands not used for 440 */
295 dccci r0,r0 /* NOTE: operands not used for 440 */
296 sync
297 li r0,0
298 mtspr srr0,r0
299 mtspr srr1,r0
300 mtspr csrr0,r0
301 mtspr csrr1,r0
302 /* NOTE: 440GX adds machine check status regs */
303 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
304 mtspr mcsrr0,r0
305 mtspr mcsrr1,r0
306 mfspr r1,mcsr
307 mtspr mcsr,r1
308 #endif
310 /*----------------------------------------------------------------*/
311 /* CCR0 init */
312 /*----------------------------------------------------------------*/
313 /* Disable store gathering & broadcast, guarantee inst/data
314 * cache block touch, force load/store alignment
315 * (see errata 1.12: 440_33)
316 */
317 lis r1,0x0030 /* store gathering & broadcast disable */
318 ori r1,r1,0x6000 /* cache touch */
319 mtspr ccr0,r1
321 /*----------------------------------------------------------------*/
322 /* Initialize debug */
323 /*----------------------------------------------------------------*/
324 mfspr r1,dbcr0
325 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
326 bne skip_debug_init /* if set, don't clear debug register */
327 mtspr dbcr0,r0
328 mtspr dbcr1,r0
329 mtspr dbcr2,r0
330 mtspr iac1,r0
331 mtspr iac2,r0
332 mtspr iac3,r0
333 mtspr dac1,r0
334 mtspr dac2,r0
335 mtspr dvc1,r0
336 mtspr dvc2,r0
338 mfspr r1,dbsr
339 mtspr dbsr,r1 /* Clear all valid bits */
340 skip_debug_init:
342 #if defined (CONFIG_440SPE)
343 /*----------------------------------------------------------------+
344 | Initialize Core Configuration Reg1.
345 | a. ICDPEI: Record even parity. Normal operation.
346 | b. ICTPEI: Record even parity. Normal operation.
347 | c. DCTPEI: Record even parity. Normal operation.
348 | d. DCDPEI: Record even parity. Normal operation.
349 | e. DCUPEI: Record even parity. Normal operation.
350 | f. DCMPEI: Record even parity. Normal operation.
351 | g. FCOM: Normal operation
352 | h. MMUPEI: Record even parity. Normal operation.
353 | i. FFF: Flush only as much data as necessary.
354 | j. TCS: Timebase increments from CPU clock.
355 +-----------------------------------------------------------------*/
356 li r0,0
357 mtspr ccr1, r0
359 /*----------------------------------------------------------------+
360 | Reset the timebase.
361 | The previous write to CCR1 sets the timebase source.
362 +-----------------------------------------------------------------*/
363 mtspr tbl, r0
364 mtspr tbu, r0
365 #endif
367 /*----------------------------------------------------------------*/
368 /* Setup interrupt vectors */
369 /*----------------------------------------------------------------*/
370 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
371 li r1,0x0100
372 mtspr ivor0,r1 /* Critical input */
373 li r1,0x0200
374 mtspr ivor1,r1 /* Machine check */
375 li r1,0x0300
376 mtspr ivor2,r1 /* Data storage */
377 li r1,0x0400
378 mtspr ivor3,r1 /* Instruction storage */
379 li r1,0x0500
380 mtspr ivor4,r1 /* External interrupt */
381 li r1,0x0600
382 mtspr ivor5,r1 /* Alignment */
383 li r1,0x0700
384 mtspr ivor6,r1 /* Program check */
385 li r1,0x0800
386 mtspr ivor7,r1 /* Floating point unavailable */
387 li r1,0x0c00
388 mtspr ivor8,r1 /* System call */
389 li r1,0x0a00
390 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
391 li r1,0x0900
392 mtspr ivor10,r1 /* Decrementer */
393 li r1,0x1300
394 mtspr ivor13,r1 /* Data TLB error */
395 li r1,0x1400
396 mtspr ivor14,r1 /* Instr TLB error */
397 li r1,0x2000
398 mtspr ivor15,r1 /* Debug */
400 /*----------------------------------------------------------------*/
401 /* Configure cache regions */
402 /*----------------------------------------------------------------*/
403 mtspr inv0,r0
404 mtspr inv1,r0
405 mtspr inv2,r0
406 mtspr inv3,r0
407 mtspr dnv0,r0
408 mtspr dnv1,r0
409 mtspr dnv2,r0
410 mtspr dnv3,r0
411 mtspr itv0,r0
412 mtspr itv1,r0
413 mtspr itv2,r0
414 mtspr itv3,r0
415 mtspr dtv0,r0
416 mtspr dtv1,r0
417 mtspr dtv2,r0
418 mtspr dtv3,r0
420 /*----------------------------------------------------------------*/
421 /* Cache victim limits */
422 /*----------------------------------------------------------------*/
423 /* floors 0, ceiling max to use the entire cache -- nothing locked
424 */
425 lis r1,0x0001
426 ori r1,r1,0xf800
427 mtspr ivlim,r1
428 mtspr dvlim,r1
430 /*----------------------------------------------------------------+
431 |Initialize MMUCR[STID] = 0.
432 +-----------------------------------------------------------------*/
433 mfspr r0,mmucr
434 addis r1,0,0xFFFF
435 ori r1,r1,0xFF00
436 and r0,r0,r1
437 mtspr mmucr,r0
439 /*----------------------------------------------------------------*/
440 /* Clear all TLB entries -- TID = 0, TS = 0 */
441 /*----------------------------------------------------------------*/
442 addis r0,0,0x0000
443 li r1,0x003f /* 64 TLB entries */
444 mtctr r1
445 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
446 tlbwe r0,r1,0x0001
447 tlbwe r0,r1,0x0002
448 subi r1,r1,0x0001
449 bdnz rsttlb
451 /*----------------------------------------------------------------*/
452 /* TLB entry setup -- step thru tlbtab */
453 /*----------------------------------------------------------------*/
454 #if defined(CONFIG_440SPE)
455 /*----------------------------------------------------------------*/
456 /* We have different TLB tables for revA and rev B of 440SPe */
457 /*----------------------------------------------------------------*/
458 mfspr r1, PVR
459 lis r0,0x5342
460 ori r0,r0,0x1891
461 cmpw r7,r1,r0
462 bne r7,..revA
463 bl tlbtabB
464 b ..goon
465 ..revA:
466 bl tlbtabA
467 ..goon:
468 #else
469 bl tlbtab /* Get tlbtab pointer */
470 #endif
471 mr r5,r0
472 li r1,0x003f /* 64 TLB entries max */
473 mtctr r1
474 li r4,0 /* TLB # */
476 addi r5,r5,-4
477 1: lwzu r0,4(r5)
478 cmpwi r0,0
479 beq 2f /* 0 marks end */
480 lwzu r1,4(r5)
481 lwzu r2,4(r5)
482 tlbwe r0,r4,0 /* TLB Word 0 */
483 tlbwe r1,r4,1 /* TLB Word 1 */
484 tlbwe r2,r4,2 /* TLB Word 2 */
485 addi r4,r4,1 /* Next TLB */
486 bdnz 1b
488 /*----------------------------------------------------------------*/
489 /* Continue from 'normal' start */
490 /*----------------------------------------------------------------*/
491 2:
492 bl 3f
493 b _start
495 3: li r0,0
496 mtspr srr1,r0 /* Keep things disabled for now */
497 mflr r1
498 mtspr srr0,r1
499 rfi
500 #endif /* CONFIG_440 */
502 /*
503 * r3 - 1st arg to board_init(): IMMP pointer
504 * r4 - 2nd arg to board_init(): boot flag
505 */
506 #ifndef CONFIG_NAND_SPL
507 .text
508 .long 0x27051956 /* U-Boot Magic Number */
509 .globl version_string
510 version_string:
511 .ascii U_BOOT_VERSION
512 .ascii " (", __DATE__, " - ", __TIME__, ")"
513 .ascii CONFIG_IDENT_STRING, "\0"
515 . = EXC_OFF_SYS_RESET
516 .globl _start_of_vectors
517 _start_of_vectors:
519 /* Critical input. */
520 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
522 #ifdef CONFIG_440
523 /* Machine check */
524 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
525 #else
526 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
527 #endif /* CONFIG_440 */
529 /* Data Storage exception. */
530 STD_EXCEPTION(0x300, DataStorage, UnknownException)
532 /* Instruction Storage exception. */
533 STD_EXCEPTION(0x400, InstStorage, UnknownException)
535 /* External Interrupt exception. */
536 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
538 /* Alignment exception. */
539 . = 0x600
540 Alignment:
541 EXCEPTION_PROLOG(SRR0, SRR1)
542 mfspr r4,DAR
543 stw r4,_DAR(r21)
544 mfspr r5,DSISR
545 stw r5,_DSISR(r21)
546 addi r3,r1,STACK_FRAME_OVERHEAD
547 li r20,MSR_KERNEL
548 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
549 lwz r6,GOT(transfer_to_handler)
550 mtlr r6
551 blrl
552 .L_Alignment:
553 .long AlignmentException - _start + _START_OFFSET
554 .long int_return - _start + _START_OFFSET
556 /* Program check exception */
557 . = 0x700
558 ProgramCheck:
559 EXCEPTION_PROLOG(SRR0, SRR1)
560 addi r3,r1,STACK_FRAME_OVERHEAD
561 li r20,MSR_KERNEL
562 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
563 lwz r6,GOT(transfer_to_handler)
564 mtlr r6
565 blrl
566 .L_ProgramCheck:
567 .long ProgramCheckException - _start + _START_OFFSET
568 .long int_return - _start + _START_OFFSET
570 #ifdef CONFIG_440
571 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
572 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
573 STD_EXCEPTION(0xa00, APU, UnknownException)
574 #endif
575 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
577 #ifdef CONFIG_440
578 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
579 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
580 #else
581 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
582 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
583 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
584 #endif
585 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
587 .globl _end_of_vectors
588 _end_of_vectors:
589 . = _START_OFFSET
590 #endif
591 .globl _start
592 _start:
594 /*****************************************************************************/
595 #if defined(CONFIG_440)
597 /*----------------------------------------------------------------*/
598 /* Clear and set up some registers. */
599 /*----------------------------------------------------------------*/
600 li r0,0x0000
601 lis r1,0xffff
602 mtspr dec,r0 /* prevent dec exceptions */
603 mtspr tbl,r0 /* prevent fit & wdt exceptions */
604 mtspr tbu,r0
605 mtspr tsr,r1 /* clear all timer exception status */
606 mtspr tcr,r0 /* disable all */
607 mtspr esr,r0 /* clear exception syndrome register */
608 mtxer r0 /* clear integer exception register */
610 /*----------------------------------------------------------------*/
611 /* Debug setup -- some (not very good) ice's need an event*/
612 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
613 /* value you need in this case 0x8cff 0000 should do the trick */
614 /*----------------------------------------------------------------*/
615 #if defined(CFG_INIT_DBCR)
616 lis r1,0xffff
617 ori r1,r1,0xffff
618 mtspr dbsr,r1 /* Clear all status bits */
619 lis r0,CFG_INIT_DBCR@h
620 ori r0,r0,CFG_INIT_DBCR@l
621 mtspr dbcr0,r0
622 isync
623 #endif
625 /*----------------------------------------------------------------*/
626 /* Setup the internal SRAM */
627 /*----------------------------------------------------------------*/
628 li r0,0
630 #ifdef CFG_INIT_RAM_DCACHE
631 /* Clear Dcache to use as RAM */
632 addis r3,r0,CFG_INIT_RAM_ADDR@h
633 ori r3,r3,CFG_INIT_RAM_ADDR@l
634 addis r4,r0,CFG_INIT_RAM_END@h
635 ori r4,r4,CFG_INIT_RAM_END@l
636 rlwinm. r5,r4,0,27,31
637 rlwinm r5,r4,27,5,31
638 beq ..d_ran
639 addi r5,r5,0x0001
640 ..d_ran:
641 mtctr r5
642 ..d_ag:
643 dcbz r0,r3
644 addi r3,r3,32
645 bdnz ..d_ag
647 /*
648 * Lock the init-ram/stack in d-cache, so that other regions
649 * may use d-cache as well
650 * Note, that this current implementation locks exactly 4k
651 * of d-cache, so please make sure that you don't define a
652 * bigger init-ram area. Take a look at the lwmon5 440EPx
653 * implementation as a reference.
654 */
655 msync
656 isync
657 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
658 lis r1,0x0201
659 ori r1,r1,0xf808
660 mtspr dvlim,r1
661 lis r1,0x0808
662 ori r1,r1,0x0808
663 mtspr dnv0,r1
664 mtspr dnv1,r1
665 mtspr dnv2,r1
666 mtspr dnv3,r1
667 mtspr dtv0,r1
668 mtspr dtv1,r1
669 mtspr dtv2,r1
670 mtspr dtv3,r1
671 msync
672 isync
673 #endif /* CFG_INIT_RAM_DCACHE */
675 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
676 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
677 /* not all PPC's have internal SRAM usable as L2-cache */
678 #if defined(CONFIG_440GX) || \
679 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
680 defined(CONFIG_460EX) || defined(CONFIG_460GT)
681 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
682 #endif
684 lis r2,0x7fff
685 ori r2,r2,0xffff
686 mfdcr r1,isram0_dpc
687 and r1,r1,r2 /* Disable parity check */
688 mtdcr isram0_dpc,r1
689 mfdcr r1,isram0_pmeg
690 and r1,r1,r2 /* Disable pwr mgmt */
691 mtdcr isram0_pmeg,r1
693 lis r1,0x8000 /* BAS = 8000_0000 */
694 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
695 ori r1,r1,0x0980 /* first 64k */
696 mtdcr isram0_sb0cr,r1
697 lis r1,0x8001
698 ori r1,r1,0x0980 /* second 64k */
699 mtdcr isram0_sb1cr,r1
700 lis r1, 0x8002
701 ori r1,r1, 0x0980 /* third 64k */
702 mtdcr isram0_sb2cr,r1
703 lis r1, 0x8003
704 ori r1,r1, 0x0980 /* fourth 64k */
705 mtdcr isram0_sb3cr,r1
706 #elif defined(CONFIG_440SPE)
707 lis r1,0x0000 /* BAS = 0000_0000 */
708 ori r1,r1,0x0984 /* first 64k */
709 mtdcr isram0_sb0cr,r1
710 lis r1,0x0001
711 ori r1,r1,0x0984 /* second 64k */
712 mtdcr isram0_sb1cr,r1
713 lis r1, 0x0002
714 ori r1,r1, 0x0984 /* third 64k */
715 mtdcr isram0_sb2cr,r1
716 lis r1, 0x0003
717 ori r1,r1, 0x0984 /* fourth 64k */
718 mtdcr isram0_sb3cr,r1
719 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
720 lis r1,0x4000 /* BAS = 8000_0000 */
721 ori r1,r1,0x4580 /* 16k */
722 mtdcr isram0_sb0cr,r1
723 #elif defined(CONFIG_440GP)
724 ori r1,r1,0x0380 /* 8k rw */
725 mtdcr isram0_sb0cr,r1
726 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
727 #endif
728 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
730 /*----------------------------------------------------------------*/
731 /* Setup the stack in internal SRAM */
732 /*----------------------------------------------------------------*/
733 lis r1,CFG_INIT_RAM_ADDR@h
734 ori r1,r1,CFG_INIT_SP_OFFSET@l
735 li r0,0
736 stwu r0,-4(r1)
737 stwu r0,-4(r1) /* Terminate call chain */
739 stwu r1,-8(r1) /* Save back chain and move SP */
740 lis r0,RESET_VECTOR@h /* Address of reset vector */
741 ori r0,r0, RESET_VECTOR@l
742 stwu r1,-8(r1) /* Save back chain and move SP */
743 stw r0,+12(r1) /* Save return addr (underflow vect) */
745 #ifdef CONFIG_NAND_SPL
746 bl nand_boot_common /* will not return */
747 #else
748 GET_GOT
750 bl cpu_init_f /* run low-level CPU init code (from Flash) */
751 bl board_init_f
752 #endif
754 #endif /* CONFIG_440 */
756 /*****************************************************************************/
757 #ifdef CONFIG_IOP480
758 /*----------------------------------------------------------------------- */
759 /* Set up some machine state registers. */
760 /*----------------------------------------------------------------------- */
761 addi r0,r0,0x0000 /* initialize r0 to zero */
762 mtspr esr,r0 /* clear Exception Syndrome Reg */
763 mttcr r0 /* timer control register */
764 mtexier r0 /* disable all interrupts */
765 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
766 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
767 mtdbsr r4 /* clear/reset the dbsr */
768 mtexisr r4 /* clear all pending interrupts */
769 addis r4,r0,0x8000
770 mtexier r4 /* enable critical exceptions */
771 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
772 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
773 mtiocr r4 /* since bit not used) & DRC to latch */
774 /* data bus on rising edge of CAS */
775 /*----------------------------------------------------------------------- */
776 /* Clear XER. */
777 /*----------------------------------------------------------------------- */
778 mtxer r0
779 /*----------------------------------------------------------------------- */
780 /* Invalidate i-cache and d-cache TAG arrays. */
781 /*----------------------------------------------------------------------- */
782 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
783 addi r4,0,1024 /* 1/4 of I-cache */
784 ..cloop:
785 iccci 0,r3
786 iccci r4,r3
787 dccci 0,r3
788 addic. r3,r3,-16 /* move back one cache line */
789 bne ..cloop /* loop back to do rest until r3 = 0 */
791 /* */
792 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
793 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
794 /* */
796 /* first copy IOP480 register base address into r3 */
797 addis r3,0,0x5000 /* IOP480 register base address hi */
798 /* ori r3,r3,0x0000 / IOP480 register base address lo */
800 #ifdef CONFIG_ADCIOP
801 /* use r4 as the working variable */
802 /* turn on CS3 (LOCCTL.7) */
803 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
804 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
805 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
806 #endif
808 #ifdef CONFIG_DASA_SIM
809 /* use r4 as the working variable */
810 /* turn on MA17 (LOCCTL.7) */
811 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
812 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
813 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
814 #endif
816 /* turn on MA16..13 (LCS0BRD.12 = 0) */
817 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
818 andi. r4,r4,0xefff /* make bit 12 = 0 */
819 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
821 /* make sure above stores all comlete before going on */
822 sync
824 /* last thing, set local init status done bit (DEVINIT.31) */
825 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
826 oris r4,r4,0x8000 /* make bit 31 = 1 */
827 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
829 /* clear all pending interrupts and disable all interrupts */
830 li r4,-1 /* set p1 to 0xffffffff */
831 stw r4,0x1b0(r3) /* clear all pending interrupts */
832 stw r4,0x1b8(r3) /* clear all pending interrupts */
833 li r4,0 /* set r4 to 0 */
834 stw r4,0x1b4(r3) /* disable all interrupts */
835 stw r4,0x1bc(r3) /* disable all interrupts */
837 /* make sure above stores all comlete before going on */
838 sync
840 /* Set-up icache cacheability. */
841 lis r1, CFG_ICACHE_SACR_VALUE@h
842 ori r1, r1, CFG_ICACHE_SACR_VALUE@l
843 mticcr r1
844 isync
846 /* Set-up dcache cacheability. */
847 lis r1, CFG_DCACHE_SACR_VALUE@h
848 ori r1, r1, CFG_DCACHE_SACR_VALUE@l
849 mtdccr r1
851 addis r1,r0,CFG_INIT_RAM_ADDR@h
852 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
853 li r0, 0 /* Make room for stack frame header and */
854 stwu r0, -4(r1) /* clear final stack frame so that */
855 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
857 GET_GOT /* initialize GOT access */
859 bl board_init_f /* run first part of init code (from Flash) */
861 #endif /* CONFIG_IOP480 */
863 /*****************************************************************************/
864 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
865 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
866 defined(CONFIG_405EX) || defined(CONFIG_405)
867 /*----------------------------------------------------------------------- */
868 /* Clear and set up some registers. */
869 /*----------------------------------------------------------------------- */
870 addi r4,r0,0x0000
871 #if !defined(CONFIG_405EX)
872 mtspr sgr,r4
873 #else
874 /*
875 * On 405EX, completely clearing the SGR leads to PPC hangup
876 * upon PCIe configuration access. The PCIe memory regions
877 * need to be guarded!
878 */
879 lis r3,0x0000
880 ori r3,r3,0x7FFC
881 mtspr sgr,r3
882 #endif
883 mtspr dcwr,r4
884 mtesr r4 /* clear Exception Syndrome Reg */
885 mttcr r4 /* clear Timer Control Reg */
886 mtxer r4 /* clear Fixed-Point Exception Reg */
887 mtevpr r4 /* clear Exception Vector Prefix Reg */
888 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
889 /* dbsr is cleared by setting bits to 1) */
890 mtdbsr r4 /* clear/reset the dbsr */
892 /* Invalidate the i- and d-caches. */
893 bl invalidate_icache
894 bl invalidate_dcache
896 /* Set-up icache cacheability. */
897 lis r4, CFG_ICACHE_SACR_VALUE@h
898 ori r4, r4, CFG_ICACHE_SACR_VALUE@l
899 mticcr r4
900 isync
902 /* Set-up dcache cacheability. */
903 lis r4, CFG_DCACHE_SACR_VALUE@h
904 ori r4, r4, CFG_DCACHE_SACR_VALUE@l
905 mtdccr r4
907 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
908 /*----------------------------------------------------------------------- */
909 /* Tune the speed and size for flash CS0 */
910 /*----------------------------------------------------------------------- */
911 bl ext_bus_cntlr_init
912 #endif
914 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
915 /*
916 * For boards that don't have OCM and can't use the data cache
917 * for their primordial stack, setup stack here directly after the
918 * SDRAM is initialized in ext_bus_cntlr_init.
919 */
920 lis r1, CFG_INIT_RAM_ADDR@h
921 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
923 li r0, 0 /* Make room for stack frame header and */
924 stwu r0, -4(r1) /* clear final stack frame so that */
925 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
926 /*
927 * Set up a dummy frame to store reset vector as return address.
928 * this causes stack underflow to reset board.
929 */
930 stwu r1, -8(r1) /* Save back chain and move SP */
931 lis r0, RESET_VECTOR@h /* Address of reset vector */
932 ori r0, r0, RESET_VECTOR@l
933 stwu r1, -8(r1) /* Save back chain and move SP */
934 stw r0, +12(r1) /* Save return addr (underflow vect) */
935 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
937 #if defined(CONFIG_405EP)
938 /*----------------------------------------------------------------------- */
939 /* DMA Status, clear to come up clean */
940 /*----------------------------------------------------------------------- */
941 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
942 ori r3,r3, 0xFFFF
943 mtdcr dmasr, r3
945 bl ppc405ep_init /* do ppc405ep specific init */
946 #endif /* CONFIG_405EP */
948 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
949 #if defined(CONFIG_405EZ)
950 /********************************************************************
951 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
952 *******************************************************************/
953 /*
954 * We can map the OCM on the PLB3, so map it at
955 * CFG_OCM_DATA_ADDR + 0x8000
956 */
957 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
958 ori r3,r3,CFG_OCM_DATA_ADDR@l
959 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
960 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
961 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
962 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
963 isync
965 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
966 ori r3,r3,CFG_OCM_DATA_ADDR@l
967 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
968 mtdcr ocmdscr1, r3 /* Set Data Side */
969 mtdcr ocmiscr1, r3 /* Set Instruction Side */
970 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
971 mtdcr ocmdscr2, r3 /* Set Data Side */
972 mtdcr ocmiscr2, r3 /* Set Instruction Side */
973 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
974 mtdcr ocmdsisdpc,r3
976 isync
977 #else /* CONFIG_405EZ */
978 /********************************************************************
979 * Setup OCM - On Chip Memory
980 *******************************************************************/
981 /* Setup OCM */
982 lis r0, 0x7FFF
983 ori r0, r0, 0xFFFF
984 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
985 mfdcr r4, ocmdscntl /* get data-side IRAM config */
986 and r3, r3, r0 /* disable data-side IRAM */
987 and r4, r4, r0 /* disable data-side IRAM */
988 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
989 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
990 isync
992 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
993 ori r3,r3,CFG_OCM_DATA_ADDR@l
994 mtdcr ocmdsarc, r3
995 addis r4, 0, 0xC000 /* OCM data area enabled */
996 mtdcr ocmdscntl, r4
997 isync
998 #endif /* CONFIG_405EZ */
999 #endif
1001 /*----------------------------------------------------------------------- */
1002 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1003 /*----------------------------------------------------------------------- */
1004 #ifdef CFG_INIT_DCACHE_CS
1005 li r4, PBxAP
1006 mtdcr ebccfga, r4
1007 lis r4, CFG_INIT_DCACHE_PBxAR@h
1008 ori r4, r4, CFG_INIT_DCACHE_PBxAR@l
1009 mtdcr ebccfgd, r4
1011 addi r4, 0, PBxCR
1012 mtdcr ebccfga, r4
1013 lis r4, CFG_INIT_DCACHE_PBxCR@h
1014 ori r4, r4, CFG_INIT_DCACHE_PBxCR@l
1015 mtdcr ebccfgd, r4
1017 /*
1018 * Enable the data cache for the 128MB storage access control region
1019 * at CFG_INIT_RAM_ADDR.
1020 */
1021 mfdccr r4
1022 oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
1023 ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
1024 mtdccr r4
1026 /*
1027 * Preallocate data cache lines to be used to avoid a subsequent
1028 * cache miss and an ensuing machine check exception when exceptions
1029 * are enabled.
1030 */
1031 li r0, 0
1033 lis r3, CFG_INIT_RAM_ADDR@h
1034 ori r3, r3, CFG_INIT_RAM_ADDR@l
1036 lis r4, CFG_INIT_RAM_END@h
1037 ori r4, r4, CFG_INIT_RAM_END@l
1039 /*
1040 * Convert the size, in bytes, to the number of cache lines/blocks
1041 * to preallocate.
1042 */
1043 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1044 srwi r5, r4, L1_CACHE_SHIFT
1045 beq ..load_counter
1046 addi r5, r5, 0x0001
1047 ..load_counter:
1048 mtctr r5
1050 /* Preallocate the computed number of cache blocks. */
1051 ..alloc_dcache_block:
1052 dcba r0, r3
1053 addi r3, r3, L1_CACHE_BYTES
1054 bdnz ..alloc_dcache_block
1055 sync
1057 /*
1058 * Load the initial stack pointer and data area and convert the size,
1059 * in bytes, to the number of words to initialize to a known value.
1060 */
1061 lis r1, CFG_INIT_RAM_ADDR@h
1062 ori r1, r1, CFG_INIT_SP_OFFSET@l
1064 lis r4, (CFG_INIT_RAM_END >> 2)@h
1065 ori r4, r4, (CFG_INIT_RAM_END >> 2)@l
1066 mtctr r4
1068 lis r2, CFG_INIT_RAM_ADDR@h
1069 ori r2, r2, CFG_INIT_RAM_END@l
1071 lis r4, CFG_INIT_RAM_PATTERN@h
1072 ori r4, r4, CFG_INIT_RAM_PATTERN@l
1074 ..stackloop:
1075 stwu r4, -4(r2)
1076 bdnz ..stackloop
1078 /*
1079 * Make room for stack frame header and clear final stack frame so
1080 * that stack backtraces terminate cleanly.
1081 */
1082 stwu r0, -4(r1)
1083 stwu r0, -4(r1)
1085 /*
1086 * Set up a dummy frame to store reset vector as return address.
1087 * this causes stack underflow to reset board.
1088 */
1089 stwu r1, -8(r1) /* Save back chain and move SP */
1090 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1091 ori r0, r0, RESET_VECTOR@l
1092 stwu r1, -8(r1) /* Save back chain and move SP */
1093 stw r0, +12(r1) /* Save return addr (underflow vect) */
1095 #elif defined(CFG_TEMP_STACK_OCM) && \
1096 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1097 /*
1098 * Stack in OCM.
1099 */
1101 /* Set up Stack at top of OCM */
1102 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1103 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1105 /* Set up a zeroized stack frame so that backtrace works right */
1106 li r0, 0
1107 stwu r0, -4(r1)
1108 stwu r0, -4(r1)
1110 /*
1111 * Set up a dummy frame to store reset vector as return address.
1112 * this causes stack underflow to reset board.
1113 */
1114 stwu r1, -8(r1) /* Save back chain and move SP */
1115 lis r0, RESET_VECTOR@h /* Address of reset vector */
1116 ori r0, r0, RESET_VECTOR@l
1117 stwu r1, -8(r1) /* Save back chain and move SP */
1118 stw r0, +12(r1) /* Save return addr (underflow vect) */
1119 #endif /* CFG_INIT_DCACHE_CS */
1121 #ifdef CONFIG_NAND_SPL
1122 bl nand_boot_common /* will not return */
1123 #else
1124 GET_GOT /* initialize GOT access */
1126 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1128 /* NEVER RETURNS! */
1129 bl board_init_f /* run first part of init code (from Flash) */
1130 #endif /* CONFIG_NAND_SPL */
1132 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1133 /*----------------------------------------------------------------------- */
1136 #ifndef CONFIG_NAND_SPL
1137 /*
1138 * This code finishes saving the registers to the exception frame
1139 * and jumps to the appropriate handler for the exception.
1140 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1141 */
1142 .globl transfer_to_handler
1143 transfer_to_handler:
1144 stw r22,_NIP(r21)
1145 lis r22,MSR_POW@h
1146 andc r23,r23,r22
1147 stw r23,_MSR(r21)
1148 SAVE_GPR(7, r21)
1149 SAVE_4GPRS(8, r21)
1150 SAVE_8GPRS(12, r21)
1151 SAVE_8GPRS(24, r21)
1152 mflr r23
1153 andi. r24,r23,0x3f00 /* get vector offset */
1154 stw r24,TRAP(r21)
1155 li r22,0
1156 stw r22,RESULT(r21)
1157 mtspr SPRG2,r22 /* r1 is now kernel sp */
1158 lwz r24,0(r23) /* virtual address of handler */
1159 lwz r23,4(r23) /* where to go when done */
1160 mtspr SRR0,r24
1161 mtspr SRR1,r20
1162 mtlr r23
1163 SYNC
1164 rfi /* jump to handler, enable MMU */
1166 int_return:
1167 mfmsr r28 /* Disable interrupts */
1168 li r4,0
1169 ori r4,r4,MSR_EE
1170 andc r28,r28,r4
1171 SYNC /* Some chip revs need this... */
1172 mtmsr r28
1173 SYNC
1174 lwz r2,_CTR(r1)
1175 lwz r0,_LINK(r1)
1176 mtctr r2
1177 mtlr r0
1178 lwz r2,_XER(r1)
1179 lwz r0,_CCR(r1)
1180 mtspr XER,r2
1181 mtcrf 0xFF,r0
1182 REST_10GPRS(3, r1)
1183 REST_10GPRS(13, r1)
1184 REST_8GPRS(23, r1)
1185 REST_GPR(31, r1)
1186 lwz r2,_NIP(r1) /* Restore environment */
1187 lwz r0,_MSR(r1)
1188 mtspr SRR0,r2
1189 mtspr SRR1,r0
1190 lwz r0,GPR0(r1)
1191 lwz r2,GPR2(r1)
1192 lwz r1,GPR1(r1)
1193 SYNC
1194 rfi
1196 crit_return:
1197 mfmsr r28 /* Disable interrupts */
1198 li r4,0
1199 ori r4,r4,MSR_EE
1200 andc r28,r28,r4
1201 SYNC /* Some chip revs need this... */
1202 mtmsr r28
1203 SYNC
1204 lwz r2,_CTR(r1)
1205 lwz r0,_LINK(r1)
1206 mtctr r2
1207 mtlr r0
1208 lwz r2,_XER(r1)
1209 lwz r0,_CCR(r1)
1210 mtspr XER,r2
1211 mtcrf 0xFF,r0
1212 REST_10GPRS(3, r1)
1213 REST_10GPRS(13, r1)
1214 REST_8GPRS(23, r1)
1215 REST_GPR(31, r1)
1216 lwz r2,_NIP(r1) /* Restore environment */
1217 lwz r0,_MSR(r1)
1218 mtspr csrr0,r2
1219 mtspr csrr1,r0
1220 lwz r0,GPR0(r1)
1221 lwz r2,GPR2(r1)
1222 lwz r1,GPR1(r1)
1223 SYNC
1224 rfci
1226 #ifdef CONFIG_440
1227 mck_return:
1228 mfmsr r28 /* Disable interrupts */
1229 li r4,0
1230 ori r4,r4,MSR_EE
1231 andc r28,r28,r4
1232 SYNC /* Some chip revs need this... */
1233 mtmsr r28
1234 SYNC
1235 lwz r2,_CTR(r1)
1236 lwz r0,_LINK(r1)
1237 mtctr r2
1238 mtlr r0
1239 lwz r2,_XER(r1)
1240 lwz r0,_CCR(r1)
1241 mtspr XER,r2
1242 mtcrf 0xFF,r0
1243 REST_10GPRS(3, r1)
1244 REST_10GPRS(13, r1)
1245 REST_8GPRS(23, r1)
1246 REST_GPR(31, r1)
1247 lwz r2,_NIP(r1) /* Restore environment */
1248 lwz r0,_MSR(r1)
1249 mtspr mcsrr0,r2
1250 mtspr mcsrr1,r0
1251 lwz r0,GPR0(r1)
1252 lwz r2,GPR2(r1)
1253 lwz r1,GPR1(r1)
1254 SYNC
1255 rfmci
1256 #endif /* CONFIG_440 */
1259 .globl get_pvr
1260 get_pvr:
1261 mfspr r3, PVR
1262 blr
1264 /*------------------------------------------------------------------------------- */
1265 /* Function: out16 */
1266 /* Description: Output 16 bits */
1267 /*------------------------------------------------------------------------------- */
1268 .globl out16
1269 out16:
1270 sth r4,0x0000(r3)
1271 blr
1273 /*------------------------------------------------------------------------------- */
1274 /* Function: out16r */
1275 /* Description: Byte reverse and output 16 bits */
1276 /*------------------------------------------------------------------------------- */
1277 .globl out16r
1278 out16r:
1279 sthbrx r4,r0,r3
1280 blr
1282 /*------------------------------------------------------------------------------- */
1283 /* Function: out32r */
1284 /* Description: Byte reverse and output 32 bits */
1285 /*------------------------------------------------------------------------------- */
1286 .globl out32r
1287 out32r:
1288 stwbrx r4,r0,r3
1289 blr
1291 /*------------------------------------------------------------------------------- */
1292 /* Function: in16 */
1293 /* Description: Input 16 bits */
1294 /*------------------------------------------------------------------------------- */
1295 .globl in16
1296 in16:
1297 lhz r3,0x0000(r3)
1298 blr
1300 /*------------------------------------------------------------------------------- */
1301 /* Function: in16r */
1302 /* Description: Input 16 bits and byte reverse */
1303 /*------------------------------------------------------------------------------- */
1304 .globl in16r
1305 in16r:
1306 lhbrx r3,r0,r3
1307 blr
1309 /*------------------------------------------------------------------------------- */
1310 /* Function: in32r */
1311 /* Description: Input 32 bits and byte reverse */
1312 /*------------------------------------------------------------------------------- */
1313 .globl in32r
1314 in32r:
1315 lwbrx r3,r0,r3
1316 blr
1318 /*
1319 * void relocate_code (addr_sp, gd, addr_moni)
1320 *
1321 * This "function" does not return, instead it continues in RAM
1322 * after relocating the monitor code.
1323 *
1324 * r3 = Relocated stack pointer
1325 * r4 = Relocated global data pointer
1326 * r5 = Relocated text pointer
1327 */
1328 .globl relocate_code
1329 relocate_code:
1330 #if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS)
1331 /*
1332 * We need to flush the initial global data (gd_t) before the dcache
1333 * will be invalidated.
1334 */
1336 /* Save registers */
1337 mr r9, r3
1338 mr r10, r4
1339 mr r11, r5
1341 /* Flush initial global data range */
1342 mr r3, r4
1343 addi r4, r4, CFG_GBL_DATA_SIZE@l
1344 bl flush_dcache_range
1346 #if defined(CFG_INIT_DCACHE_CS)
1347 /*
1348 * Undo the earlier data cache set-up for the primordial stack and
1349 * data area. First, invalidate the data cache and then disable data
1350 * cacheability for that area. Finally, restore the EBC values, if
1351 * any.
1352 */
1354 /* Invalidate the primordial stack and data area in cache */
1355 lis r3, CFG_INIT_RAM_ADDR@h
1356 ori r3, r3, CFG_INIT_RAM_ADDR@l
1358 lis r4, CFG_INIT_RAM_END@h
1359 ori r4, r4, CFG_INIT_RAM_END@l
1360 add r4, r4, r3
1362 bl invalidate_dcache_range
1364 /* Disable cacheability for the region */
1365 mfdccr r3
1366 lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
1367 ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
1368 and r3, r3, r4
1369 mtdccr r3
1371 /* Restore the EBC parameters */
1372 li r3, PBxAP
1373 mtdcr ebccfga, r3
1374 lis r3, PBxAP_VAL@h
1375 ori r3, r3, PBxAP_VAL@l
1376 mtdcr ebccfgd, r3
1378 li r3, PBxCR
1379 mtdcr ebccfga, r3
1380 lis r3, PBxCR_VAL@h
1381 ori r3, r3, PBxCR_VAL@l
1382 mtdcr ebccfgd, r3
1383 #endif /* defined(CFG_INIT_DCACHE_CS) */
1385 /* Restore registers */
1386 mr r3, r9
1387 mr r4, r10
1388 mr r5, r11
1389 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */
1391 #ifdef CFG_INIT_RAM_DCACHE
1392 /*
1393 * Unlock the previously locked d-cache
1394 */
1395 msync
1396 isync
1397 /* set TFLOOR/NFLOOR to 0 again */
1398 lis r6,0x0001
1399 ori r6,r6,0xf800
1400 mtspr dvlim,r6
1401 lis r6,0x0000
1402 ori r6,r6,0x0000
1403 mtspr dnv0,r6
1404 mtspr dnv1,r6
1405 mtspr dnv2,r6
1406 mtspr dnv3,r6
1407 mtspr dtv0,r6
1408 mtspr dtv1,r6
1409 mtspr dtv2,r6
1410 mtspr dtv3,r6
1411 msync
1412 isync
1413 #endif /* CFG_INIT_RAM_DCACHE */
1415 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1416 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1417 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1418 defined(CONFIG_460EX) || defined(CONFIG_460GT)
1419 /*
1420 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1421 * to speed up the boot process. Now this cache needs to be disabled.
1422 */
1423 iccci 0,0 /* Invalidate inst cache */
1424 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1425 sync
1426 isync
1427 #ifdef CFG_TLB_FOR_BOOT_FLASH
1428 addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1429 #else
1430 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1431 #endif /* CFG_TLB_FOR_BOOT_FLASH */
1432 tlbre r0,r1,0x0002 /* Read contents */
1433 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1434 tlbwe r0,r1,0x0002 /* Save it out */
1435 sync
1436 isync
1437 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1438 mr r1, r3 /* Set new stack pointer */
1439 mr r9, r4 /* Save copy of Init Data pointer */
1440 mr r10, r5 /* Save copy of Destination Address */
1442 mr r3, r5 /* Destination Address */
1443 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1444 ori r4, r4, CFG_MONITOR_BASE@l
1445 lwz r5, GOT(__init_end)
1446 sub r5, r5, r4
1447 li r6, L1_CACHE_BYTES /* Cache Line Size */
1449 /*
1450 * Fix GOT pointer:
1451 *
1452 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1453 *
1454 * Offset:
1455 */
1456 sub r15, r10, r4
1458 /* First our own GOT */
1459 add r14, r14, r15
1460 /* then the one used by the C code */
1461 add r30, r30, r15
1463 /*
1464 * Now relocate code
1465 */
1467 cmplw cr1,r3,r4
1468 addi r0,r5,3
1469 srwi. r0,r0,2
1470 beq cr1,4f /* In place copy is not necessary */
1471 beq 7f /* Protect against 0 count */
1472 mtctr r0
1473 bge cr1,2f
1475 la r8,-4(r4)
1476 la r7,-4(r3)
1477 1: lwzu r0,4(r8)
1478 stwu r0,4(r7)
1479 bdnz 1b
1480 b 4f
1482 2: slwi r0,r0,2
1483 add r8,r4,r0
1484 add r7,r3,r0
1485 3: lwzu r0,-4(r8)
1486 stwu r0,-4(r7)
1487 bdnz 3b
1489 /*
1490 * Now flush the cache: note that we must start from a cache aligned
1491 * address. Otherwise we might miss one cache line.
1492 */
1493 4: cmpwi r6,0
1494 add r5,r3,r5
1495 beq 7f /* Always flush prefetch queue in any case */
1496 subi r0,r6,1
1497 andc r3,r3,r0
1498 mr r4,r3
1499 5: dcbst 0,r4
1500 add r4,r4,r6
1501 cmplw r4,r5
1502 blt 5b
1503 sync /* Wait for all dcbst to complete on bus */
1504 mr r4,r3
1505 6: icbi 0,r4
1506 add r4,r4,r6
1507 cmplw r4,r5
1508 blt 6b
1509 7: sync /* Wait for all icbi to complete on bus */
1510 isync
1512 /*
1513 * We are done. Do not return, instead branch to second part of board
1514 * initialization, now running from RAM.
1515 */
1517 addi r0, r10, in_ram - _start + _START_OFFSET
1518 mtlr r0
1519 blr /* NEVER RETURNS! */
1521 in_ram:
1523 /*
1524 * Relocation Function, r14 point to got2+0x8000
1525 *
1526 * Adjust got2 pointers, no need to check for 0, this code
1527 * already puts a few entries in the table.
1528 */
1529 li r0,__got2_entries@sectoff@l
1530 la r3,GOT(_GOT2_TABLE_)
1531 lwz r11,GOT(_GOT2_TABLE_)
1532 mtctr r0
1533 sub r11,r3,r11
1534 addi r3,r3,-4
1535 1: lwzu r0,4(r3)
1536 add r0,r0,r11
1537 stw r0,0(r3)
1538 bdnz 1b
1540 /*
1541 * Now adjust the fixups and the pointers to the fixups
1542 * in case we need to move ourselves again.
1543 */
1544 2: li r0,__fixup_entries@sectoff@l
1545 lwz r3,GOT(_FIXUP_TABLE_)
1546 cmpwi r0,0
1547 mtctr r0
1548 addi r3,r3,-4
1549 beq 4f
1550 3: lwzu r4,4(r3)
1551 lwzux r0,r4,r11
1552 add r0,r0,r11
1553 stw r10,0(r3)
1554 stw r0,0(r4)
1555 bdnz 3b
1556 4:
1557 clear_bss:
1558 /*
1559 * Now clear BSS segment
1560 */
1561 lwz r3,GOT(__bss_start)
1562 lwz r4,GOT(_end)
1564 cmplw 0, r3, r4
1565 beq 7f
1567 li r0, 0
1569 andi. r5, r4, 3
1570 beq 6f
1571 sub r4, r4, r5
1572 mtctr r5
1573 mr r5, r4
1574 5: stb r0, 0(r5)
1575 addi r5, r5, 1
1576 bdnz 5b
1577 6:
1578 stw r0, 0(r3)
1579 addi r3, r3, 4
1580 cmplw 0, r3, r4
1581 bne 6b
1583 7:
1584 mr r3, r9 /* Init Data pointer */
1585 mr r4, r10 /* Destination Address */
1586 bl board_init_r
1588 /*
1589 * Copy exception vector code to low memory
1590 *
1591 * r3: dest_addr
1592 * r7: source address, r8: end address, r9: target address
1593 */
1594 .globl trap_init
1595 trap_init:
1596 lwz r7, GOT(_start_of_vectors)
1597 lwz r8, GOT(_end_of_vectors)
1599 li r9, 0x100 /* reset vector always at 0x100 */
1601 cmplw 0, r7, r8
1602 bgelr /* return if r7>=r8 - just in case */
1604 mflr r4 /* save link register */
1605 1:
1606 lwz r0, 0(r7)
1607 stw r0, 0(r9)
1608 addi r7, r7, 4
1609 addi r9, r9, 4
1610 cmplw 0, r7, r8
1611 bne 1b
1613 /*
1614 * relocate `hdlr' and `int_return' entries
1615 */
1616 li r7, .L_MachineCheck - _start + _START_OFFSET
1617 li r8, Alignment - _start + _START_OFFSET
1618 2:
1619 bl trap_reloc
1620 addi r7, r7, 0x100 /* next exception vector */
1621 cmplw 0, r7, r8
1622 blt 2b
1624 li r7, .L_Alignment - _start + _START_OFFSET
1625 bl trap_reloc
1627 li r7, .L_ProgramCheck - _start + _START_OFFSET
1628 bl trap_reloc
1630 #ifdef CONFIG_440
1631 li r7, .L_FPUnavailable - _start + _START_OFFSET
1632 bl trap_reloc
1634 li r7, .L_Decrementer - _start + _START_OFFSET
1635 bl trap_reloc
1637 li r7, .L_APU - _start + _START_OFFSET
1638 bl trap_reloc
1640 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1641 bl trap_reloc
1643 li r7, .L_DataTLBError - _start + _START_OFFSET
1644 bl trap_reloc
1645 #else /* CONFIG_440 */
1646 li r7, .L_PIT - _start + _START_OFFSET
1647 bl trap_reloc
1649 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1650 bl trap_reloc
1652 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1653 bl trap_reloc
1654 #endif /* CONFIG_440 */
1656 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1657 bl trap_reloc
1659 #if !defined(CONFIG_440)
1660 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1661 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1662 mtmsr r7 /* change MSR */
1663 #else
1664 bl __440_msr_set
1665 b __440_msr_continue
1667 __440_msr_set:
1668 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1669 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1670 mtspr srr1,r7
1671 mflr r7
1672 mtspr srr0,r7
1673 rfi
1674 __440_msr_continue:
1675 #endif
1677 mtlr r4 /* restore link register */
1678 blr
1680 /*
1681 * Function: relocate entries for one exception vector
1682 */
1683 trap_reloc:
1684 lwz r0, 0(r7) /* hdlr ... */
1685 add r0, r0, r3 /* ... += dest_addr */
1686 stw r0, 0(r7)
1688 lwz r0, 4(r7) /* int_return ... */
1689 add r0, r0, r3 /* ... += dest_addr */
1690 stw r0, 4(r7)
1692 blr
1694 #if defined(CONFIG_440)
1695 /*----------------------------------------------------------------------------+
1696 | dcbz_area.
1697 +----------------------------------------------------------------------------*/
1698 function_prolog(dcbz_area)
1699 rlwinm. r5,r4,0,27,31
1700 rlwinm r5,r4,27,5,31
1701 beq ..d_ra2
1702 addi r5,r5,0x0001
1703 ..d_ra2:mtctr r5
1704 ..d_ag2:dcbz r0,r3
1705 addi r3,r3,32
1706 bdnz ..d_ag2
1707 sync
1708 blr
1709 function_epilog(dcbz_area)
1710 #endif /* CONFIG_440 */
1711 #endif /* CONFIG_NAND_SPL */
1713 /*------------------------------------------------------------------------------- */
1714 /* Function: in8 */
1715 /* Description: Input 8 bits */
1716 /*------------------------------------------------------------------------------- */
1717 .globl in8
1718 in8:
1719 lbz r3,0x0000(r3)
1720 blr
1722 /*------------------------------------------------------------------------------- */
1723 /* Function: out8 */
1724 /* Description: Output 8 bits */
1725 /*------------------------------------------------------------------------------- */
1726 .globl out8
1727 out8:
1728 stb r4,0x0000(r3)
1729 blr
1731 /*------------------------------------------------------------------------------- */
1732 /* Function: out32 */
1733 /* Description: Output 32 bits */
1734 /*------------------------------------------------------------------------------- */
1735 .globl out32
1736 out32:
1737 stw r4,0x0000(r3)
1738 blr
1740 /*------------------------------------------------------------------------------- */
1741 /* Function: in32 */
1742 /* Description: Input 32 bits */
1743 /*------------------------------------------------------------------------------- */
1744 .globl in32
1745 in32:
1746 lwz 3,0x0000(3)
1747 blr
1749 /**************************************************************************/
1750 /* PPC405EP specific stuff */
1751 /**************************************************************************/
1752 #ifdef CONFIG_405EP
1753 ppc405ep_init:
1755 #ifdef CONFIG_BUBINGA
1756 /*
1757 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1758 * function) to support FPGA and NVRAM accesses below.
1759 */
1761 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1762 ori r3,r3,GPIO0_OSRH@l
1763 lis r4,CFG_GPIO0_OSRH@h
1764 ori r4,r4,CFG_GPIO0_OSRH@l
1765 stw r4,0(r3)
1766 lis r3,GPIO0_OSRL@h
1767 ori r3,r3,GPIO0_OSRL@l
1768 lis r4,CFG_GPIO0_OSRL@h
1769 ori r4,r4,CFG_GPIO0_OSRL@l
1770 stw r4,0(r3)
1772 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1773 ori r3,r3,GPIO0_ISR1H@l
1774 lis r4,CFG_GPIO0_ISR1H@h
1775 ori r4,r4,CFG_GPIO0_ISR1H@l
1776 stw r4,0(r3)
1777 lis r3,GPIO0_ISR1L@h
1778 ori r3,r3,GPIO0_ISR1L@l
1779 lis r4,CFG_GPIO0_ISR1L@h
1780 ori r4,r4,CFG_GPIO0_ISR1L@l
1781 stw r4,0(r3)
1783 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1784 ori r3,r3,GPIO0_TSRH@l
1785 lis r4,CFG_GPIO0_TSRH@h
1786 ori r4,r4,CFG_GPIO0_TSRH@l
1787 stw r4,0(r3)
1788 lis r3,GPIO0_TSRL@h
1789 ori r3,r3,GPIO0_TSRL@l
1790 lis r4,CFG_GPIO0_TSRL@h
1791 ori r4,r4,CFG_GPIO0_TSRL@l
1792 stw r4,0(r3)
1794 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1795 ori r3,r3,GPIO0_TCR@l
1796 lis r4,CFG_GPIO0_TCR@h
1797 ori r4,r4,CFG_GPIO0_TCR@l
1798 stw r4,0(r3)
1800 li r3,pb1ap /* program EBC bank 1 for RTC access */
1801 mtdcr ebccfga,r3
1802 lis r3,CFG_EBC_PB1AP@h
1803 ori r3,r3,CFG_EBC_PB1AP@l
1804 mtdcr ebccfgd,r3
1805 li r3,pb1cr
1806 mtdcr ebccfga,r3
1807 lis r3,CFG_EBC_PB1CR@h
1808 ori r3,r3,CFG_EBC_PB1CR@l
1809 mtdcr ebccfgd,r3
1811 li r3,pb1ap /* program EBC bank 1 for RTC access */
1812 mtdcr ebccfga,r3
1813 lis r3,CFG_EBC_PB1AP@h
1814 ori r3,r3,CFG_EBC_PB1AP@l
1815 mtdcr ebccfgd,r3
1816 li r3,pb1cr
1817 mtdcr ebccfga,r3
1818 lis r3,CFG_EBC_PB1CR@h
1819 ori r3,r3,CFG_EBC_PB1CR@l
1820 mtdcr ebccfgd,r3
1822 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1823 mtdcr ebccfga,r3
1824 lis r3,CFG_EBC_PB4AP@h
1825 ori r3,r3,CFG_EBC_PB4AP@l
1826 mtdcr ebccfgd,r3
1827 li r3,pb4cr
1828 mtdcr ebccfga,r3
1829 lis r3,CFG_EBC_PB4CR@h
1830 ori r3,r3,CFG_EBC_PB4CR@l
1831 mtdcr ebccfgd,r3
1832 #endif
1834 /*
1835 !-----------------------------------------------------------------------
1836 ! Check to see if chip is in bypass mode.
1837 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1838 ! CPU reset Otherwise, skip this step and keep going.
1839 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1840 ! will not be fast enough for the SDRAM (min 66MHz)
1841 !-----------------------------------------------------------------------
1842 */
1843 mfdcr r5, CPC0_PLLMR1
1844 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1845 cmpi cr0,0,r4,0x1
1847 beq pll_done /* if SSCS =b'1' then PLL has */
1848 /* already been set */
1849 /* and CPU has been reset */
1850 /* so skip to next section */
1852 #ifdef CONFIG_BUBINGA
1853 /*
1854 !-----------------------------------------------------------------------
1855 ! Read NVRAM to get value to write in PLLMR.
1856 ! If value has not been correctly saved, write default value
1857 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1858 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1859 !
1860 ! WARNING: This code assumes the first three words in the nvram_t
1861 ! structure in openbios.h. Changing the beginning of
1862 ! the structure will break this code.
1863 !
1864 !-----------------------------------------------------------------------
1865 */
1866 addis r3,0,NVRAM_BASE@h
1867 addi r3,r3,NVRAM_BASE@l
1869 lwz r4, 0(r3)
1870 addis r5,0,NVRVFY1@h
1871 addi r5,r5,NVRVFY1@l
1872 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1873 bne ..no_pllset
1874 addi r3,r3,4
1875 lwz r4, 0(r3)
1876 addis r5,0,NVRVFY2@h
1877 addi r5,r5,NVRVFY2@l
1878 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1879 bne ..no_pllset
1880 addi r3,r3,8 /* Skip over conf_size */
1881 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1882 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1883 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1884 cmpi cr0,0,r5,1 /* See if PLL is locked */
1885 beq pll_write
1886 ..no_pllset:
1887 #endif /* CONFIG_BUBINGA */
1889 #ifdef CONFIG_TAIHU
1890 mfdcr r4, CPC0_BOOT
1891 andi. r5, r4, CPC0_BOOT_SEP@l
1892 bne strap_1 /* serial eeprom present */
1893 addis r5,0,CPLD_REG0_ADDR@h
1894 ori r5,r5,CPLD_REG0_ADDR@l
1895 andi. r5, r5, 0x10
1896 bne _pci_66mhz
1897 #endif /* CONFIG_TAIHU */
1899 #if defined(CONFIG_ZEUS)
1900 mfdcr r4, CPC0_BOOT
1901 andi. r5, r4, CPC0_BOOT_SEP@l
1902 bne strap_1 /* serial eeprom present */
1903 lis r3,0x0000
1904 addi r3,r3,0x3030
1905 lis r4,0x8042
1906 addi r4,r4,0x223e
1907 b 1f
1908 strap_1:
1909 mfdcr r3, CPC0_PLLMR0
1910 mfdcr r4, CPC0_PLLMR1
1911 b 1f
1912 #endif
1914 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1915 ori r3,r3,PLLMR0_DEFAULT@l /* */
1916 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1917 ori r4,r4,PLLMR1_DEFAULT@l /* */
1919 #ifdef CONFIG_TAIHU
1920 b 1f
1921 _pci_66mhz:
1922 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1923 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1924 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1925 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1926 b 1f
1927 strap_1:
1928 mfdcr r3, CPC0_PLLMR0
1929 mfdcr r4, CPC0_PLLMR1
1930 #endif /* CONFIG_TAIHU */
1932 1:
1933 b pll_write /* Write the CPC0_PLLMR with new value */
1935 pll_done:
1936 /*
1937 !-----------------------------------------------------------------------
1938 ! Clear Soft Reset Register
1939 ! This is needed to enable PCI if not booting from serial EPROM
1940 !-----------------------------------------------------------------------
1941 */
1942 addi r3, 0, 0x0
1943 mtdcr CPC0_SRR, r3
1945 addis r3,0,0x0010
1946 mtctr r3
1947 pci_wait:
1948 bdnz pci_wait
1950 blr /* return to main code */
1952 /*
1953 !-----------------------------------------------------------------------------
1954 ! Function: pll_write
1955 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1956 ! That is:
1957 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1958 ! 2. PLL is reset
1959 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1960 ! 4. PLL Reset is cleared
1961 ! 5. Wait 100us for PLL to lock
1962 ! 6. A core reset is performed
1963 ! Input: r3 = Value to write to CPC0_PLLMR0
1964 ! Input: r4 = Value to write to CPC0_PLLMR1
1965 ! Output r3 = none
1966 !-----------------------------------------------------------------------------
1967 */
1968 pll_write:
1969 mfdcr r5, CPC0_UCR
1970 andis. r5,r5,0xFFFF
1971 ori r5,r5,0x0101 /* Stop the UART clocks */
1972 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1974 mfdcr r5, CPC0_PLLMR1
1975 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1976 mtdcr CPC0_PLLMR1,r5
1977 oris r5,r5,0x4000 /* Set PLL Reset */
1978 mtdcr CPC0_PLLMR1,r5
1980 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1981 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1982 oris r5,r5,0x4000 /* Set PLL Reset */
1983 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1984 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1985 mtdcr CPC0_PLLMR1,r5
1987 /*
1988 ! Wait min of 100us for PLL to lock.
1989 ! See CMOS 27E databook for more info.
1990 ! At 200MHz, that means waiting 20,000 instructions
1991 */
1992 addi r3,0,20000 /* 2000 = 0x4e20 */
1993 mtctr r3
1994 pll_wait:
1995 bdnz pll_wait
1997 oris r5,r5,0x8000 /* Enable PLL */
1998 mtdcr CPC0_PLLMR1,r5 /* Engage */
2000 /*
2001 * Reset CPU to guarantee timings are OK
2002 * Not sure if this is needed...
2003 */
2004 addis r3,0,0x1000
2005 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2006 /* execution will continue from the poweron */
2007 /* vector of 0xfffffffc */
2008 #endif /* CONFIG_405EP */
2010 #if defined(CONFIG_440)
2011 /*----------------------------------------------------------------------------+
2012 | mttlb3.
2013 +----------------------------------------------------------------------------*/
2014 function_prolog(mttlb3)
2015 TLBWE(4,3,2)
2016 blr
2017 function_epilog(mttlb3)
2019 /*----------------------------------------------------------------------------+
2020 | mftlb3.
2021 +----------------------------------------------------------------------------*/
2022 function_prolog(mftlb3)
2023 TLBRE(3,3,2)
2024 blr
2025 function_epilog(mftlb3)
2027 /*----------------------------------------------------------------------------+
2028 | mttlb2.
2029 +----------------------------------------------------------------------------*/
2030 function_prolog(mttlb2)
2031 TLBWE(4,3,1)
2032 blr
2033 function_epilog(mttlb2)
2035 /*----------------------------------------------------------------------------+
2036 | mftlb2.
2037 +----------------------------------------------------------------------------*/
2038 function_prolog(mftlb2)
2039 TLBRE(3,3,1)
2040 blr
2041 function_epilog(mftlb2)
2043 /*----------------------------------------------------------------------------+
2044 | mttlb1.
2045 +----------------------------------------------------------------------------*/
2046 function_prolog(mttlb1)
2047 TLBWE(4,3,0)
2048 blr
2049 function_epilog(mttlb1)
2051 /*----------------------------------------------------------------------------+
2052 | mftlb1.
2053 +----------------------------------------------------------------------------*/
2054 function_prolog(mftlb1)
2055 TLBRE(3,3,0)
2056 blr
2057 function_epilog(mftlb1)
2058 #endif /* CONFIG_440 */
2060 #if defined(CONFIG_NAND_SPL)
2061 /*
2062 * void nand_boot_relocate(dst, src, bytes)
2063 *
2064 * r3 = Destination address to copy code to (in SDRAM)
2065 * r4 = Source address to copy code from
2066 * r5 = size to copy in bytes
2067 */
2068 nand_boot_relocate:
2069 mr r6,r3
2070 mr r7,r4
2071 mflr r8
2073 /*
2074 * Copy SPL from icache into SDRAM
2075 */
2076 subi r3,r3,4
2077 subi r4,r4,4
2078 srwi r5,r5,2
2079 mtctr r5
2080 ..spl_loop:
2081 lwzu r0,4(r4)
2082 stwu r0,4(r3)
2083 bdnz ..spl_loop
2085 /*
2086 * Calculate "corrected" link register, so that we "continue"
2087 * in execution in destination range
2088 */
2089 sub r3,r7,r6 /* r3 = src - dst */
2090 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2091 mtlr r8
2092 blr
2094 nand_boot_common:
2095 /*
2096 * First initialize SDRAM. It has to be available *before* calling
2097 * nand_boot().
2098 */
2099 lis r3,CFG_SDRAM_BASE@h
2100 ori r3,r3,CFG_SDRAM_BASE@l
2101 bl initdram
2103 /*
2104 * Now copy the 4k SPL code into SDRAM and continue execution
2105 * from there.
2106 */
2107 lis r3,CFG_NAND_BOOT_SPL_DST@h
2108 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
2109 lis r4,CFG_NAND_BOOT_SPL_SRC@h
2110 ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l
2111 lis r5,CFG_NAND_BOOT_SPL_SIZE@h
2112 ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l
2113 bl nand_boot_relocate
2115 /*
2116 * We're running from SDRAM now!!!
2117 *
2118 * It is necessary for 4xx systems to relocate from running at
2119 * the original location (0xfffffxxx) to somewhere else (SDRAM
2120 * preferably). This is because CS0 needs to be reconfigured for
2121 * NAND access. And we can't reconfigure this CS when currently
2122 * "running" from it.
2123 */
2125 /*
2126 * Finally call nand_boot() to load main NAND U-Boot image from
2127 * NAND and jump to it.
2128 */
2129 bl nand_boot /* will not return */
2130 #endif /* CONFIG_NAND_SPL */