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Change boot command to boot kernel from 0xc1028380
[u-boot-m93030.git] / drivers / usb / usbdcore_omap1510.c
blob84bb936d86923edd3275fd3891172f3991db0603
1 /*
2 * (C) Copyright 2003
3 * Gerry Hamel, geh@ti.com, Texas Instruments
4 *
5 * Based on
6 * linux/drivers/usb/device/bi/omap.c
7 * TI OMAP1510 USB bus interface driver
8 *
9 * Author: MontaVista Software, Inc.
10 * source@mvista.com
11 * (C) Copyright 2002
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29 #include <common.h>
30
31 #if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE)
32
33 #include <asm/io.h>
34 #ifdef CONFIG_OMAP_SX1
35 #include <i2c.h>
36 #endif
37
38 #include "usbdcore.h"
39 #include "usbdcore_omap1510.h"
40 #include "usbdcore_ep0.h"
41
42
43 #define UDC_INIT_MDELAY 80 /* Device settle delay */
44 #define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */
45
46 /* Some kind of debugging output... */
47 #if 1
48 #define UDCDBG(str)
49 #define UDCDBGA(fmt,args...)
50 #else /* The bugs still exists... */
51 #define UDCDBG(str) serial_printf("[%s] %s:%d: " str "\n", __FILE__,__FUNCTION__,__LINE__)
52 #define UDCDBGA(fmt,args...) serial_printf("[%s] %s:%d: " fmt "\n", __FILE__,__FUNCTION__,__LINE__, ##args)
53 #endif
54
55 #if 1
56 #define UDCREG(name)
57 #define UDCREGL(name)
58 #else /* The bugs still exists... */
59 #define UDCREG(name) serial_printf("%s():%d: %s[%08x]=%.4x\n",__FUNCTION__,__LINE__, (#name), name, inw(name)) /* For 16-bit regs */
60 #define UDCREGL(name) serial_printf("%s():%d: %s[%08x]=%.8x\n",__FUNCTION__,__LINE__, (#name), name, inl(name)) /* For 32-bit regs */
61 #endif
62
63
64 static struct urb *ep0_urb = NULL;
65
66 static struct usb_device_instance *udc_device; /* Used in interrupt handler */
67 static u16 udc_devstat = 0; /* UDC status (DEVSTAT) */
68 static u32 udc_interrupts = 0;
69
70 static void udc_stall_ep (unsigned int ep_addr);
71
72
73 static struct usb_endpoint_instance *omap1510_find_ep (int ep)
74 {
75 int i;
76
77 for (i = 0; i < udc_device->bus->max_endpoints; i++) {
78 if (udc_device->bus->endpoint_array[i].endpoint_address == ep)
79 return &udc_device->bus->endpoint_array[i];
80 }
81 return NULL;
82 }
83
84 /* ************************************************************************** */
85 /* IO
86 */
87
88 /*
89 * omap1510_prepare_endpoint_for_rx
90 *
91 * This function implements TRM Figure 14-11.
92 *
93 * The endpoint to prepare for transfer is specified as a physical endpoint
94 * number. For OUT (rx) endpoints 1 through 15, the corresponding endpoint
95 * configuration register is checked to see if the endpoint is ISO or not.
96 * If the OUT endpoint is valid and is non-ISO then its FIFO is enabled.
97 * No action is taken for endpoint 0 or for IN (tx) endpoints 16 through 30.
98 */
99 static void omap1510_prepare_endpoint_for_rx (int ep_addr)
100 {
101 int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
102
103 UDCDBGA ("omap1510_prepare_endpoint %x", ep_addr);
104 if (((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT)) {
105 if ((inw (UDC_EP_RX (ep_num)) &
106 (UDC_EPn_RX_Valid | UDC_EPn_RX_Iso)) ==
107 UDC_EPn_RX_Valid) {
108 /* rx endpoint is valid, non-ISO, so enable its FIFO */
109 outw (UDC_EP_Sel | ep_num, UDC_EP_NUM);
110 outw (UDC_Set_FIFO_En, UDC_CTRL);
111 outw (0, UDC_EP_NUM);
112 }
113 }
114 }
115
116 /* omap1510_configure_endpoints
117 *
118 * This function implements TRM Figure 14-10.
119 */
120 static void omap1510_configure_endpoints (struct usb_device_instance *device)
121 {
122 int ep;
123 struct usb_bus_instance *bus;
124 struct usb_endpoint_instance *endpoint;
125 unsigned short ep_ptr;
126 unsigned short ep_size;
127 unsigned short ep_isoc;
128 unsigned short ep_doublebuffer;
129 int ep_addr;
130 int packet_size;
131 int buffer_size;
132 int attributes;
133
134 bus = device->bus;
135
136 /* There is a dedicated 2048 byte buffer for USB packets that may be
137 * arbitrarily partitioned among the endpoints on 8-byte boundaries.
138 * The first 8 bytes are reserved for receiving setup packets on
139 * endpoint 0.
140 */
141 ep_ptr = 8; /* reserve the first 8 bytes for the setup fifo */
142
143 for (ep = 0; ep < bus->max_endpoints; ep++) {
144 endpoint = bus->endpoint_array + ep;
145 ep_addr = endpoint->endpoint_address;
146 if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
147 /* IN endpoint */
148 packet_size = endpoint->tx_packetSize;
149 attributes = endpoint->tx_attributes;
150 } else {
151 /* OUT endpoint */
152 packet_size = endpoint->rcv_packetSize;
153 attributes = endpoint->rcv_attributes;
154 }
155
156 switch (packet_size) {
157 case 0:
158 ep_size = 0;
159 break;
160 case 8:
161 ep_size = 0;
162 break;
163 case 16:
164 ep_size = 1;
165 break;
166 case 32:
167 ep_size = 2;
168 break;
169 case 64:
170 ep_size = 3;
171 break;
172 case 128:
173 ep_size = 4;
174 break;
175 case 256:
176 ep_size = 5;
177 break;
178 case 512:
179 ep_size = 6;
180 break;
181 default:
182 UDCDBGA ("ep 0x%02x has bad packet size %d",
183 ep_addr, packet_size);
184 packet_size = 0;
185 ep_size = 0;
186 break;
187 }
188
189 switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
190 case USB_ENDPOINT_XFER_CONTROL:
191 case USB_ENDPOINT_XFER_BULK:
192 case USB_ENDPOINT_XFER_INT:
193 default:
194 /* A non-isochronous endpoint may optionally be
195 * double-buffered. For now we disable
196 * double-buffering.
197 */
198 ep_doublebuffer = 0;
199 ep_isoc = 0;
200 if (packet_size > 64)
201 packet_size = 0;
202 if (!ep || !ep_doublebuffer)
203 buffer_size = packet_size;
204 else
205 buffer_size = packet_size * 2;
206 break;
207 case USB_ENDPOINT_XFER_ISOC:
208 /* Isochronous endpoints are always double-
209 * buffered, but the double-buffering bit
210 * in the endpoint configuration register
211 * becomes the msb of the endpoint size so we
212 * set the double-buffering flag to zero.
213 */
214 ep_doublebuffer = 0;
215 ep_isoc = 1;
216 buffer_size = packet_size * 2;
217 break;
218 }
219
220 /* check to see if our packet buffer RAM is exhausted */
221 if ((ep_ptr + buffer_size) > 2048) {
222 UDCDBGA ("out of packet RAM for ep 0x%02x buf size %d", ep_addr, buffer_size);
223 buffer_size = packet_size = 0;
224 }
225
226 /* force a default configuration for endpoint 0 since it is
227 * always enabled
228 */
229 if (!ep && ((packet_size < 8) || (packet_size > 64))) {
230 buffer_size = packet_size = 64;
231 ep_size = 3;
232 }
233
234 if (!ep) {
235 /* configure endpoint 0 */
236 outw ((ep_size << 12) | (ep_ptr >> 3), UDC_EP0);
237 /*UDCDBGA("ep 0 buffer offset 0x%03x packet size 0x%03x", */
238 /* ep_ptr, packet_size); */
239 } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
240 /* IN endpoint */
241 if (packet_size) {
242 outw ((1 << 15) | (ep_doublebuffer << 14) |
243 (ep_size << 12) | (ep_isoc << 11) |
244 (ep_ptr >> 3),
245 UDC_EP_TX (ep_addr &
246 USB_ENDPOINT_NUMBER_MASK));
247 UDCDBGA ("IN ep %d buffer offset 0x%03x"
248 " packet size 0x%03x",
249 ep_addr & USB_ENDPOINT_NUMBER_MASK,
250 ep_ptr, packet_size);
251 } else {
252 outw (0,
253 UDC_EP_TX (ep_addr &
254 USB_ENDPOINT_NUMBER_MASK));
255 }
256 } else {
257 /* OUT endpoint */
258 if (packet_size) {
259 outw ((1 << 15) | (ep_doublebuffer << 14) |
260 (ep_size << 12) | (ep_isoc << 11) |
261 (ep_ptr >> 3),
262 UDC_EP_RX (ep_addr &
263 USB_ENDPOINT_NUMBER_MASK));
264 UDCDBGA ("OUT ep %d buffer offset 0x%03x"
265 " packet size 0x%03x",
266 ep_addr & USB_ENDPOINT_NUMBER_MASK,
267 ep_ptr, packet_size);
268 } else {
269 outw (0,
270 UDC_EP_RX (ep_addr &
271 USB_ENDPOINT_NUMBER_MASK));
272 }
273 }
274 ep_ptr += buffer_size;
275 }
276 }
277
278 /* omap1510_deconfigure_device
279 *
280 * This function balances omap1510_configure_device.
281 */
282 static void omap1510_deconfigure_device (void)
283 {
284 int epnum;
285
286 UDCDBG ("clear Cfg_Lock");
287 outw (inw (UDC_SYSCON1) & ~UDC_Cfg_Lock, UDC_SYSCON1);
288 UDCREG (UDC_SYSCON1);
289
290 /* deconfigure all endpoints */
291 for (epnum = 1; epnum <= 15; epnum++) {
292 outw (0, UDC_EP_RX (epnum));
293 outw (0, UDC_EP_TX (epnum));
294 }
295 }
296
297 /* omap1510_configure_device
298 *
299 * This function implements TRM Figure 14-9.
300 */
301 static void omap1510_configure_device (struct usb_device_instance *device)
302 {
303 omap1510_configure_endpoints (device);
304
305
306 /* Figure 14-9 indicates we should enable interrupts here, but we have
307 * other routines (udc_all_interrupts, udc_suspended_interrupts) to
308 * do that.
309 */
310
311 UDCDBG ("set Cfg_Lock");
312 outw (inw (UDC_SYSCON1) | UDC_Cfg_Lock, UDC_SYSCON1);
313 UDCREG (UDC_SYSCON1);
314 }
315
316 /* omap1510_write_noniso_tx_fifo
317 *
318 * This function implements TRM Figure 14-30.
319 *
320 * If the endpoint has an active tx_urb, then the next packet of data from the
321 * URB is written to the tx FIFO. The total amount of data in the urb is given
322 * by urb->actual_length. The maximum amount of data that can be sent in any
323 * one packet is given by endpoint->tx_packetSize. The number of data bytes
324 * from this URB that have already been transmitted is given by endpoint->sent.
325 * endpoint->last is updated by this routine with the number of data bytes
326 * transmitted in this packet.
327 *
328 * In accordance with Figure 14-30, the EP_NUM register must already have been
329 * written with the value to select the appropriate tx FIFO before this routine
330 * is called.
331 */
332 static void omap1510_write_noniso_tx_fifo (struct usb_endpoint_instance
333 *endpoint)
334 {
335 struct urb *urb = endpoint->tx_urb;
336
337 if (urb) {
338 unsigned int last, i;
339
340 UDCDBGA ("urb->buffer %p, buffer_length %d, actual_length %d",
341 urb->buffer, urb->buffer_length, urb->actual_length);
342 if ((last =
343 MIN (urb->actual_length - endpoint->sent,
344 endpoint->tx_packetSize))) {
345 u8 *cp = urb->buffer + endpoint->sent;
346
347 UDCDBGA ("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last);
348
349 if (((u32) cp & 1) == 0) { /* word aligned? */
350 outsw (UDC_DATA, cp, last >> 1);
351 } else { /* byte aligned. */
352 for (i = 0; i < (last >> 1); i++) {
353 u16 w = ((u16) cp[2 * i + 1] << 8) |
354 (u16) cp[2 * i];
355 outw (w, UDC_DATA);
356 }
357 }
358 if (last & 1) {
359 outb (*(cp + last - 1), UDC_DATA);
360 }
361 }
362 endpoint->last = last;
363 }
364 }
365
366 /* omap1510_read_noniso_rx_fifo
367 *
368 * This function implements TRM Figure 14-28.
369 *
370 * If the endpoint has an active rcv_urb, then the next packet of data is read
371 * from the rcv FIFO and written to rcv_urb->buffer at offset
372 * rcv_urb->actual_length to append the packet data to the data from any
373 * previous packets for this transfer. We assume that there is sufficient room
374 * left in the buffer to hold an entire packet of data.
375 *
376 * The return value is the number of bytes read from the FIFO for this packet.
377 *
378 * In accordance with Figure 14-28, the EP_NUM register must already have been
379 * written with the value to select the appropriate rcv FIFO before this routine
380 * is called.
381 */
382 static int omap1510_read_noniso_rx_fifo (struct usb_endpoint_instance
383 *endpoint)
384 {
385 struct urb *urb = endpoint->rcv_urb;
386 int len = 0;
387
388 if (urb) {
389 len = inw (UDC_RXFSTAT);
390
391 if (len) {
392 unsigned char *cp = urb->buffer + urb->actual_length;
393
394 insw (UDC_DATA, cp, len >> 1);
395 if (len & 1)
396 *(cp + len - 1) = inb (UDC_DATA);
397 }
398 }
399 return len;
400 }
401
402 /* omap1510_prepare_for_control_write_status
403 *
404 * This function implements TRM Figure 14-17.
405 *
406 * We have to deal here with non-autodecoded control writes that haven't already
407 * been dealt with by ep0_recv_setup. The non-autodecoded standard control
408 * write requests are: set/clear endpoint feature, set configuration, set
409 * interface, and set descriptor. ep0_recv_setup handles set/clear requests for
410 * ENDPOINT_HALT by halting the endpoint for a set request and resetting the
411 * endpoint for a clear request. ep0_recv_setup returns an error for
412 * SET_DESCRIPTOR requests which causes them to be terminated with a stall by
413 * the setup handler. A SET_INTERFACE request is handled by ep0_recv_setup by
414 * generating a DEVICE_SET_INTERFACE event. This leaves only the
415 * SET_CONFIGURATION event for us to deal with here.
416 *
417 */
418 static void omap1510_prepare_for_control_write_status (struct urb *urb)
419 {
420 struct usb_device_request *request = &urb->device_request;;
421
422 /* check for a SET_CONFIGURATION request */
423 if (request->bRequest == USB_REQ_SET_CONFIGURATION) {
424 int configuration = le16_to_cpu (request->wValue) & 0xff;
425 unsigned short devstat = inw (UDC_DEVSTAT);
426
427 if ((devstat & (UDC_ADD | UDC_CFG)) == UDC_ADD) {
428 /* device is currently in ADDRESSED state */
429 if (configuration) {
430 /* Assume the specified non-zero configuration
431 * value is valid and switch to the CONFIGURED
432 * state.
433 */
434 outw (UDC_Dev_Cfg, UDC_SYSCON2);
435 }
436 } else if ((devstat & UDC_CFG) == UDC_CFG) {
437 /* device is currently in CONFIGURED state */
438 if (!configuration) {
439 /* Switch to ADDRESSED state. */
440 outw (UDC_Clr_Cfg, UDC_SYSCON2);
441 }
442 }
443 }
444
445 /* select EP0 tx FIFO */
446 outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM);
447 /* clear endpoint (no data bytes in status stage) */
448 outw (UDC_Clr_EP, UDC_CTRL);
449 /* enable the EP0 tx FIFO */
450 outw (UDC_Set_FIFO_En, UDC_CTRL);
451 /* deselect the endpoint */
452 outw (UDC_EP_Dir, UDC_EP_NUM);
453 }
454
455 /* udc_state_transition_up
456 * udc_state_transition_down
457 *
458 * Helper functions to implement device state changes. The device states and
459 * the events that transition between them are:
460 *
461 * STATE_ATTACHED
462 * || /\
463 * \/ ||
464 * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET
465 * || /\
466 * \/ ||
467 * STATE_POWERED
468 * || /\
469 * \/ ||
470 * DEVICE_RESET DEVICE_POWER_INTERRUPTION
471 * || /\
472 * \/ ||
473 * STATE_DEFAULT
474 * || /\
475 * \/ ||
476 * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET
477 * || /\
478 * \/ ||
479 * STATE_ADDRESSED
480 * || /\
481 * \/ ||
482 * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED
483 * || /\
484 * \/ ||
485 * STATE_CONFIGURED
486 *
487 * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED
488 * to STATE_CONFIGURED) from the specified initial state to the specified final
489 * state, passing through each intermediate state on the way. If the initial
490 * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
491 * no state transitions will take place.
492 *
493 * udc_state_transition_down transitions down (in the direction from
494 * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
495 * specified final state, passing through each intermediate state on the way.
496 * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
497 * state, then no state transitions will take place.
498 *
499 * These functions must only be called with interrupts disabled.
500 */
501 static void udc_state_transition_up (usb_device_state_t initial,
502 usb_device_state_t final)
503 {
504 if (initial < final) {
505 switch (initial) {
506 case STATE_ATTACHED:
507 usbd_device_event_irq (udc_device,
508 DEVICE_HUB_CONFIGURED, 0);
509 if (final == STATE_POWERED)
510 break;
511 case STATE_POWERED:
512 usbd_device_event_irq (udc_device, DEVICE_RESET, 0);
513 if (final == STATE_DEFAULT)
514 break;
515 case STATE_DEFAULT:
516 usbd_device_event_irq (udc_device,
517 DEVICE_ADDRESS_ASSIGNED, 0);
518 if (final == STATE_ADDRESSED)
519 break;
520 case STATE_ADDRESSED:
521 usbd_device_event_irq (udc_device, DEVICE_CONFIGURED,
522 0);
523 case STATE_CONFIGURED:
524 break;
525 default:
526 break;
527 }
528 }
529 }
530
531 static void udc_state_transition_down (usb_device_state_t initial,
532 usb_device_state_t final)
533 {
534 if (initial > final) {
535 switch (initial) {
536 case STATE_CONFIGURED:
537 usbd_device_event_irq (udc_device, DEVICE_DE_CONFIGURED, 0);
538 if (final == STATE_ADDRESSED)
539 break;
540 case STATE_ADDRESSED:
541 usbd_device_event_irq (udc_device, DEVICE_RESET, 0);
542 if (final == STATE_DEFAULT)
543 break;
544 case STATE_DEFAULT:
545 usbd_device_event_irq (udc_device, DEVICE_POWER_INTERRUPTION, 0);
546 if (final == STATE_POWERED)
547 break;
548 case STATE_POWERED:
549 usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, 0);
550 case STATE_ATTACHED:
551 break;
552 default:
553 break;
554 }
555 }
556 }
557
558 /* Handle all device state changes.
559 * This function implements TRM Figure 14-21.
560 */
561 static void omap1510_udc_state_changed (void)
562 {
563 u16 bits;
564 u16 devstat = inw (UDC_DEVSTAT);
565
566 UDCDBGA ("state changed, devstat %x, old %x", devstat, udc_devstat);
567
568 bits = devstat ^ udc_devstat;
569 if (bits) {
570 if (bits & UDC_ATT) {
571 if (devstat & UDC_ATT) {
572 UDCDBG ("device attached and powered");
573 udc_state_transition_up (udc_device->device_state, STATE_POWERED);
574 } else {
575 UDCDBG ("device detached or unpowered");
576 udc_state_transition_down (udc_device->device_state, STATE_ATTACHED);
577 }
578 }
579 if (bits & UDC_USB_Reset) {
580 if (devstat & UDC_USB_Reset) {
581 UDCDBG ("device reset in progess");
582 udc_state_transition_down (udc_device->device_state, STATE_POWERED);
583 } else {
584 UDCDBG ("device reset completed");
585 }
586 }
587 if (bits & UDC_DEF) {
588 if (devstat & UDC_DEF) {
589 UDCDBG ("device entering default state");
590 udc_state_transition_up (udc_device->device_state, STATE_DEFAULT);
591 } else {
592 UDCDBG ("device leaving default state");
593 udc_state_transition_down (udc_device->device_state, STATE_POWERED);
594 }
595 }
596 if (bits & UDC_SUS) {
597 if (devstat & UDC_SUS) {
598 UDCDBG ("entering suspended state");
599 usbd_device_event_irq (udc_device, DEVICE_BUS_INACTIVE, 0);
600 } else {
601 UDCDBG ("leaving suspended state");
602 usbd_device_event_irq (udc_device, DEVICE_BUS_ACTIVITY, 0);
603 }
604 }
605 if (bits & UDC_R_WK_OK) {
606 UDCDBGA ("remote wakeup %s", (devstat & UDC_R_WK_OK)
607 ? "enabled" : "disabled");
608 }
609 if (bits & UDC_ADD) {
610 if (devstat & UDC_ADD) {
611 UDCDBG ("default -> addressed");
612 udc_state_transition_up (udc_device->device_state, STATE_ADDRESSED);
613 } else {
614 UDCDBG ("addressed -> default");
615 udc_state_transition_down (udc_device->device_state, STATE_DEFAULT);
616 }
617 }
618 if (bits & UDC_CFG) {
619 if (devstat & UDC_CFG) {
620 UDCDBG ("device configured");
621 /* The ep0_recv_setup function generates the
622 * DEVICE_CONFIGURED event when a
623 * USB_REQ_SET_CONFIGURATION setup packet is
624 * received, so we should already be in the
625 * state STATE_CONFIGURED.
626 */
627 udc_state_transition_up (udc_device->device_state, STATE_CONFIGURED);
628 } else {
629 UDCDBG ("device deconfigured");
630 udc_state_transition_down (udc_device->device_state, STATE_ADDRESSED);
631 }
632 }
633 }
634
635 /* Clear interrupt source */
636 outw (UDC_DS_Chg, UDC_IRQ_SRC);
637
638 /* Save current DEVSTAT */
639 udc_devstat = devstat;
640 }
641
642 /* Handle SETUP USB interrupt.
643 * This function implements TRM Figure 14-14.
644 */
645 static void omap1510_udc_setup (struct usb_endpoint_instance *endpoint)
646 {
647 UDCDBG ("-> Entering device setup");
648
649 do {
650 const int setup_pktsize = 8;
651 unsigned char *datap =
652 (unsigned char *) &ep0_urb->device_request;
653
654 /* Gain access to EP 0 setup FIFO */
655 outw (UDC_Setup_Sel, UDC_EP_NUM);
656
657 /* Read control request data */
658 insb (UDC_DATA, datap, setup_pktsize);
659
660 UDCDBGA ("EP0 setup read [%x %x %x %x %x %x %x %x]",
661 *(datap + 0), *(datap + 1), *(datap + 2),
662 *(datap + 3), *(datap + 4), *(datap + 5),
663 *(datap + 6), *(datap + 7));
664
665 /* Reset EP0 setup FIFO */
666 outw (0, UDC_EP_NUM);
667 } while (inw (UDC_IRQ_SRC) & UDC_Setup);
668
669 /* Try to process setup packet */
670 if (ep0_recv_setup (ep0_urb)) {
671 /* Not a setup packet, stall next EP0 transaction */
672 udc_stall_ep (0);
673 UDCDBG ("can't parse setup packet, still waiting for setup");
674 return;
675 }
676
677 /* Check direction */
678 if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
679 == USB_REQ_HOST2DEVICE) {
680 UDCDBG ("control write on EP0");
681 if (le16_to_cpu (ep0_urb->device_request.wLength)) {
682 /* We don't support control write data stages.
683 * The only standard control write request with a data
684 * stage is SET_DESCRIPTOR, and ep0_recv_setup doesn't
685 * support that so we just stall those requests. A
686 * function driver might support a non-standard
687 * write request with a data stage, but it isn't
688 * obvious what we would do with the data if we read it
689 * so we'll just stall it. It seems like the API isn't
690 * quite right here.
691 */
692 #if 0
693 /* Here is what we would do if we did support control
694 * write data stages.
695 */
696 ep0_urb->actual_length = 0;
697 outw (0, UDC_EP_NUM);
698 /* enable the EP0 rx FIFO */
699 outw (UDC_Set_FIFO_En, UDC_CTRL);
700 #else
701 /* Stall this request */
702 UDCDBG ("Stalling unsupported EP0 control write data "
703 "stage.");
704 udc_stall_ep (0);
705 #endif
706 } else {
707 omap1510_prepare_for_control_write_status (ep0_urb);
708 }
709 } else {
710 UDCDBG ("control read on EP0");
711 /* The ep0_recv_setup function has already placed our response
712 * packet data in ep0_urb->buffer and the packet length in
713 * ep0_urb->actual_length.
714 */
715 endpoint->tx_urb = ep0_urb;
716 endpoint->sent = 0;
717 /* select the EP0 tx FIFO */
718 outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM);
719 /* Write packet data to the FIFO. omap1510_write_noniso_tx_fifo
720 * will update endpoint->last with the number of bytes written
721 * to the FIFO.
722 */
723 omap1510_write_noniso_tx_fifo (endpoint);
724 /* enable the FIFO to start the packet transmission */
725 outw (UDC_Set_FIFO_En, UDC_CTRL);
726 /* deselect the EP0 tx FIFO */
727 outw (UDC_EP_Dir, UDC_EP_NUM);
728 }
729
730 UDCDBG ("<- Leaving device setup");
731 }
732
733 /* Handle endpoint 0 RX interrupt
734 * This routine implements TRM Figure 14-16.
735 */
736 static void omap1510_udc_ep0_rx (struct usb_endpoint_instance *endpoint)
737 {
738 unsigned short status;
739
740 UDCDBG ("RX on EP0");
741 /* select EP0 rx FIFO */
742 outw (UDC_EP_Sel, UDC_EP_NUM);
743
744 status = inw (UDC_STAT_FLG);
745
746 if (status & UDC_ACK) {
747 /* Check direction */
748 if ((ep0_urb->device_request.bmRequestType
749 & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
750 /* This rx interrupt must be for a control write data
751 * stage packet.
752 *
753 * We don't support control write data stages.
754 * We should never end up here.
755 */
756
757 /* clear the EP0 rx FIFO */
758 outw (UDC_Clr_EP, UDC_CTRL);
759
760 /* deselect the EP0 rx FIFO */
761 outw (0, UDC_EP_NUM);
762
763 UDCDBG ("Stalling unexpected EP0 control write "
764 "data stage packet");
765 udc_stall_ep (0);
766 } else {
767 /* This rx interrupt must be for a control read status
768 * stage packet.
769 */
770 UDCDBG ("ACK on EP0 control read status stage packet");
771 /* deselect EP0 rx FIFO */
772 outw (0, UDC_EP_NUM);
773 }
774 } else if (status & UDC_STALL) {
775 UDCDBG ("EP0 stall during RX");
776 /* deselect EP0 rx FIFO */
777 outw (0, UDC_EP_NUM);
778 } else {
779 /* deselect EP0 rx FIFO */
780 outw (0, UDC_EP_NUM);
781 }
782 }
783
784 /* Handle endpoint 0 TX interrupt
785 * This routine implements TRM Figure 14-18.
786 */
787 static void omap1510_udc_ep0_tx (struct usb_endpoint_instance *endpoint)
788 {
789 unsigned short status;
790 struct usb_device_request *request = &ep0_urb->device_request;
791
792 UDCDBG ("TX on EP0");
793 /* select EP0 TX FIFO */
794 outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM);
795
796 status = inw (UDC_STAT_FLG);
797 if (status & UDC_ACK) {
798 /* Check direction */
799 if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
800 USB_REQ_HOST2DEVICE) {
801 /* This tx interrupt must be for a control write status
802 * stage packet.
803 */
804 UDCDBG ("ACK on EP0 control write status stage packet");
805 /* deselect EP0 TX FIFO */
806 outw (UDC_EP_Dir, UDC_EP_NUM);
807 } else {
808 /* This tx interrupt must be for a control read data
809 * stage packet.
810 */
811 int wLength = le16_to_cpu (request->wLength);
812
813 /* Update our count of bytes sent so far in this
814 * transfer.
815 */
816 endpoint->sent += endpoint->last;
817
818 /* We are finished with this transfer if we have sent
819 * all of the bytes in our tx urb (urb->actual_length)
820 * unless we need a zero-length terminating packet. We
821 * need a zero-length terminating packet if we returned
822 * fewer bytes than were requested (wLength) by the host,
823 * and the number of bytes we returned is an exact
824 * multiple of the packet size endpoint->tx_packetSize.
825 */
826 if ((endpoint->sent == ep0_urb->actual_length)
827 && ((ep0_urb->actual_length == wLength)
828 || (endpoint->last !=
829 endpoint->tx_packetSize))) {
830 /* Done with control read data stage. */
831 UDCDBG ("control read data stage complete");
832 /* deselect EP0 TX FIFO */
833 outw (UDC_EP_Dir, UDC_EP_NUM);
834 /* select EP0 RX FIFO to prepare for control
835 * read status stage.
836 */
837 outw (UDC_EP_Sel, UDC_EP_NUM);
838 /* clear the EP0 RX FIFO */
839 outw (UDC_Clr_EP, UDC_CTRL);
840 /* enable the EP0 RX FIFO */
841 outw (UDC_Set_FIFO_En, UDC_CTRL);
842 /* deselect the EP0 RX FIFO */
843 outw (0, UDC_EP_NUM);
844 } else {
845 /* We still have another packet of data to send
846 * in this control read data stage or else we
847 * need a zero-length terminating packet.
848 */
849 UDCDBG ("ACK control read data stage packet");
850 omap1510_write_noniso_tx_fifo (endpoint);
851 /* enable the EP0 tx FIFO to start transmission */
852 outw (UDC_Set_FIFO_En, UDC_CTRL);
853 /* deselect EP0 TX FIFO */
854 outw (UDC_EP_Dir, UDC_EP_NUM);
855 }
856 }
857 } else if (status & UDC_STALL) {
858 UDCDBG ("EP0 stall during TX");
859 /* deselect EP0 TX FIFO */
860 outw (UDC_EP_Dir, UDC_EP_NUM);
861 } else {
862 /* deselect EP0 TX FIFO */
863 outw (UDC_EP_Dir, UDC_EP_NUM);
864 }
865 }
866
867 /* Handle RX transaction on non-ISO endpoint.
868 * This function implements TRM Figure 14-27.
869 * The ep argument is a physical endpoint number for a non-ISO OUT endpoint
870 * in the range 1 to 15.
871 */
872 static void omap1510_udc_epn_rx (int ep)
873 {
874 unsigned short status;
875
876 /* Check endpoint status */
877 status = inw (UDC_STAT_FLG);
878
879 if (status & UDC_ACK) {
880 int nbytes;
881 struct usb_endpoint_instance *endpoint =
882 omap1510_find_ep (ep);
883
884 nbytes = omap1510_read_noniso_rx_fifo (endpoint);
885 usbd_rcv_complete (endpoint, nbytes, 0);
886
887 /* enable rx FIFO to prepare for next packet */
888 outw (UDC_Set_FIFO_En, UDC_CTRL);
889 } else if (status & UDC_STALL) {
890 UDCDBGA ("STALL on RX endpoint %d", ep);
891 } else if (status & UDC_NAK) {
892 UDCDBGA ("NAK on RX ep %d", ep);
893 } else {
894 serial_printf ("omap-bi: RX on ep %d with status %x", ep,
895 status);
896 }
897 }
898
899 /* Handle TX transaction on non-ISO endpoint.
900 * This function implements TRM Figure 14-29.
901 * The ep argument is a physical endpoint number for a non-ISO IN endpoint
902 * in the range 16 to 30.
903 */
904 static void omap1510_udc_epn_tx (int ep)
905 {
906 unsigned short status;
907
908 /*serial_printf("omap1510_udc_epn_tx( %x )\n",ep); */
909
910 /* Check endpoint status */
911 status = inw (UDC_STAT_FLG);
912
913 if (status & UDC_ACK) {
914 struct usb_endpoint_instance *endpoint =
915 omap1510_find_ep (ep);
916
917 /* We need to transmit a terminating zero-length packet now if
918 * we have sent all of the data in this URB and the transfer
919 * size was an exact multiple of the packet size.
920 */
921 if (endpoint->tx_urb
922 && (endpoint->last == endpoint->tx_packetSize)
923 && (endpoint->tx_urb->actual_length - endpoint->sent -
924 endpoint->last == 0)) {
925 /* Prepare to transmit a zero-length packet. */
926 endpoint->sent += endpoint->last;
927 /* write 0 bytes of data to FIFO */
928 omap1510_write_noniso_tx_fifo (endpoint);
929 /* enable tx FIFO to start transmission */
930 outw (UDC_Set_FIFO_En, UDC_CTRL);
931 } else if (endpoint->tx_urb
932 && endpoint->tx_urb->actual_length) {
933 /* retire the data that was just sent */
934 usbd_tx_complete (endpoint);
935 /* Check to see if we have more data ready to transmit
936 * now.
937 */
938 if (endpoint->tx_urb
939 && endpoint->tx_urb->actual_length) {
940 /* write data to FIFO */
941 omap1510_write_noniso_tx_fifo (endpoint);
942 /* enable tx FIFO to start transmission */
943 outw (UDC_Set_FIFO_En, UDC_CTRL);
944 }
945 }
946 } else if (status & UDC_STALL) {
947 UDCDBGA ("STALL on TX endpoint %d", ep);
948 } else if (status & UDC_NAK) {
949 UDCDBGA ("NAK on TX endpoint %d", ep);
950 } else {
951 /*serial_printf("omap-bi: TX on ep %d with status %x\n", ep, status); */
952 }
953 }
954
955
956 /*
957 -------------------------------------------------------------------------------
958 */
959
960 /* Handle general USB interrupts and dispatch according to type.
961 * This function implements TRM Figure 14-13.
962 */
963 void omap1510_udc_irq (void)
964 {
965 u16 irq_src = inw (UDC_IRQ_SRC);
966 int valid_irq = 0;
967
968 if (!(irq_src & ~UDC_SOF_Flg)) /* ignore SOF interrupts ) */
969 return;
970
971 UDCDBGA ("< IRQ #%d start >- %x", udc_interrupts, irq_src);
972 /*serial_printf("< IRQ #%d start >- %x\n", udc_interrupts, irq_src); */
973
974 if (irq_src & UDC_DS_Chg) {
975 /* Device status changed */
976 omap1510_udc_state_changed ();
977 valid_irq++;
978 }
979 if (irq_src & UDC_EP0_RX) {
980 /* Endpoint 0 receive */
981 outw (UDC_EP0_RX, UDC_IRQ_SRC); /* ack interrupt */
982 omap1510_udc_ep0_rx (udc_device->bus->endpoint_array + 0);
983 valid_irq++;
984 }
985 if (irq_src & UDC_EP0_TX) {
986 /* Endpoint 0 transmit */
987 outw (UDC_EP0_TX, UDC_IRQ_SRC); /* ack interrupt */
988 omap1510_udc_ep0_tx (udc_device->bus->endpoint_array + 0);
989 valid_irq++;
990 }
991 if (irq_src & UDC_Setup) {
992 /* Device setup */
993 omap1510_udc_setup (udc_device->bus->endpoint_array + 0);
994 valid_irq++;
995 }
996 /*if (!valid_irq) */
997 /* serial_printf("unknown interrupt, IRQ_SRC %.4x\n", irq_src); */
998 UDCDBGA ("< IRQ #%d end >", udc_interrupts);
999 udc_interrupts++;
1000 }
1001
1002 /* This function implements TRM Figure 14-26. */
1003 void omap1510_udc_noniso_irq (void)
1004 {
1005 unsigned short epnum;
1006 unsigned short irq_src = inw (UDC_IRQ_SRC);
1007 int valid_irq = 0;
1008
1009 if (!(irq_src & (UDC_EPn_RX | UDC_EPn_TX)))
1010 return;
1011
1012 UDCDBGA ("non-ISO IRQ, IRQ_SRC %x", inw (UDC_IRQ_SRC));
1013
1014 if (irq_src & UDC_EPn_RX) { /* Endpoint N OUT transaction */
1015 /* Determine the endpoint number for this interrupt */
1016 epnum = (inw (UDC_EPN_STAT) & 0x0f00) >> 8;
1017 UDCDBGA ("RX on ep %x", epnum);
1018
1019 /* acknowledge interrupt */
1020 outw (UDC_EPn_RX, UDC_IRQ_SRC);
1021
1022 if (epnum) {
1023 /* select the endpoint FIFO */
1024 outw (UDC_EP_Sel | epnum, UDC_EP_NUM);
1025
1026 omap1510_udc_epn_rx (epnum);
1027
1028 /* deselect the endpoint FIFO */
1029 outw (epnum, UDC_EP_NUM);
1030 }
1031 valid_irq++;
1032 }
1033 if (irq_src & UDC_EPn_TX) { /* Endpoint N IN transaction */
1034 /* Determine the endpoint number for this interrupt */
1035 epnum = (inw (UDC_EPN_STAT) & 0x000f) | USB_DIR_IN;
1036 UDCDBGA ("TX on ep %x", epnum);
1037
1038 /* acknowledge interrupt */
1039 outw (UDC_EPn_TX, UDC_IRQ_SRC);
1040
1041 if (epnum) {
1042 /* select the endpoint FIFO */
1043 outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM);
1044
1045 omap1510_udc_epn_tx (epnum);
1046
1047 /* deselect the endpoint FIFO */
1048 outw (UDC_EP_Dir | epnum, UDC_EP_NUM);
1049 }
1050 valid_irq++;
1051 }
1052 if (!valid_irq)
1053 serial_printf (": unknown non-ISO interrupt, IRQ_SRC %.4x\n",
1054 irq_src);
1055 }
1056
1057 /*
1058 -------------------------------------------------------------------------------
1059 */
1060
1061
1062 /*
1063 * Start of public functions.
1064 */
1065
1066 /* Called to start packet transmission. */
1067 void udc_endpoint_write (struct usb_endpoint_instance *endpoint)
1068 {
1069 unsigned short epnum =
1070 endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK;
1071
1072 UDCDBGA ("Starting transmit on ep %x", epnum);
1073
1074 if (endpoint->tx_urb) {
1075 /* select the endpoint FIFO */
1076 outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM);
1077 /* write data to FIFO */
1078 omap1510_write_noniso_tx_fifo (endpoint);
1079 /* enable tx FIFO to start transmission */
1080 outw (UDC_Set_FIFO_En, UDC_CTRL);
1081 /* deselect the endpoint FIFO */
1082 outw (UDC_EP_Dir | epnum, UDC_EP_NUM);
1083 }
1084 }
1085
1086 /* Start to initialize h/w stuff */
1087 int udc_init (void)
1088 {
1089 u16 udc_rev;
1090 uchar value;
1091 ulong gpio;
1092 int i;
1093
1094 /* Let the device settle down before we start */
1095 for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000);
1096
1097 udc_device = NULL;
1098
1099 UDCDBG ("starting");
1100
1101 /* Check peripheral reset. Must be 1 to make sure
1102 MPU TIPB peripheral reset is inactive */
1103 UDCREG (ARM_RSTCT2);
1104
1105 /* Set and check clock control.
1106 * We might ought to be using the clock control API to do
1107 * this instead of fiddling with the clock registers directly
1108 * here.
1109 */
1110 outw ((1 << 4) | (1 << 5), CLOCK_CTRL);
1111 UDCREG (CLOCK_CTRL);
1112 /* Set and check APLL */
1113 outw (0x0008, APLL_CTRL);
1114 UDCREG (APLL_CTRL);
1115 /* Set and check DPLL */
1116 outw (0x2210, DPLL_CTRL);
1117 UDCREG (DPLL_CTRL);
1118 /* Set and check SOFT */
1119 outw ((1 << 4) | (1 << 3) | 1, SOFT_REQ);
1120 /* Short delay to wait for DPLL */
1121 udelay (1000);
1122
1123 /* Print banner with device revision */
1124 udc_rev = inw (UDC_REV) & 0xff;
1125 printf ("USB: TI OMAP1510 USB function module rev %d.%d\n",
1126 udc_rev >> 4, udc_rev & 0xf);
1127
1128 #ifdef CONFIG_OMAP_SX1
1129 i2c_read (0x32, 0x04, 1, &value, 1);
1130 value |= 0x04;
1131 i2c_write (0x32, 0x04, 1, &value, 1);
1132
1133 i2c_read (0x32, 0x03, 1, &value, 1);
1134 value |= 0x01;
1135 i2c_write (0x32, 0x03, 1, &value, 1);
1136
1137 gpio = inl(GPIO_PIN_CONTROL_REG);
1138 gpio |= 0x0002; /* A_IRDA_OFF */
1139 gpio |= 0x0800; /* A_SWITCH */
1140 gpio |= 0x8000; /* A_USB_ON */
1141 outl (gpio, GPIO_PIN_CONTROL_REG);
1142
1143 gpio = inl(GPIO_DIR_CONTROL_REG);
1144 gpio &= ~0x0002; /* A_IRDA_OFF */
1145 gpio &= ~0x0800; /* A_SWITCH */
1146 gpio &= ~0x8000; /* A_USB_ON */
1147 outl (gpio, GPIO_DIR_CONTROL_REG);
1148
1149 gpio = inl(GPIO_DATA_OUTPUT_REG);
1150 gpio |= 0x0002; /* A_IRDA_OFF */
1151 gpio &= ~0x0800; /* A_SWITCH */
1152 gpio &= ~0x8000; /* A_USB_ON */
1153 outl (gpio, GPIO_DATA_OUTPUT_REG);
1154 #endif
1155
1156 /* The VBUS_MODE bit selects whether VBUS detection is done via
1157 * software (1) or hardware (0). When software detection is
1158 * selected, VBUS_CTRL selects whether USB is not connected (0)
1159 * or connected (1).
1160 */
1161 outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0);
1162 outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0);
1163 UDCREGL (FUNC_MUX_CTRL_0);
1164
1165 /*
1166 * At this point, device is ready for configuration...
1167 */
1168
1169 UDCDBG ("disable USB interrupts");
1170 outw (0, UDC_IRQ_EN);
1171 UDCREG (UDC_IRQ_EN);
1172
1173 UDCDBG ("disable USB DMA");
1174 outw (0, UDC_DMA_IRQ_EN);
1175 UDCREG (UDC_DMA_IRQ_EN);
1176
1177 UDCDBG ("initialize SYSCON1");
1178 outw (UDC_Self_Pwr | UDC_Pullup_En, UDC_SYSCON1);
1179 UDCREG (UDC_SYSCON1);
1180
1181 return 0;
1182 }
1183
1184 /* Stall endpoint */
1185 static void udc_stall_ep (unsigned int ep_addr)
1186 {
1187 /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */
1188 int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
1189
1190 UDCDBGA ("stall ep_addr %d", ep_addr);
1191
1192 /* REVISIT?
1193 * The OMAP TRM section 14.2.4.2 says we must check that the FIFO
1194 * is empty before halting the endpoint. The current implementation
1195 * doesn't check that the FIFO is empty.
1196 */
1197
1198 if (!ep_num) {
1199 outw (UDC_Stall_Cmd, UDC_SYSCON2);
1200 } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) {
1201 if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) {
1202 /* we have a valid rx endpoint, so halt it */
1203 outw (UDC_EP_Sel | ep_num, UDC_EP_NUM);
1204 outw (UDC_Set_Halt, UDC_CTRL);
1205 outw (ep_num, UDC_EP_NUM);
1206 }
1207 } else {
1208 if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) {
1209 /* we have a valid tx endpoint, so halt it */
1210 outw (UDC_EP_Sel | UDC_EP_Dir | ep_num, UDC_EP_NUM);
1211 outw (UDC_Set_Halt, UDC_CTRL);
1212 outw (ep_num, UDC_EP_NUM);
1213 }
1214 }
1215 }
1216
1217 /* Reset endpoint */
1218 #if 0
1219 static void udc_reset_ep (unsigned int ep_addr)
1220 {
1221 /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */
1222 int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
1223
1224 UDCDBGA ("reset ep_addr %d", ep_addr);
1225
1226 if (!ep_num) {
1227 /* control endpoint 0 can't be reset */
1228 } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) {
1229 UDCDBGA ("UDC_EP_RX(%d) = 0x%04x", ep_num,
1230 inw (UDC_EP_RX (ep_num)));
1231 if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) {
1232 /* we have a valid rx endpoint, so reset it */
1233 outw (ep_num | UDC_EP_Sel, UDC_EP_NUM);
1234 outw (UDC_Reset_EP, UDC_CTRL);
1235 outw (ep_num, UDC_EP_NUM);
1236 UDCDBGA ("OUT endpoint %d reset", ep_num);
1237 }
1238 } else {
1239 UDCDBGA ("UDC_EP_TX(%d) = 0x%04x", ep_num,
1240 inw (UDC_EP_TX (ep_num)));
1241 /* Resetting of tx endpoints seems to be causing the USB function
1242 * module to fail, which causes problems when the driver is
1243 * uninstalled. We'll skip resetting tx endpoints for now until
1244 * we figure out what the problem is.
1245 */
1246 #if 0
1247 if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) {
1248 /* we have a valid tx endpoint, so reset it */
1249 outw (ep_num | UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM);
1250 outw (UDC_Reset_EP, UDC_CTRL);
1251 outw (ep_num | UDC_EP_Dir, UDC_EP_NUM);
1252 UDCDBGA ("IN endpoint %d reset", ep_num);
1253 }
1254 #endif
1255 }
1256 }
1257 #endif
1258
1259 /* ************************************************************************** */
1260
1261 /**
1262 * udc_check_ep - check logical endpoint
1263 *
1264 * Return physical endpoint number to use for this logical endpoint or zero if not valid.
1265 */
1266 #if 0
1267 int udc_check_ep (int logical_endpoint, int packetsize)
1268 {
1269 if ((logical_endpoint == 0x80) ||
1270 ((logical_endpoint & 0x8f) != logical_endpoint)) {
1271 return 0;
1272 }
1273
1274 switch (packetsize) {
1275 case 8:
1276 case 16:
1277 case 32:
1278 case 64:
1279 case 128:
1280 case 256:
1281 case 512:
1282 break;
1283 default:
1284 return 0;
1285 }
1286
1287 return EP_ADDR_TO_PHYS_EP (logical_endpoint);
1288 }
1289 #endif
1290
1291 /*
1292 * udc_setup_ep - setup endpoint
1293 *
1294 * Associate a physical endpoint with endpoint_instance
1295 */
1296 void udc_setup_ep (struct usb_device_instance *device,
1297 unsigned int ep, struct usb_endpoint_instance *endpoint)
1298 {
1299 UDCDBGA ("setting up endpoint addr %x", endpoint->endpoint_address);
1300
1301 /* This routine gets called by bi_modinit for endpoint 0 and from
1302 * bi_config for all of the other endpoints. bi_config gets called
1303 * during the DEVICE_CREATE, DEVICE_CONFIGURED, and
1304 * DEVICE_SET_INTERFACE events. We need to reconfigure the OMAP packet
1305 * RAM after bi_config scans the selected device configuration and
1306 * initializes the endpoint structures, but before this routine enables
1307 * the OUT endpoint FIFOs. Since bi_config calls this routine in a
1308 * loop for endpoints 1 through UDC_MAX_ENDPOINTS, we reconfigure our
1309 * packet RAM here when ep==1.
1310 * I really hate to do this here, but it seems like the API exported
1311 * by the USB bus interface controller driver to the usbd-bi module
1312 * isn't quite right so there is no good place to do this.
1313 */
1314 if (ep == 1) {
1315 omap1510_deconfigure_device ();
1316 omap1510_configure_device (device);
1317 }
1318
1319 if (endpoint && (ep < UDC_MAX_ENDPOINTS)) {
1320 int ep_addr = endpoint->endpoint_address;
1321
1322 if (!ep_addr) {
1323 /* nothing to do for endpoint 0 */
1324 } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
1325 /* nothing to do for IN (tx) endpoints */
1326 } else { /* OUT (rx) endpoint */
1327 if (endpoint->rcv_packetSize) {
1328 /*struct urb* urb = &(urb_out_array[ep&0xFF]); */
1329 /*urb->endpoint = endpoint; */
1330 /*urb->device = device; */
1331 /*urb->buffer_length = sizeof(urb->buffer); */
1332
1333 /*endpoint->rcv_urb = urb; */
1334 omap1510_prepare_endpoint_for_rx (ep_addr);
1335 }
1336 }
1337 }
1338 }
1339
1340 /**
1341 * udc_disable_ep - disable endpoint
1342 * @ep:
1343 *
1344 * Disable specified endpoint
1345 */
1346 #if 0
1347 void udc_disable_ep (unsigned int ep_addr)
1348 {
1349 /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */
1350 int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
1351 struct usb_endpoint_instance *endpoint = omap1510_find_ep (ep_addr); /*udc_device->bus->endpoint_array + ep; */
1352
1353 UDCDBGA ("disable ep_addr %d", ep_addr);
1354
1355 if (!ep_num) {
1356 /* nothing to do for endpoint 0 */ ;
1357 } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
1358 if (endpoint->tx_packetSize) {
1359 /* we have a valid tx endpoint */
1360 /*usbd_flush_tx(endpoint); */
1361 endpoint->tx_urb = NULL;
1362 }
1363 } else {
1364 if (endpoint->rcv_packetSize) {
1365 /* we have a valid rx endpoint */
1366 /*usbd_flush_rcv(endpoint); */
1367 endpoint->rcv_urb = NULL;
1368 }
1369 }
1370 }
1371 #endif
1372
1373 /* ************************************************************************** */
1374
1375 /**
1376 * udc_connected - is the USB cable connected
1377 *
1378 * Return non-zero if cable is connected.
1379 */
1380 #if 0
1381 int udc_connected (void)
1382 {
1383 return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT);
1384 }
1385 #endif
1386
1387 /* Turn on the USB connection by enabling the pullup resistor */
1388 void udc_connect (void)
1389 {
1390 UDCDBG ("connect, enable Pullup");
1391 outl (0x00000018, FUNC_MUX_CTRL_D);
1392 }
1393
1394 /* Turn off the USB connection by disabling the pullup resistor */
1395 void udc_disconnect (void)
1396 {
1397 UDCDBG ("disconnect, disable Pullup");
1398 outl (0x00000000, FUNC_MUX_CTRL_D);
1399 }
1400
1401 /* ************************************************************************** */
1402
1403
1404 /*
1405 * udc_disable_interrupts - disable interrupts
1406 * switch off interrupts
1407 */
1408 #if 0
1409 void udc_disable_interrupts (struct usb_device_instance *device)
1410 {
1411 UDCDBG ("disabling all interrupts");
1412 outw (0, UDC_IRQ_EN);
1413 }
1414 #endif
1415
1416 /* ************************************************************************** */
1417
1418 /**
1419 * udc_ep0_packetsize - return ep0 packetsize
1420 */
1421 #if 0
1422 int udc_ep0_packetsize (void)
1423 {
1424 return EP0_PACKETSIZE;
1425 }
1426 #endif
1427
1428 /* Switch on the UDC */
1429 void udc_enable (struct usb_device_instance *device)
1430 {
1431 UDCDBGA ("enable device %p, status %d", device, device->status);
1432
1433 /* initialize driver state variables */
1434 udc_devstat = 0;
1435
1436 /* Save the device structure pointer */
1437 udc_device = device;
1438
1439 /* Setup ep0 urb */
1440 if (!ep0_urb) {
1441 ep0_urb =
1442 usbd_alloc_urb (udc_device,
1443 udc_device->bus->endpoint_array);
1444 } else {
1445 serial_printf ("udc_enable: ep0_urb already allocated %p\n",
1446 ep0_urb);
1447 }
1448
1449 UDCDBG ("Check clock status");
1450 UDCREG (STATUS_REQ);
1451
1452 /* The VBUS_MODE bit selects whether VBUS detection is done via
1453 * software (1) or hardware (0). When software detection is
1454 * selected, VBUS_CTRL selects whether USB is not connected (0)
1455 * or connected (1).
1456 */
1457 outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_CTRL | UDC_VBUS_MODE,
1458 FUNC_MUX_CTRL_0);
1459 UDCREGL (FUNC_MUX_CTRL_0);
1460
1461 omap1510_configure_device (device);
1462 }
1463
1464 /* Switch off the UDC */
1465 void udc_disable (void)
1466 {
1467 UDCDBG ("disable UDC");
1468
1469 omap1510_deconfigure_device ();
1470
1471 /* The VBUS_MODE bit selects whether VBUS detection is done via
1472 * software (1) or hardware (0). When software detection is
1473 * selected, VBUS_CTRL selects whether USB is not connected (0)
1474 * or connected (1).
1475 */
1476 outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0);
1477 outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0);
1478 UDCREGL (FUNC_MUX_CTRL_0);
1479
1480 /* Free ep0 URB */
1481 if (ep0_urb) {
1482 /*usbd_dealloc_urb(ep0_urb); */
1483 ep0_urb = NULL;
1484 }
1485
1486 /* Reset device pointer.
1487 * We ought to do this here to balance the initialization of udc_device
1488 * in udc_enable, but some of our other exported functions get called
1489 * by the bus interface driver after udc_disable, so we have to hang on
1490 * to the device pointer to avoid a null pointer dereference. */
1491 /* udc_device = NULL; */
1492 }
1493
1494 /**
1495 * udc_startup - allow udc code to do any additional startup
1496 */
1497 void udc_startup_events (struct usb_device_instance *device)
1498 {
1499 /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
1500 usbd_device_event_irq (device, DEVICE_INIT, 0);
1501
1502 /* The DEVICE_CREATE event puts the USB device in the state
1503 * STATE_ATTACHED.
1504 */
1505 usbd_device_event_irq (device, DEVICE_CREATE, 0);
1506
1507 /* Some USB controller driver implementations signal
1508 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
1509 * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
1510 * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
1511 * The OMAP USB client controller has the capability to detect when the
1512 * USB cable is connected to a powered USB bus via the ATT bit in the
1513 * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and
1514 * DEVICE_RESET events until later.
1515 */
1516
1517 udc_enable (device);
1518 }
1519
1520 /**
1521 * udc_irq - do pseudo interrupts
1522 */
1523 void udc_irq(void)
1524 {
1525 /* Loop while we have interrupts.
1526 * If we don't do this, the input chain
1527 * polling delay is likely to miss
1528 * host requests.
1529 */
1530 while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) {
1531 /* Handle any new IRQs */
1532 omap1510_udc_irq ();
1533 omap1510_udc_noniso_irq ();
1534 }
1535 }
1536
1537 /* Flow control */
1538 void udc_set_nak(int epid)
1539 {
1540 /* TODO: implement this functionality in omap1510 */
1541 }
1542
1543 void udc_unset_nak (int epid)
1544 {
1545 /* TODO: implement this functionality in omap1510 */
1546 }
1547 #endif
u-boot for m93030