arch/arc/dts/axs10x_mb.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
   4  */
   5
   6 / {
   7         aliases {
   8                 spi0 = &spi0;
   9         };
  10
  11         axs10x_mb@e0000000 {
  12                 compatible = "simple-bus";
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges = <0x00000000 0xe0000000 0x10000000>;
  16                 bootph-all;
  17
  18                 clocks {
  19                         compatible = "simple-bus";
  20                         bootph-all;
  21
  22                         apbclk: apbclk {
  23                                 compatible = "fixed-clock";
  24                                 clock-frequency = <50000000>;
  25                                 #clock-cells = <0>;
  26                         };
  27
  28                         uartclk: uartclk {
  29                                 compatible = "fixed-clock";
  30                                 clock-frequency = <33333333>;
  31                                 #clock-cells = <0>;
  32                                 bootph-all;
  33                         };
  34
  35                         mmcclk_ciu: mmcclk-ciu {
  36                                 compatible = "fixed-clock";
  37                                 /*
  38                                  * DW sdio controller has external ciu clock divider
  39                                  * controlled via register in SDIO IP. It divides
  40                                  * sdio_ref_clk (which comes from CGU) by 16 for
  41                                  * default. So default mmcclk clock (which comes
  42                                  * to sdk_in) is 25000000 Hz.
  43                                  */
  44                                 clock-frequency = <25000000>;
  45                                 #clock-cells = <0>;
  46                         };
  47
  48                         mmcclk_biu: mmcclk-biu {
  49                                 compatible = "fixed-clock";
  50                                 clock-frequency = <50000000>;
  51                                 #clock-cells = <0>;
  52                         };
  53                 };
  54
  55                 ethernet@18000 {
  56                         compatible = "snps,arc-dwmac-3.70a";
  57                         reg = < 0x18000 0x2000 >;
  58                         phy-mode = "gmii";
  59                         snps,pbl = < 32 >;
  60                         clocks = <&apbclk>;
  61                         clock-names = "stmmaceth";
  62                         max-speed = <100>;
  63                 };
  64
  65                 ehci@40000 {
  66                         compatible = "generic-ehci";
  67                         reg = < 0x40000 0x100 >;
  68                 };
  69
  70                 ohci@60000 {
  71                         compatible = "generic-ohci";
  72                         reg = < 0x60000 0x100 >;
  73                 };
  74
  75                 mmc: mmc@15000 {
  76                         compatible = "snps,dw-mshc";
  77                         reg = <0x15000 0x400>;
  78                         bus-width = <4>;
  79                         clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
  80                         clock-names = "biu", "ciu";
  81                         max-frequency = <25000000>;
  82                 };
  83
  84                 uart0: serial0@22000 {
  85                         compatible = "snps,dw-apb-uart";
  86                         reg = <0x22000 0x100>;
  87                         clocks = <&uartclk>;
  88                         reg-shift = <2>;
  89                         reg-io-width = <4>;
  90                 };
  91
  92                 spi0: spi@0 {
  93                         compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
  94                         reg = <0x0 0x100>;
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         spi-max-frequency = <4000000>;
  98                         clocks = <&apbclk>;
  99                         clock-names = "spi_clk";
 100                         num-cs = <1>;
 101                         cs-gpios = <&cs_gpio 0>;
 102                         spi_flash@0 {
 103                                 compatible = "jedec,spi-nor";
 104                                 reg = <0>;
 105                                 spi-max-frequency = <4000000>;
 106                         };
 107                 };
 108
 109                 cs_gpio: gpio@11218 {
 110                         compatible = "snps,creg-gpio";
 111                         reg = <0x11218 0x4>;
 112                         gpio-controller;
 113                         #gpio-cells = <1>;
 114                         gpio-bank-name = "axs-spi-cs";
 115                         gpio-count = <1>;
 116                         gpio-first-shift = <0>;
 117                         gpio-bit-per-line = <2>;
 118                         gpio-activate-val = <1>;
 119                         gpio-deactivate-val = <3>;
 120                         gpio-default-val = <1>;
 121                 };
 122         };
 123 };