include/common_timing_params.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef COMMON_TIMING_PARAMS_H
   7 #define COMMON_TIMING_PARAMS_H
   8
   9 typedef struct {
  10         /* parameters to constrict */
  11
  12         unsigned int tckmin_x_ps;
  13         unsigned int tckmax_ps;
  14         unsigned int trcd_ps;
  15         unsigned int trp_ps;
  16         unsigned int tras_ps;
  17 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  18         unsigned int taamin_ps;
  19 #endif
  20
  21 #ifdef CONFIG_SYS_FSL_DDR4
  22         unsigned int trfc1_ps;
  23         unsigned int trfc2_ps;
  24         unsigned int trfc4_ps;
  25         unsigned int trrds_ps;
  26         unsigned int trrdl_ps;
  27         unsigned int tccdl_ps;
  28         unsigned int trfc_slr_ps;
  29 #else
  30         unsigned int twtr_ps;   /* maximum = 63750 ps */
  31         unsigned int trfc_ps;   /* maximum = 255 ns + 256 ns + .75 ns
  32                                            = 511750 ps */
  33
  34         unsigned int trrd_ps;   /* maximum = 63750 ps */
  35         unsigned int trtp_ps;   /* byte 38, spd->trtp */
  36 #endif
  37         unsigned int twr_ps;    /* maximum = 63750 ps */
  38         unsigned int trc_ps;    /* maximum = 254 ns + .75 ns = 254750 ps */
  39
  40         unsigned int refresh_rate_ps;
  41         unsigned int extended_op_srt;
  42
  43 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
  44         unsigned int tis_ps;    /* byte 32, spd->ca_setup */
  45         unsigned int tih_ps;    /* byte 33, spd->ca_hold */
  46         unsigned int tds_ps;    /* byte 34, spd->data_setup */
  47         unsigned int tdh_ps;    /* byte 35, spd->data_hold */
  48         unsigned int tdqsq_max_ps;      /* byte 44, spd->tdqsq */
  49         unsigned int tqhs_ps;   /* byte 45, spd->tqhs */
  50 #endif
  51
  52         unsigned int ndimms_present;
  53         unsigned int lowest_common_spd_caslat;
  54         unsigned int highest_common_derated_caslat;
  55         unsigned int additive_latency;
  56         unsigned int all_dimms_burst_lengths_bitmask;
  57         unsigned int all_dimms_registered;
  58         unsigned int all_dimms_unbuffered;
  59         unsigned int all_dimms_ecc_capable;
  60
  61         unsigned long long total_mem;
  62         unsigned long long base_address;
  63
  64         /* DDR3 RDIMM */
  65         unsigned char rcw[16];  /* Register Control Word 0-15 */
  66 } common_timing_params_t;
  67
  68 #endif