1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __IMX8M_PHANBELL_H
7 #define __IMX8M_PHANBELL_H
9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h>
12 #ifdef CONFIG_XPL_BUILD
13 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
15 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
16 #define CFG_MALLOC_F_ADDR 0x182000
17 /* For RAW image gives a error info not panic */
22 #if defined(CONFIG_CMD_NET)
23 #define CFG_FEC_MXC_PHYADDR 0
26 #define CFG_MFG_ENV_SETTINGS \
27 "initrd_addr=0x43800000\0" \
28 "initrd_high=0xffffffff\0" \
30 /* Initial environment variables */
31 #define CFG_EXTRA_ENV_SETTINGS \
32 CFG_MFG_ENV_SETTINGS \
35 "console=ttymxc0,115200\0" \
36 "fdt_addr=0x43000000\0" \
37 "fdt_high=0xffffffffffffffff\0" \
39 "fdt_file=imx8mq-phanbell.dtb\0" \
40 "initrd_addr=0x43800000\0" \
41 "initrd_high=0xffffffffffffffff\0" \
42 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
44 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
45 "mmcautodetect=yes\0" \
46 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
47 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
48 "bootscript=echo Running bootscript from mmc ...; " \
50 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
51 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
52 "mmcboot=echo Booting from mmc ...; " \
54 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
55 "if run loadfdt; then " \
56 "booti ${loadaddr} - ${fdt_addr}; " \
58 "echo WARN: Cannot load the DT; " \
61 "echo wait for boot; " \
63 "netargs=setenv bootargs console=${console} " \
65 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
66 "netboot=echo Booting from net ...; " \
68 "if test ${ip_dyn} = yes; then " \
69 "setenv get_cmd dhcp; " \
71 "setenv get_cmd tftp; " \
73 "${get_cmd} ${loadaddr} ${image}; " \
74 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
75 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
76 "booti ${loadaddr} - ${fdt_addr}; " \
78 "echo WARN: Cannot load the DT; " \
84 /* Link Definitions */
86 #define CFG_SYS_INIT_RAM_ADDR 0x40000000
87 #define CFG_SYS_INIT_RAM_SIZE 0x80000
89 #define CFG_SYS_SDRAM_BASE 0x40000000
90 #define PHYS_SDRAM 0x40000000
91 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
93 #define CFG_MXC_UART_BASE UART_BASE_ADDR(1)
95 #define CFG_SYS_FSL_USDHC_NUM 2
96 #define CFG_SYS_FSL_ESDHC_ADDR 0