include/configs/imx8mq_reform2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __IMX8M_REFORM2_H
   7 #define __IMX8M_REFORM2_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #ifdef CONFIG_XPL_BUILD
  14 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  15
  16 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  17 #define CFG_MALLOC_F_ADDR               0x182000
  18 /* For RAW image gives a error info not panic */
  19 #endif
  20
  21 /* ENET Config */
  22 /* ENET1 */
  23 #if defined(CONFIG_CMD_NET)
  24 #define CFG_FEC_MXC_PHYADDR             4
  25 #endif
  26
  27 #define BOOT_TARGET_DEVICES(func) \
  28         func(MMC, mmc, 1) \
  29         func(MMC, mmc, 0) \
  30         func(USB, usb, 0) \
  31         func(DHCP, dhcp, na)
  32
  33 #include <config_distro_bootcmd.h>
  34
  35 /* Initial environment variables */
  36 #define CFG_EXTRA_ENV_SETTINGS          \
  37         BOOTENV \
  38         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  39         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  40         "image=Image\0" \
  41         "console=ttymxc0,115200\0" \
  42         "fdt_addr_r=0x43000000\0" \
  43         "ramdisk_addr_r=0x44000000\0" \
  44         "boot_fdt=try\0" \
  45         "fdtfile=imx8mq-mnt-reform2.dtb\0" \
  46         "initrd_addr=0x43800000\0" \
  47         "bootm_size=0x10000000\0" \
  48         "mmcpart=1\0" \
  49         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  50         "stdin=serial,usbkbd\0"
  51
  52 /* Link Definitions */
  53
  54 #define CFG_SYS_INIT_RAM_ADDR           0x40000000
  55 #define CFG_SYS_INIT_RAM_SIZE           0x80000
  56
  57 #define CFG_SYS_SDRAM_BASE              0x40000000
  58 #define PHYS_SDRAM                      0x40000000
  59 #define PHYS_SDRAM_SIZE                 0x100000000     /* 4 GiB DDR */
  60
  61 #define CFG_MXC_UART_BASE               UART_BASE_ADDR(1)
  62
  63 #define CFG_SYS_FSL_USDHC_NUM           2
  64 #define CFG_SYS_FSL_ESDHC_ADDR          0
  65
  66 #endif