include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  12 #define SYS_NO_FLASH
  13 #endif
  14
  15 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  16
  17 #define SPD_EEPROM_ADDRESS              0x51
  18
  19 /*
  20  * IFC Definitions
  21  */
  22 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  23 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  24 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128*1024*1024)
  25 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  26
  27 #define CFG_SYS_NOR0_CSPR                                       \
  28         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)                | \
  29         CSPR_PORT_SIZE_16                                       | \
  30         CSPR_MSEL_NOR                                           | \
  31         CSPR_V)
  32 #define CFG_SYS_NOR0_CSPR_EARLY                         \
  33         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)  | \
  34         CSPR_PORT_SIZE_16                                       | \
  35         CSPR_MSEL_NOR                                           | \
  36         CSPR_V)
  37 #define CFG_SYS_NOR1_CSPR                                       \
  38         (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS)               | \
  39         CSPR_PORT_SIZE_16                                       | \
  40         CSPR_MSEL_NOR                                           | \
  41         CSPR_V)
  42 #define CFG_SYS_NOR1_CSPR_EARLY                         \
  43         (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  44         CSPR_PORT_SIZE_16                                       | \
  45         CSPR_MSEL_NOR                                           | \
  46         CSPR_V)
  47 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(12)
  48 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
  49                                 FTIM0_NOR_TEADC(0x5) | \
  50                                 FTIM0_NOR_TAVDS(0x6) | \
  51                                 FTIM0_NOR_TEAHC(0x5))
  52 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
  53                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  54                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  55 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x8) | \
  56                                 FTIM2_NOR_TCH(0x8) | \
  57                                 FTIM2_NOR_TWPH(0xe) | \
  58                                 FTIM2_NOR_TWP(0x1c))
  59 #define CFG_SYS_NOR_FTIM3       0x04000000
  60 #define CFG_SYS_IFC_CCR 0x01000000
  61
  62 #ifndef SYS_NO_FLASH
  63 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE,\
  64                                          CFG_SYS_FLASH_BASE + 0x40000000}
  65 #endif
  66 #endif
  67
  68 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  69 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  70                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  71                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  72                                 | CSPR_V)
  73 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024)
  74
  75 #define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  76                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  77                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  78                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  79                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  80                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  81                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  82
  83 /* ONFI NAND Flash mode0 Timing Params */
  84 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
  85                                         FTIM0_NAND_TWP(0x18)   | \
  86                                         FTIM0_NAND_TWCHT(0x07) | \
  87                                         FTIM0_NAND_TWH(0x0a))
  88 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  89                                         FTIM1_NAND_TWBE(0x39)  | \
  90                                         FTIM1_NAND_TRR(0x0e)   | \
  91                                         FTIM1_NAND_TRP(0x18))
  92 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
  93                                         FTIM2_NAND_TREH(0x0a) | \
  94                                         FTIM2_NAND_TWHRE(0x1e))
  95 #define CFG_SYS_NAND_FTIM3              0x0
  96
  97 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
  98
  99 #define CFG_SYS_I2C_FPGA_ADDR   0x66
 100 #define QIXIS_LBMAP_SWITCH              6
 101 #define QIXIS_QMAP_MASK                 0xe0
 102 #define QIXIS_QMAP_SHIFT                5
 103 #define QIXIS_LBMAP_MASK                0x0f
 104 #define QIXIS_LBMAP_SHIFT               0
 105 #define QIXIS_LBMAP_DFLTBANK            0x0e
 106 #define QIXIS_LBMAP_ALTBANK             0x2e
 107 #define QIXIS_LBMAP_SD                  0x00
 108 #define QIXIS_LBMAP_EMMC                0x00
 109 #define QIXIS_LBMAP_IFC                 0x00
 110 #define QIXIS_LBMAP_SD_QSPI             0x0e
 111 #define QIXIS_LBMAP_QSPI                0x0e
 112 #define QIXIS_RCW_SRC_IFC               0x25
 113 #define QIXIS_RCW_SRC_SD                0x40
 114 #define QIXIS_RCW_SRC_EMMC              0x41
 115 #define QIXIS_RCW_SRC_QSPI              0x62
 116 #define QIXIS_RST_CTL_RESET             0x41
 117 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 118 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 119 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 120 #define QIXIS_RST_FORCE_MEM             0x01
 121 #define QIXIS_STAT_PRES1                0xb
 122 #define QIXIS_SDID_MASK                 0x07
 123 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 124
 125 #define CFG_SYS_FPGA_CSPR_EXT   (0x0)
 126 #define CFG_SYS_FPGA_CSPR               (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 127                                         | CSPR_PORT_SIZE_8 \
 128                                         | CSPR_MSEL_GPCM \
 129                                         | CSPR_V)
 130 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 131                                         | CSPR_PORT_SIZE_8 \
 132                                         | CSPR_MSEL_GPCM \
 133                                         | CSPR_V)
 134
 135 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 136 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 137 #define CFG_SYS_FPGA_CSOR               CSOR_GPCM_ADM_SHIFT(0)
 138 #else
 139 #define CFG_SYS_FPGA_CSOR               CSOR_GPCM_ADM_SHIFT(12)
 140 #endif
 141 /* QIXIS Timing parameters*/
 142 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 143                                         FTIM0_GPCM_TEADC(0x0e) | \
 144                                         FTIM0_GPCM_TEAHC(0x0e))
 145 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 146                                         FTIM1_GPCM_TRAD(0x3f))
 147 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 148                                         FTIM2_GPCM_TCH(0xf) | \
 149                                         FTIM2_GPCM_TWP(0x3E))
 150 #define SYS_FPGA_CS_FTIM3       0x0
 151
 152 #ifdef CONFIG_TFABOOT
 153 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 154 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR_EARLY
 155 #define CFG_SYS_CSPR0_FINAL             CFG_SYS_NOR0_CSPR
 156 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 157 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 158 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 159 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 160 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 161 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 162 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 163 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR_EARLY
 164 #define CFG_SYS_CSPR1_FINAL             CFG_SYS_NOR1_CSPR
 165 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK_EARLY
 166 #define CFG_SYS_AMASK1_FINAL            CFG_SYS_NOR_AMASK
 167 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 168 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 169 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 170 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 171 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 172 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 173 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 174 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 175 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 176 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 177 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 178 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 179 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 180 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 181 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 182 #define CFG_SYS_CSPR3_FINAL             SYS_FPGA_CSPR_FINAL
 183 #define CFG_SYS_AMASK3          SYS_FPGA_AMASK
 184 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 185 #define CFG_SYS_CS3_FTIM0               SYS_FPGA_CS_FTIM0
 186 #define CFG_SYS_CS3_FTIM1               SYS_FPGA_CS_FTIM1
 187 #define CFG_SYS_CS3_FTIM2               SYS_FPGA_CS_FTIM2
 188 #define CFG_SYS_CS3_FTIM3               SYS_FPGA_CS_FTIM3
 189 #else
 190 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 191 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 192 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 193 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 194 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 195 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 196 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 197 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 198 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 199 #define CFG_SYS_CSPR2_EXT               CFG_SYS_FPGA_CSPR_EXT
 200 #define CFG_SYS_CSPR2           CFG_SYS_FPGA_CSPR
 201 #define CFG_SYS_CSPR2_FINAL             SYS_FPGA_CSPR_FINAL
 202 #define CFG_SYS_AMASK2          SYS_FPGA_AMASK
 203 #define CFG_SYS_CSOR2           CFG_SYS_FPGA_CSOR
 204 #define CFG_SYS_CS2_FTIM0               SYS_FPGA_CS_FTIM0
 205 #define CFG_SYS_CS2_FTIM1               SYS_FPGA_CS_FTIM1
 206 #define CFG_SYS_CS2_FTIM2               SYS_FPGA_CS_FTIM2
 207 #define CFG_SYS_CS2_FTIM3               SYS_FPGA_CS_FTIM3
 208 #else
 209 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 210 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR_EARLY
 211 #define CFG_SYS_CSPR0_FINAL             CFG_SYS_NOR0_CSPR
 212 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 213 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 214 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 215 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 216 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 217 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 218 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 219 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR_EARLY
 220 #define CFG_SYS_CSPR1_FINAL             CFG_SYS_NOR1_CSPR
 221 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK_EARLY
 222 #define CFG_SYS_AMASK1_FINAL            CFG_SYS_NOR_AMASK
 223 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 224 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 225 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 226 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 227 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 228 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 229 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 230 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 231 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 232 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 233 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 234 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 235 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 236 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 237 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 238 #define CFG_SYS_CSPR3_FINAL             SYS_FPGA_CSPR_FINAL
 239 #define CFG_SYS_AMASK3          SYS_FPGA_AMASK
 240 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 241 #define CFG_SYS_CS3_FTIM0               SYS_FPGA_CS_FTIM0
 242 #define CFG_SYS_CS3_FTIM1               SYS_FPGA_CS_FTIM1
 243 #define CFG_SYS_CS3_FTIM2               SYS_FPGA_CS_FTIM2
 244 #define CFG_SYS_CS3_FTIM3               SYS_FPGA_CS_FTIM3
 245 #endif
 246 #endif
 247
 248 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 249
 250 /*
 251  * I2C bus multiplexer
 252  */
 253 #define I2C_MUX_PCA_ADDR_PRI            0x77
 254 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 255 #define I2C_RETIMER_ADDR                0x18
 256 #define I2C_RETIMER_ADDR2               0x19
 257 #define I2C_MUX_CH_DEFAULT              0x8
 258 #define I2C_MUX_CH5                     0xD
 259
 260 #define I2C_MUX_CH_VOL_MONITOR          0xA
 261
 262 /* Voltage monitor on channel 2*/
 263 #define I2C_VOL_MONITOR_ADDR           0x63
 264 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 265 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 266 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 267 #define I2C_SVDD_MONITOR_ADDR           0x4F
 268
 269 /* The lowest and highest voltage allowed for LS1088AQDS */
 270 #define VDD_MV_MIN                      819
 271 #define VDD_MV_MAX                      1212
 272
 273 #define PWM_CHANNEL0                    0x0
 274
 275 /*
 276 * RTC configuration
 277 */
 278 #define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 279
 280 #ifdef CONFIG_FSL_DSPI
 281 #if !defined(CONFIG_TFABOOT) && \
 282         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 283 #endif
 284 #endif
 285
 286 #define COMMON_ENV \
 287         "kernelheader_addr_r=0x80200000\0"      \
 288         "fdtheader_addr_r=0x80100000\0"         \
 289         "kernel_addr_r=0x81000000\0"            \
 290         "fdt_addr_r=0x90000000\0"               \
 291         "load_addr=0xa0000000\0"
 292
 293 /* Initial environment variables */
 294 #ifdef CONFIG_NXP_ESBC
 295 #undef CFG_EXTRA_ENV_SETTINGS
 296 #define CFG_EXTRA_ENV_SETTINGS          \
 297         COMMON_ENV                              \
 298         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 299         "loadaddr=0x90100000\0"                 \
 300         "kernel_addr=0x100000\0"                \
 301         "ramdisk_addr=0x800000\0"               \
 302         "ramdisk_size=0x2000000\0"              \
 303         "fdt_high=0xa0000000\0"                 \
 304         "initrd_high=0xffffffffffffffff\0"      \
 305         "kernel_start=0x1000000\0"              \
 306         "kernel_load=0xa0000000\0"              \
 307         "kernel_size=0x2800000\0"               \
 308         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 309         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 310         "sf read 0xa0e00000 0xe00000 0x100000;" \
 311         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 312         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 313         "mcmemsize=0x70000000 \0"
 314 #else /* if !(CONFIG_NXP_ESBC) */
 315 #ifdef CONFIG_TFABOOT
 316 #define QSPI_MC_INIT_CMD                                \
 317         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 318         "sf read 0x80e00000 0xE00000 0x100000;" \
 319         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 320 #define SD_MC_INIT_CMD                          \
 321         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 322         "mmc read 0x80e00000 0x7000 0x800;" \
 323         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 324 #define IFC_MC_INIT_CMD                         \
 325         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 326
 327 #undef CFG_EXTRA_ENV_SETTINGS
 328 #define CFG_EXTRA_ENV_SETTINGS          \
 329         COMMON_ENV                              \
 330         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 331         "loadaddr=0x90100000\0"                 \
 332         "kernel_addr=0x100000\0"                \
 333         "kernel_addr_sd=0x800\0"                \
 334         "ramdisk_addr=0x800000\0"               \
 335         "ramdisk_size=0x2000000\0"              \
 336         "fdt_high=0xa0000000\0"                 \
 337         "initrd_high=0xffffffffffffffff\0"      \
 338         "kernel_start=0x1000000\0"              \
 339         "kernel_start_sd=0x8000\0"              \
 340         "kernel_load=0xa0000000\0"              \
 341         "kernel_size=0x2800000\0"               \
 342         "kernel_size_sd=0x14000\0"               \
 343         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 344         "sf read 0x80e00000 0xE00000 0x100000;" \
 345         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 346         "mcmemsize=0x70000000 \0"               \
 347         "BOARD=ls1088aqds\0" \
 348         "scriptaddr=0x80000000\0"               \
 349         "scripthdraddr=0x80080000\0"            \
 350         BOOTENV                                 \
 351         "boot_scripts=ls1088aqds_boot.scr\0"    \
 352         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 353         "scan_dev_for_boot_part="               \
 354                 "part list ${devtype} ${devnum} devplist; "     \
 355                 "env exists devplist || setenv devplist 1; "    \
 356                 "for distro_bootpart in ${devplist}; do "       \
 357                         "if fstype ${devtype} "                 \
 358                                 "${devnum}:${distro_bootpart} " \
 359                                 "bootfstype; then "             \
 360                                 "run scan_dev_for_boot; "       \
 361                         "fi; "                                  \
 362                 "done\0"                                        \
 363         "boot_a_script="                                        \
 364                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 365                 "${scriptaddr} ${prefix}${script}; "            \
 366         "env exists secureboot && load ${devtype} "             \
 367                 "${devnum}:${distro_bootpart} "                 \
 368                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 369                 "env exists secureboot "                        \
 370                 "&& esbc_validate ${scripthdraddr};"            \
 371                 "source ${scriptaddr}\0"                        \
 372         "qspi_bootcmd=echo Trying load from qspi..; " \
 373                 "sf probe 0:0; " \
 374                 "sf read 0x80001000 0xd00000 0x100000; " \
 375                 "fsl_mc lazyapply dpl 0x80001000 && " \
 376                 "sf read $kernel_load $kernel_start " \
 377                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 378         "sd_bootcmd=echo Trying load from sd card..; " \
 379                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 380                 "fsl_mc lazyapply dpl 0x80001000 && " \
 381                 "mmc read $kernel_load $kernel_start_sd " \
 382                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 383         "nor_bootcmd=echo Trying load from nor..; " \
 384                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 385                 "cp.b $kernel_start $kernel_load " \
 386                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 387 #else
 388 #if defined(CONFIG_QSPI_BOOT)
 389 #undef CFG_EXTRA_ENV_SETTINGS
 390 #define CFG_EXTRA_ENV_SETTINGS          \
 391         COMMON_ENV                              \
 392         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 393         "loadaddr=0x90100000\0"                 \
 394         "kernel_addr=0x100000\0"                \
 395         "ramdisk_addr=0x800000\0"               \
 396         "ramdisk_size=0x2000000\0"              \
 397         "fdt_high=0xa0000000\0"                 \
 398         "initrd_high=0xffffffffffffffff\0"      \
 399         "kernel_start=0x1000000\0"              \
 400         "kernel_load=0xa0000000\0"              \
 401         "kernel_size=0x2800000\0"               \
 402         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 403         "sf read 0x80e00000 0xE00000 0x100000;" \
 404         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 405         "mcmemsize=0x70000000 \0"
 406 #elif defined(CONFIG_SD_BOOT)
 407 #undef CFG_EXTRA_ENV_SETTINGS
 408 #define CFG_EXTRA_ENV_SETTINGS               \
 409         COMMON_ENV                              \
 410         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 411         "loadaddr=0x90100000\0"                 \
 412         "kernel_addr=0x800\0"                \
 413         "ramdisk_addr=0x800000\0"               \
 414         "ramdisk_size=0x2000000\0"              \
 415         "fdt_high=0xa0000000\0"                 \
 416         "initrd_high=0xffffffffffffffff\0"      \
 417         "kernel_start=0x8000\0"              \
 418         "kernel_load=0xa0000000\0"              \
 419         "kernel_size=0x14000\0"               \
 420         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 421         "mmc read 0x80e00000 0x7000 0x800;" \
 422         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 423         "mcmemsize=0x70000000 \0"
 424 #else   /* NOR BOOT */
 425 #undef CFG_EXTRA_ENV_SETTINGS
 426 #define CFG_EXTRA_ENV_SETTINGS          \
 427         COMMON_ENV                              \
 428         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 429         "loadaddr=0x90100000\0"                 \
 430         "kernel_addr=0x100000\0"                \
 431         "ramdisk_addr=0x800000\0"               \
 432         "ramdisk_size=0x2000000\0"              \
 433         "fdt_high=0xa0000000\0"                 \
 434         "initrd_high=0xffffffffffffffff\0"      \
 435         "kernel_start=0x1000000\0"              \
 436         "kernel_load=0xa0000000\0"              \
 437         "kernel_size=0x2800000\0"               \
 438         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 439         "mcmemsize=0x70000000 \0"
 440 #endif
 441 #endif /* CONFIG_TFABOOT */
 442 #endif /* CONFIG_NXP_ESBC */
 443
 444 #ifdef CONFIG_TFABOOT
 445 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 446                            "env exists secureboot && esbc_halt;;"
 447 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 448                            "env exists secureboot && esbc_halt;;"
 449 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 450                            "env exists secureboot && esbc_halt;;"
 451 #endif
 452
 453 #ifdef CONFIG_FSL_MC_ENET
 454 #define RGMII_PHY1_ADDR         0x1
 455 #define RGMII_PHY2_ADDR         0x2
 456 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 457 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 458 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 459 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 460
 461 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 462 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 463 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 464 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 465 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 466 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 467 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 468 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 469 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 470 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 471 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 472 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 473 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 474 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 475 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 476 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 477
 478 #endif
 479
 480 #define BOOT_TARGET_DEVICES(func) \
 481         func(USB, usb, 0) \
 482         func(MMC, mmc, 0) \
 483         func(SCSI, scsi, 0) \
 484         func(DHCP, dhcp, na)
 485 #include <config_distro_bootcmd.h>
 486
 487 #include <asm/fsl_secure_boot.h>
 488
 489 #endif /* __LS1088A_QDS_H */