include/configs/turris_1x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* (C) 2022 Pali Rohár <pali@kernel.org> */
   3
   4 #ifndef _CONFIG_TURRIS_1X_H
   5 #define _CONFIG_TURRIS_1X_H
   6
   7 #include <linux/sizes.h>
   8
   9 /*
  10  * Turris 1.x memory map:
  11  *
  12  * 0x0000_0000 - 0x7fff_ffff    2 GB  DDR                 cacheable
  13  * 0x8000_0000 - 0xbfff_ffff    1 GB  PCIe MEM (bus 1-2)  non-cacheable
  14  * 0xc000_0000 - 0xc01f_ffff    2 MB  PCIe MEM (bus 3)    non-cacheable
  15  * 0xc020_0000 - 0xeeff_ffff  750 MB  unused
  16  * 0xef00_0000 - 0xefff_ffff   16 MB  NOR (CS0)           non-cacheable
  17  * 0xf000_0000 - 0xf8f7_ffff  143 MB  unused
  18  * 0xf8f8_0000 - 0xf8ff_ffff  512 kB  L2 SRAM             cacheable (early boot, SD card only)
  19  * 0xf900_0000 - 0xff6f_ffff  103 MB  unused
  20  * 0xff70_0000 - 0xff7f_ffff    1 MB  CCSR                non-cacheable (SPL only)
  21  * 0xff80_0000 - 0xff83_ffff  256 kB  NAND (CS1)          non-cacheable
  22  * 0xffa0_0000 - 0xffa1_ffff  128 kB  CPLD (CS3)          non-cacheable
  23  * 0xffc0_0000 - 0xffc2_ffff  192 kB  PCIe IO             non-cacheable
  24  * 0xffd0_0000 - 0xffd0_3fff   16 kB  L1 stack            cacheable (early boot)
  25  * 0xffe0_0000 - 0xffef_ffff    1 MB  CCSR                non-cacheable (not in SPL)
  26  * 0xffff_f000 - 0xffff_ffff    4 kB  Boot page           non-cacheable
  27  */
  28
  29 /*
  30  * Global settings
  31  */
  32
  33 /*
  34  * CONFIG_ENABLE_36BIT_PHYS needs to be always defined when processor supports
  35  * 36-bit addressing (which is case for P2020), also when only 32-bit addressing
  36  * mode is used. Name of this config option is misleading and should have been
  37  * called SUPPORT instead of ENABLE.
  38  * When CONFIG_PHYS_64BIT is set then 36-bit addressing is used, when unset then
  39  * 32-bit addressing is used. Name of this config option is misleading too and
  40  * should have been called 36BIT and ENABLED, not 64BIT.
  41  * Due to performance reasons (see document AN4064), Turris 1.x boards use only
  42  * 32-bit addressing. Also all config options are currently defined only for
  43  * 32-bit addressing, so compiling U-Boot for 36-bit addressing is not possible
  44  * yet.
  45  */
  46 #ifdef CONFIG_PHYS_64BIT
  47 #error "36-bit addressing is not implemented for this board"
  48 #endif
  49
  50 /*
  51  * Boot settings
  52  */
  53
  54 /*
  55  * Booting from SD card
  56  * BootROM configures L2 cache as SRAM, loads image from SD card into L2 SRAM
  57  * and starts executing directly _start entry point in L2 SRAM. Therefore reset
  58  * vector is not used and maximal size of the image is L2 cache size. For builds
  59  * with SPL there is no limit of U-Boot proper as BootROM loads SPL which then
  60  * loads U-Boot proper directly into DDR.
  61  */
  62
  63 /*
  64  * For SD card builds without SPL it is needed to set CONFIG_SYS_RAMBOOT
  65  *
  66  * if CONFIG_XPL_BUILD
  67  *     if CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
  68  *         define CONFIG_SPL_MAX_SIZE = (CONFIG_SYS_L2_SIZE+CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
  69  *                                      * SZ_512)
  70  *     else
  71  *         define CONFIG_SPL_MAX_SIZE = CONFIG_SYS_L2_SIZE
  72  */
  73
  74 #ifdef CONFIG_SDCARD
  75 #define CFG_SYS_MMC_U_BOOT_SIZE CONFIG_BOARD_SIZE_LIMIT
  76 #define CFG_SYS_MMC_U_BOOT_DST  CONFIG_TEXT_BASE
  77 #define CFG_SYS_MMC_U_BOOT_START        CONFIG_TEXT_BASE
  78 #endif
  79
  80 /*
  81  * Booting from NOR
  82  * Last 4kB page of the NOR is mapped into CPU address space and CPU starts
  83  * executing last instruction of that page, which is reset vector address.
  84  * We have 16 MB large NOR memory, so define correct reset vector address.
  85  *
  86  * CONFIG_RESET_VECTOR_ADDRESS = (CONFIG_SYS_FLASH_BASE + SZ_16M - 4)
  87  */
  88
  89 /*
  90  * CONFIG_BOARD_SIZE_LIMIT must be hex number because it is used in Makefile.
  91  * For NOR build, size of the U-Boot binary must always be 768 kB.
  92  * For SD card build with SPL, there is no limit, just broken build system which
  93  * cannot fill CFG_SYS_MMC_U_BOOT_SIZE and CONFIG_SYS_MONITOR_LEN values
  94  * automatically. So choose it as lowest value as possible with which build
  95  * process does not fail, to minimize final binary size.
  96  * For SD card build without SPL, there is upper limit of L2 cache size.
  97  *
  98  * if SDCARD
  99  *     CONFIG_BOARD_SIZE_LIMIT = 0x000c0000 // 768 kB
 100  * elif SPL
 101  *     CONFIG_BOARD_SIZE_LIMIT = 0x00100000 // 1 MB
 102  * else
 103  *     CONFIG_BOARD_SIZE_LIMIT = 0x00080000 // 512 kB - must be same as CONFIG_SYS_L2_SIZE
 104  */
 105
 106 /*
 107  * Initial stack in L1 cache
 108  */
 109
 110 #define CFG_SYS_INIT_RAM_ADDR                   0xffd00000
 111 #define CFG_SYS_INIT_RAM_ADDR_PHYS              CFG_SYS_INIT_RAM_ADDR
 112 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 113 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW          CFG_SYS_INIT_RAM_ADDR_PHYS
 114 #define CFG_SYS_INIT_RAM_SIZE                   SZ_16K
 115
 116 #define CFG_SYS_GBL_DATA_OFFSET                 (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 117 #define CFG_SYS_INIT_SP_OFFSET                  CFG_SYS_GBL_DATA_OFFSET
 118
 119 /*
 120  * Initial SRAM in L2 cache
 121  */
 122
 123 /* Initial SRAM is used only for SD card boot in first stage image */
 124 #if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)
 125 #define CFG_SYS_INIT_L2_ADDR            0xf8f80000
 126 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 127 /*
 128  * CONFIG_SPL_RELOC_TEXT_BASE =     CONFIG_SYS_MONITOR_BASE
 129  * CONFIG_SPL_GD_ADDR =             (CFG_SYS_INIT_L2_ADDR + 112 * SZ_1K)
 130  * CONFIG_SPL_RELOC_STACK =         (CFG_SYS_INIT_L2_ADDR + 116 * SZ_1K)
 131  * CONFIG_SPL_RELOC_MALLOC_ADDR =   (CFG_SYS_INIT_L2_ADDR + 148 * SZ_1K)
 132  * CONFIG_SPL_RELOC_MALLOC_SIZE =   (364 * SZ_1K)
 133  */
 134 #endif
 135
 136 /*
 137  * CCSR
 138  */
 139
 140 #define CFG_SYS_CCSRBAR                         0xffe00000
 141 #define CFG_SYS_CCSRBAR_PHYS_LOW                CFG_SYS_CCSRBAR
 142 /*
 143  * CFG_SYS_CCSRBAR_PHYS_HIGH =  0x0
 144  */
 145
 146 /*
 147  * U-Boot _start code expects that if CCSRBAR is configured to its default
 148  * location and automatically relocate it to the new CONFIG_SYS_CCSRBAR_PHYS
 149  * location. Relocation to the new location can be skipped by defining macro
 150  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.
 151  *
 152  * All addresses in device tree are set to according the new relocated CCSRBAR.
 153  * So device tree code cannot be used when CONFIG_SYS_CCSR_DO_NOT_RELOCATE is
 154  * set.
 155  *
 156  * If CCSRBAR is not configured to its default location then _start code hangs
 157  * or crashes.
 158  *
 159  * So relocation of CCSRBAR must be disabled in every code which runs before
 160  * U-Boot proper (e.g. SPL), otherwise U-Boot proper's _start code crashes.
 161  */
 162
 163 /*
 164  * DDR
 165  */
 166
 167 #define CFG_SYS_DDR_SDRAM_BASE                  0x00000000
 168 #define CFG_SYS_SDRAM_BASE                              CFG_SYS_DDR_SDRAM_BASE
 169
 170 #define CFG_SYS_I2C_PCA9557_ADDR        0x18
 171 #define SPD_EEPROM_ADDRESS              0x52
 172
 173 /*
 174  * NOR
 175  */
 176
 177 #define CFG_SYS_FLASH_BASE              0xef000000
 178 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
 179 #define CFG_RESET_VECTOR_ADDRESS        (CFG_SYS_FLASH_BASE + SZ_16M - 4)
 180
 181 /*
 182  * CONFIG_SYS_BR0_PRELIM = (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_MS_GPCM | BR_V)
 183  * CONFIG_SYS_OR0_PRELIM = (OR_AM_16MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS
 184  *                         | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 185  */
 186
 187 /*
 188  * NAND
 189  */
 190
 191 #define CFG_SYS_NAND_BASE               0xff800000
 192 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
 193
 194 /*
 195  * CONFIG_SYS_BR1_PRELIM = BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) | BR_PS_8 | BR_MS_FCM | BR_V)
 196  * CONFIG_SYS_OR1_PRELIM = (OR_AM_256KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT
 197  *                         | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
 198  */
 199
 200 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 201 #define CFG_SYS_NAND_OR_PRELIM  CONFIG_SYS_OR1_PRELIM
 202
 203 /*
 204  * CPLD
 205  */
 206
 207 #define CFG_SYS_CPLD_BASE               0xffa00000
 208 #define CFG_SYS_CPLD_BASE_PHYS  CFG_SYS_CPLD_BASE
 209
 210 /*
 211  * CONFIG_SYS_BR3_PRELIM = (BR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) | BR_PS_8 | BR_MS_GPCM | BR_V)
 212  * CONFIG_SYS_OR3_PRELIM = (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15
 213  *                         | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 214  */
 215
 216 /*
 217  * Serial Port
 218  */
 219
 220 #if !CONFIG_IS_ENABLED(DM_SERIAL)
 221 #define CFG_SYS_NS16550_CLK                     get_bus_freq(0)
 222 #define CFG_SYS_NS16550_COM1            (CFG_SYS_CCSRBAR + 0x4500)
 223 #define CFG_SYS_NS16550_COM2            (CFG_SYS_CCSRBAR + 0x4600)
 224 #endif
 225
 226 /*
 227  * PCIe
 228  */
 229
 230 /* PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card */
 231 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 232 #define CFG_SYS_PCIE1_IO_VIRT   0xffc00000
 233 #define CFG_SYS_PCIE1_MEM_PHYS  CFG_SYS_PCIE1_MEM_VIRT
 234 #define CFG_SYS_PCIE1_IO_PHYS   CFG_SYS_PCIE1_IO_VIRT
 235
 236 /* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
 237 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 238 #define CFG_SYS_PCIE2_IO_VIRT   0xffc10000
 239 #define CFG_SYS_PCIE2_MEM_PHYS  CFG_SYS_PCIE2_MEM_VIRT
 240 #define CFG_SYS_PCIE2_IO_PHYS   CFG_SYS_PCIE2_IO_VIRT
 241
 242 /* PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller */
 243 #define CFG_SYS_PCIE3_MEM_VIRT  0xc0000000
 244 #define CFG_SYS_PCIE3_IO_VIRT   0xffc20000
 245 #define CFG_SYS_PCIE3_MEM_PHYS  CFG_SYS_PCIE3_MEM_VIRT
 246 #define CFG_SYS_PCIE3_IO_PHYS   CFG_SYS_PCIE3_IO_VIRT
 247
 248 /*
 249  * eSDHC
 250  */
 251
 252 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 253 #define SDHC_WP_IS_GPIO         /* SDHC_WP pin is not connected to SD card slot, it is GPIO pin */
 254
 255 /*
 256  * For booting Linux, the board info and command line data
 257  * have to be in the first 64 MB of memory, since this is
 258  * the maximum mapped by the Linux kernel during initialization.
 259  */
 260 #define CFG_SYS_BOOTMAPSZ               SZ_64M /* Initial Memory for Linux */
 261
 262 /*
 263  * Environment Configuration
 264  */
 265
 266 #ifdef CONFIG_SDCARD
 267 #define BOOT_TARGET_DEVICES(func) \
 268         func(MMC, mmc, 0) \
 269         func(NVME, nvme, 0) \
 270         func(SCSI, scsi, 0) \
 271         func(USB, usb, 0) \
 272         func(USB, usb, 1) \
 273         func(USB, usb, 2) \
 274         func(USB, usb, 3) \
 275         func(USB, usb, 4) \
 276         func(UBIFS, ubifs, 0, rootfs, rootfs, 512) \
 277         func(UBIFS, ubifs, 1, rootfs, rootfs, 2048) \
 278         func(DHCP, dhcp, na)
 279 #else
 280 #define BOOT_TARGET_DEVICES(func) \
 281         func(MMC, mmc, 0) \
 282         func(NVME, nvme, 0) \
 283         func(SCSI, scsi, 0) \
 284         func(USB, usb, 0) \
 285         func(USB, usb, 1) \
 286         func(USB, usb, 2) \
 287         func(USB, usb, 3) \
 288         func(USB, usb, 4) \
 289         func(DHCP, dhcp, na)
 290 #endif
 291
 292 #include <config_distro_bootcmd.h>
 293
 294 /* These boot source switches macros must be constant numbers as they are stringified */
 295 #define __SW_BOOT_MASK                  0x03
 296 #define __SW_BOOT_NOR                   0xc8
 297 #define __SW_BOOT_SPI                   0x28
 298 #define __SW_BOOT_SD                    0x68
 299 #define __SW_BOOT_SD2                   0x18
 300 #define __SW_BOOT_NAND                  0xe8
 301 #define __SW_BOOT_PCIE                  0xa8
 302 #define __SW_NOR_BANK_MASK              0xfd
 303 #define __SW_NOR_BANK_UP                0x00
 304 #define __SW_NOR_BANK_LO                0x02
 305 #define __SW_BOOT_NOR_BANK_UP           0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
 306 #define __SW_BOOT_NOR_BANK_LO           0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
 307 #define __SW_BOOT_NOR_BANK_MASK         0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
 308
 309 #include "p1_p2_bootsrc.h"
 310
 311 #define REBOOT_ENV_SETTINGS \
 312         RST_NOR_UP_CMD(reboot_to_nor, echo Rebooting to NOR bootloader;) \
 313         RST_SD_CMD(reboot_to_sd, echo Rebooting to SD bootloader;) \
 314         RST_DEF_CMD(reboot_to_def, echo Rebooting to default bootloader;) \
 315         ""
 316
 317 #define BOOTCMD_RESCUE \
 318         "setenv bootargs root=mtd2 ro rootfstype=jffs2 console=ttyS0,115200; " \
 319         "mw.b 0xffa00002 0x03; " \
 320         "bootm 0xef020000 - 0xef000000" \
 321         ""
 322
 323 #define CFG_EXTRA_ENV_SETTINGS \
 324         "fdt_addr_r=0x2000000\0" \
 325         "kernel_addr_r=0x2100000\0" \
 326         "scriptaddr=0x3000000\0" \
 327         "pxefile_addr_r=0x3100000\0" \
 328         "ramdisk_addr_r=0x4000000\0" \
 329         "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 330         "fdt_addr=0xef000000\0" \
 331         "bootcmd_rescue=" BOOTCMD_RESCUE "\0" \
 332         REBOOT_ENV_SETTINGS \
 333         BOOTENV
 334
 335 #endif /* _CONFIG_TURRIS_1X_H */