include/sdhci.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9 #ifndef __SDHCI_HW_H
  10 #define __SDHCI_HW_H
  11
  12 #include <linux/bitops.h>
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <asm/io.h>
  16 #include <mmc.h>
  17 #include <asm/gpio.h>
  18
  19 /*
  20  * Controller registers
  21  */
  22
  23 #define SDHCI_DMA_ADDRESS       0x00
  24
  25 #define SDHCI_BLOCK_SIZE        0x04
  26 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  27
  28 #define SDHCI_BLOCK_COUNT       0x06
  29
  30 #define SDHCI_ARGUMENT          0x08
  31
  32 #define SDHCI_TRANSFER_MODE     0x0C
  33 #define  SDHCI_TRNS_DMA         BIT(0)
  34 #define  SDHCI_TRNS_BLK_CNT_EN  BIT(1)
  35 #define  SDHCI_TRNS_ACMD12      BIT(2)
  36 #define  SDHCI_TRNS_READ        BIT(4)
  37 #define  SDHCI_TRNS_MULTI       BIT(5)
  38
  39 #define SDHCI_COMMAND           0x0E
  40 #define  SDHCI_CMD_RESP_MASK    0x03
  41 #define  SDHCI_CMD_CRC          0x08
  42 #define  SDHCI_CMD_INDEX        0x10
  43 #define  SDHCI_CMD_DATA         0x20
  44 #define  SDHCI_CMD_ABORTCMD     0xC0
  45
  46 #define  SDHCI_CMD_RESP_NONE    0x00
  47 #define  SDHCI_CMD_RESP_LONG    0x01
  48 #define  SDHCI_CMD_RESP_SHORT   0x02
  49 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  50
  51 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  52 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  53
  54 #define SDHCI_RESPONSE          0x10
  55
  56 #define SDHCI_BUFFER            0x20
  57
  58 #define SDHCI_PRESENT_STATE     0x24
  59 #define  SDHCI_CMD_INHIBIT      BIT(0)
  60 #define  SDHCI_DATA_INHIBIT     BIT(1)
  61 #define  SDHCI_DAT_ACTIVE       BIT(2)
  62 #define  SDHCI_DOING_WRITE      BIT(8)
  63 #define  SDHCI_DOING_READ       BIT(9)
  64 #define  SDHCI_SPACE_AVAILABLE  BIT(10)
  65 #define  SDHCI_DATA_AVAILABLE   BIT(11)
  66 #define  SDHCI_CARD_PRESENT     BIT(16)
  67 #define  SDHCI_CARD_STATE_STABLE        BIT(17)
  68 #define  SDHCI_CARD_DETECT_PIN_LEVEL    BIT(18)
  69 #define  SDHCI_WRITE_PROTECT    BIT(19)
  70 #define  SDHCI_DATA_LVL_MASK    0x00F00000
  71 #define   SDHCI_DATA_0_LVL_MASK BIT(20)
  72
  73 #define SDHCI_HOST_CONTROL      0x28
  74 #define  SDHCI_CTRL_LED         BIT(0)
  75 #define  SDHCI_CTRL_4BITBUS     BIT(1)
  76 #define  SDHCI_CTRL_HISPD       BIT(2)
  77 #define  SDHCI_CTRL_DMA_MASK    0x18
  78 #define   SDHCI_CTRL_SDMA       0x00
  79 #define   SDHCI_CTRL_ADMA1      0x08
  80 #define   SDHCI_CTRL_ADMA32     0x10
  81 #define   SDHCI_CTRL_ADMA64     0x18
  82 #define  SDHCI_CTRL_8BITBUS     BIT(5)
  83 #define  SDHCI_CTRL_CD_TEST_INS BIT(6)
  84 #define  SDHCI_CTRL_CD_TEST     BIT(7)
  85
  86 #define SDHCI_POWER_CONTROL     0x29
  87 #define  SDHCI_POWER_ON         0x01
  88 #define  SDHCI_POWER_180        0x0A
  89 #define  SDHCI_POWER_300        0x0C
  90 #define  SDHCI_POWER_330        0x0E
  91
  92 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  93
  94 #define SDHCI_WAKE_UP_CONTROL   0x2B
  95 #define  SDHCI_WAKE_ON_INT      BIT(0)
  96 #define  SDHCI_WAKE_ON_INSERT   BIT(1)
  97 #define  SDHCI_WAKE_ON_REMOVE   BIT(2)
  98
  99 #define SDHCI_CLOCK_CONTROL     0x2C
 100 #define  SDHCI_DIVIDER_SHIFT    8
 101 #define  SDHCI_DIVIDER_HI_SHIFT 6
 102 #define  SDHCI_DIV_MASK 0xFF
 103 #define  SDHCI_DIV_MASK_LEN     8
 104 #define  SDHCI_DIV_HI_MASK      0x300
 105 #define  SDHCI_PROG_CLOCK_MODE  BIT(5)
 106 #define  SDHCI_CLOCK_CARD_EN    BIT(2)
 107 #define  SDHCI_CLOCK_INT_STABLE BIT(1)
 108 #define  SDHCI_CLOCK_INT_EN     BIT(0)
 109
 110 #define SDHCI_TIMEOUT_CONTROL   0x2E
 111
 112 #define SDHCI_SOFTWARE_RESET    0x2F
 113 #define  SDHCI_RESET_ALL        0x01
 114 #define  SDHCI_RESET_CMD        0x02
 115 #define  SDHCI_RESET_DATA       0x04
 116
 117 #define SDHCI_INT_STATUS        0x30
 118 #define SDHCI_INT_ENABLE        0x34
 119 #define SDHCI_SIGNAL_ENABLE     0x38
 120 #define  SDHCI_INT_RESPONSE     BIT(0)
 121 #define  SDHCI_INT_DATA_END     BIT(1)
 122 #define  SDHCI_INT_DMA_END      BIT(3)
 123 #define  SDHCI_INT_SPACE_AVAIL  BIT(4)
 124 #define  SDHCI_INT_DATA_AVAIL   BIT(5)
 125 #define  SDHCI_INT_CARD_INSERT  BIT(6)
 126 #define  SDHCI_INT_CARD_REMOVE  BIT(7)
 127 #define  SDHCI_INT_CARD_INT     BIT(8)
 128 #define  SDHCI_INT_ERROR        BIT(15)
 129 #define  SDHCI_INT_TIMEOUT      BIT(16)
 130 #define  SDHCI_INT_CRC          BIT(17)
 131 #define  SDHCI_INT_END_BIT      BIT(18)
 132 #define  SDHCI_INT_INDEX        BIT(19)
 133 #define  SDHCI_INT_DATA_TIMEOUT BIT(20)
 134 #define  SDHCI_INT_DATA_CRC     BIT(21)
 135 #define  SDHCI_INT_DATA_END_BIT BIT(22)
 136 #define  SDHCI_INT_BUS_POWER    BIT(23)
 137 #define  SDHCI_INT_ACMD12ERR    BIT(24)
 138 #define  SDHCI_INT_ADMA_ERROR   BIT(25)
 139
 140 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 141 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 142
 143 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 144                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 145 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 146                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 147                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 148                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
 149 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 150
 151 #define SDHCI_ACMD12_ERR        0x3C
 152
 153 #define SDHCI_HOST_CONTROL2     0x3E
 154 #define  SDHCI_CTRL_UHS_MASK    0x0007
 155 #define  SDHCI_CTRL_UHS_SDR12   0x0000
 156 #define  SDHCI_CTRL_UHS_SDR25   0x0001
 157 #define  SDHCI_CTRL_UHS_SDR50   0x0002
 158 #define  SDHCI_CTRL_UHS_SDR104  0x0003
 159 #define  SDHCI_CTRL_UHS_DDR50   0x0004
 160 #define  SDHCI_CTRL_HS400       0x0005 /* Non-standard */
 161 #define  SDHCI_CTRL_VDD_180     0x0008
 162 #define  SDHCI_CTRL_DRV_TYPE_MASK       0x0030
 163 #define  SDHCI_CTRL_DRV_TYPE_B  0x0000
 164 #define  SDHCI_CTRL_DRV_TYPE_A  0x0010
 165 #define  SDHCI_CTRL_DRV_TYPE_C  0x0020
 166 #define  SDHCI_CTRL_DRV_TYPE_D  0x0030
 167 #define  SDHCI_CTRL_EXEC_TUNING 0x0040
 168 #define  SDHCI_CTRL_TUNED_CLK   0x0080
 169 #define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
 170
 171 #define SDHCI_CAPABILITIES      0x40
 172 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 173 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 174 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 175 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 176 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 177 #define  SDHCI_CLOCK_BASE_SHIFT 8
 178 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 179 #define  SDHCI_MAX_BLOCK_SHIFT  16
 180 #define  SDHCI_CAN_DO_8BIT      BIT(18)
 181 #define  SDHCI_CAN_DO_ADMA2     BIT(19)
 182 #define  SDHCI_CAN_DO_ADMA1     BIT(20)
 183 #define  SDHCI_CAN_DO_HISPD     BIT(21)
 184 #define  SDHCI_CAN_DO_SDMA      BIT(22)
 185 #define  SDHCI_CAN_VDD_330      BIT(24)
 186 #define  SDHCI_CAN_VDD_300      BIT(25)
 187 #define  SDHCI_CAN_VDD_180      BIT(26)
 188 #define  SDHCI_CAN_64BIT        BIT(28)
 189
 190 #define SDHCI_CAPABILITIES_1    0x44
 191 #define  SDHCI_SUPPORT_SDR50    0x00000001
 192 #define  SDHCI_SUPPORT_SDR104   0x00000002
 193 #define  SDHCI_SUPPORT_DDR50    0x00000004
 194 #define  SDHCI_SUPPORT_HS400    BIT(31)
 195 #define  SDHCI_USE_SDR50_TUNING 0x00002000
 196
 197 #define  SDHCI_CLOCK_MUL_MASK   0x00FF0000
 198 #define  SDHCI_CLOCK_MUL_SHIFT  16
 199
 200 #define SDHCI_MAX_CURRENT       0x48
 201
 202 /* 4C-4F reserved for more max current */
 203
 204 #define SDHCI_SET_ACMD12_ERROR  0x50
 205 #define SDHCI_SET_INT_ERROR     0x52
 206
 207 #define SDHCI_ADMA_ERROR        0x54
 208
 209 /* 55-57 reserved */
 210
 211 #define SDHCI_ADMA_ADDRESS      0x58
 212 #define SDHCI_ADMA_ADDRESS_HI   0x5c
 213
 214 /* 60-FB reserved */
 215
 216 #define SDHCI_SLOT_INT_STATUS   0xFC
 217
 218 #define SDHCI_HOST_VERSION      0xFE
 219 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 220 #define  SDHCI_VENDOR_VER_SHIFT 8
 221 #define  SDHCI_SPEC_VER_MASK    0x00FF
 222 #define  SDHCI_SPEC_VER_SHIFT   0
 223 #define   SDHCI_SPEC_100        0
 224 #define   SDHCI_SPEC_200        1
 225 #define   SDHCI_SPEC_300        2
 226
 227 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
 228
 229 /*
 230  * End of controller registers.
 231  */
 232
 233 #define SDHCI_MAX_DIV_SPEC_200  256
 234 #define SDHCI_MAX_DIV_SPEC_300  2046
 235
 236 /*
 237  * quirks
 238  */
 239 #define SDHCI_QUIRK_32BIT_DMA_ADDR      (1 << 0)
 240 #define SDHCI_QUIRK_REG32_RW            (1 << 1)
 241 #define SDHCI_QUIRK_BROKEN_R1B          (1 << 2)
 242 #define SDHCI_QUIRK_NO_HISPD_BIT        (1 << 3)
 243 #define SDHCI_QUIRK_BROKEN_VOLTAGE      (1 << 4)
 244 /*
 245  * SDHCI_QUIRK_BROKEN_HISPD_MODE
 246  * the hardware cannot operate correctly in high-speed mode,
 247  * this quirk forces the sdhci host-controller to non high-speed mode
 248  */
 249 #define SDHCI_QUIRK_BROKEN_HISPD_MODE   BIT(5)
 250 #define SDHCI_QUIRK_WAIT_SEND_CMD       (1 << 6)
 251 #define SDHCI_QUIRK_USE_WIDE8           (1 << 8)
 252 #define SDHCI_QUIRK_NO_1_8_V            (1 << 9)
 253 #define SDHCI_QUIRK_SUPPORT_SINGLE      (1 << 10)
 254 /* Capability register bit-63 indicates HS400 support */
 255 #define SDHCI_QUIRK_CAPS_BIT63_FOR_HS400        BIT(11)
 256
 257 /* to make gcc happy */
 258 struct sdhci_host;
 259
 260 /*
 261  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 262  */
 263 #define SDHCI_DEFAULT_BOUNDARY_SIZE     (512 * 1024)
 264 #define SDHCI_DEFAULT_BOUNDARY_ARG      (7)
 265 struct sdhci_ops {
 266 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 267         u32     (*read_l)(struct sdhci_host *host, int reg);
 268         u16     (*read_w)(struct sdhci_host *host, int reg);
 269         u8      (*read_b)(struct sdhci_host *host, int reg);
 270         void    (*write_l)(struct sdhci_host *host, u32 val, int reg);
 271         void    (*write_w)(struct sdhci_host *host, u16 val, int reg);
 272         void    (*write_b)(struct sdhci_host *host, u8 val, int reg);
 273 #endif
 274         int     (*get_cd)(struct sdhci_host *host);
 275         void    (*set_control_reg)(struct sdhci_host *host);
 276         int     (*set_ios_post)(struct sdhci_host *host);
 277         void    (*set_clock)(struct sdhci_host *host, u32 div);
 278         int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
 279         int (*set_delay)(struct sdhci_host *host);
 280         /* Callback function to set DLL clock configuration */
 281         int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
 282         int     (*deferred_probe)(struct sdhci_host *host);
 283
 284         /**
 285          * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
 286          *
 287          * This is called after setting the card speed and mode to
 288          * HS400 ES, and should set any host-specific configuration
 289          * necessary for it.
 290          *
 291          * @host: SDHCI host structure
 292          * Return: 0 if successful, -ve on error
 293          */
 294         int     (*set_enhanced_strobe)(struct sdhci_host *host);
 295
 296 #ifdef CONFIG_MMC_SDHCI_ADMA_HELPERS
 297         void    (*adma_write_desc)(struct sdhci_host *host, void **desc,
 298                                    dma_addr_t addr, int len, bool end);
 299 #endif
 300 };
 301
 302 #define ADMA_MAX_LEN    65532
 303 #ifdef CONFIG_MMC_SDHCI_ADMA_64BIT
 304 #define ADMA_DESC_LEN   12
 305 #else
 306 #define ADMA_DESC_LEN   8
 307 #endif
 308 #define ADMA_TABLE_NO_ENTRIES DIV_ROUND_UP(CONFIG_SYS_MMC_MAX_BLK_COUNT * \
 309                               MMC_MAX_BLOCK_LEN, ADMA_MAX_LEN)
 310
 311 #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
 312
 313 /* Decriptor table defines */
 314 #define ADMA_DESC_ATTR_VALID            BIT(0)
 315 #define ADMA_DESC_ATTR_END              BIT(1)
 316 #define ADMA_DESC_ATTR_INT              BIT(2)
 317 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 318 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 319
 320 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 321 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 322
 323 struct sdhci_adma_desc {
 324         u8 attr;
 325         u8 reserved;
 326         u16 len;
 327         u32 addr_lo;
 328 #ifdef CONFIG_MMC_SDHCI_ADMA_64BIT
 329         u32 addr_hi;
 330 #endif
 331 } __packed;
 332
 333 struct sdhci_host {
 334         const char *name;
 335         void *ioaddr;
 336         unsigned int quirks;
 337         unsigned int host_caps;
 338         unsigned int version;
 339         unsigned int max_clk;   /* Maximum Base Clock frequency */
 340         unsigned int clk_mul;   /* Clock Multiplier value */
 341         unsigned int clock;
 342         struct mmc *mmc;
 343         const struct sdhci_ops *ops;
 344         int index;
 345
 346         int bus_width;
 347         struct gpio_desc pwr_gpio;      /* Power GPIO */
 348         struct gpio_desc cd_gpio;               /* Card Detect GPIO */
 349
 350         uint    voltages;
 351
 352         struct mmc_config cfg;
 353         void *align_buffer;
 354         bool force_align_buffer;
 355         dma_addr_t start_addr;
 356         int flags;
 357 #define USE_SDMA        (0x1 << 0)
 358 #define USE_ADMA        (0x1 << 1)
 359 #define USE_ADMA64      (0x1 << 2)
 360 #define USE_DMA         (USE_SDMA | USE_ADMA | USE_ADMA64)
 361         dma_addr_t adma_addr;
 362 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 363         struct sdhci_adma_desc *adma_desc_table;
 364 #endif
 365 };
 366
 367 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 368
 369 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 370 {
 371         if (unlikely(host->ops->write_l))
 372                 host->ops->write_l(host, val, reg);
 373         else
 374                 writel(val, host->ioaddr + reg);
 375 }
 376
 377 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 378 {
 379         if (unlikely(host->ops->write_w))
 380                 host->ops->write_w(host, val, reg);
 381         else
 382                 writew(val, host->ioaddr + reg);
 383 }
 384
 385 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 386 {
 387         if (unlikely(host->ops->write_b))
 388                 host->ops->write_b(host, val, reg);
 389         else
 390                 writeb(val, host->ioaddr + reg);
 391 }
 392
 393 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 394 {
 395         if (unlikely(host->ops->read_l))
 396                 return host->ops->read_l(host, reg);
 397         else
 398                 return readl(host->ioaddr + reg);
 399 }
 400
 401 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 402 {
 403         if (unlikely(host->ops->read_w))
 404                 return host->ops->read_w(host, reg);
 405         else
 406                 return readw(host->ioaddr + reg);
 407 }
 408
 409 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 410 {
 411         if (unlikely(host->ops->read_b))
 412                 return host->ops->read_b(host, reg);
 413         else
 414                 return readb(host->ioaddr + reg);
 415 }
 416
 417 #else
 418
 419 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 420 {
 421         writel(val, host->ioaddr + reg);
 422 }
 423
 424 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 425 {
 426         writew(val, host->ioaddr + reg);
 427 }
 428
 429 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 430 {
 431         writeb(val, host->ioaddr + reg);
 432 }
 433 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 434 {
 435         return readl(host->ioaddr + reg);
 436 }
 437
 438 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 439 {
 440         return readw(host->ioaddr + reg);
 441 }
 442
 443 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 444 {
 445         return readb(host->ioaddr + reg);
 446 }
 447 #endif
 448
 449 #ifdef CONFIG_BLK
 450 /**
 451  * sdhci_setup_cfg() - Set up the configuration for DWMMC
 452  *
 453  * This is used to set up an SDHCI device when you are using CONFIG_BLK.
 454  *
 455  * This should be called from your MMC driver's probe() method once you have
 456  * the information required.
 457  *
 458  * Generally your driver will have a platform data structure which holds both
 459  * the configuration (struct mmc_config) and the MMC device info (struct mmc).
 460  * For example:
 461  *
 462  * struct msm_sdhc_plat {
 463  *      struct mmc_config cfg;
 464  *      struct mmc mmc;
 465  * };
 466  *
 467  * ...
 468  *
 469  * Inside U_BOOT_DRIVER():
 470  *      .plat_auto      = sizeof(struct msm_sdhc_plat),
 471  *
 472  * To access platform data:
 473  *      struct msm_sdhc_plat *plat = dev_get_plat(dev);
 474  *
 475  * See msm_sdhci.c for an example.
 476  *
 477  * @cfg:        Configuration structure to fill in (generally &plat->mmc)
 478  * @host:       SDHCI host structure
 479  * @f_max:      Maximum supported clock frequency in HZ (0 for default)
 480  * @f_min:      Minimum supported clock frequency in HZ (0 for default)
 481  */
 482 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 483                     u32 f_max, u32 f_min);
 484
 485 /**
 486  * sdhci_bind() - Set up a new MMC block device
 487  *
 488  * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
 489  * It should be called from your driver's bind() method.
 490  *
 491  * See msm_sdhci.c for an example.
 492  *
 493  * @dev:        Device to set up
 494  * @mmc:        Pointer to mmc structure (normally &plat->mmc)
 495  * @cfg:        Empty configuration structure (generally &plat->cfg). This is
 496  *              normally all zeroes at this point. The only purpose of passing
 497  *              this in is to set mmc->cfg to it.
 498  * Return: 0 if OK, -ve if the block device could not be created
 499  */
 500 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
 501 #else
 502
 503 /**
 504  * add_sdhci() - Add a new SDHCI interface
 505  *
 506  * This is used when you are not using CONFIG_BLK. Convert your driver over!
 507  *
 508  * @host:       SDHCI host structure
 509  * @f_max:      Maximum supported clock frequency in HZ (0 for default)
 510  * @f_min:      Minimum supported clock frequency in HZ (0 for default)
 511  * Return: 0 if OK, -ve on error
 512  */
 513 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
 514 #endif /* !CONFIG_BLK */
 515
 516 void sdhci_set_uhs_timing(struct sdhci_host *host);
 517 #ifdef CONFIG_DM_MMC
 518 /* Export the operations to drivers */
 519 int sdhci_probe(struct udevice *dev);
 520 int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
 521
 522 /**
 523  * sdhci_set_control_reg - Set control registers
 524  *
 525  * This is used set up control registers for voltage level and UHS speed
 526  * mode.
 527  *
 528  * @host: SDHCI host structure
 529  */
 530 void sdhci_set_control_reg(struct sdhci_host *host);
 531 extern const struct dm_mmc_ops sdhci_ops;
 532 #else
 533 #endif
 534
 535 void sdhci_adma_write_desc(struct sdhci_host *host, void **next_desc,
 536                            dma_addr_t addr, int len, bool end);
 537 struct sdhci_adma_desc *sdhci_adma_init(void);
 538 void sdhci_prepare_adma_table(struct sdhci_host *host,
 539                               struct sdhci_adma_desc *table,
 540                               struct mmc_data *data, dma_addr_t start_addr);
 541
 542 #endif /* __SDHCI_HW_H */