include/sunxi_gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007-2012
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Tom Cubie <tangliang@allwinnertech.com>
   6  *
   7  * Definitions that are shared between the Allwinner pinctrl and GPIO drivers,
   8  * also used by some non-DM SPL code directly.
   9  */
  10
  11 #ifndef _SUNXI_GPIO_H
  12 #define _SUNXI_GPIO_H
  13
  14 #include <linux/types.h>
  15
  16 #if defined(CONFIG_MACH_SUN9I)
  17 #define SUNXI_PIO_BASE          0x06000800
  18 #define SUNXI_R_PIO_BASE        0x08002c00
  19 #elif defined(CONFIG_SUN50I_GEN_H6)
  20 #define SUNXI_PIO_BASE          0x0300b000
  21 #define SUNXI_R_PIO_BASE        0x07022000
  22 #elif defined(CONFIG_SUNXI_GEN_NCAT2)
  23 #define SUNXI_PIO_BASE          0x02000000
  24 #define SUNXI_R_PIO_BASE        0x07022000
  25 #else
  26 #define SUNXI_PIO_BASE          0x01c20800
  27 #define SUNXI_R_PIO_BASE        0x01f02c00
  28 #endif
  29
  30 /*
  31  * sunxi has 9 banks of gpio, they are:
  32  * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
  33  * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
  34  * PG0 - PG9  | PH0 - PH27 | PI0 - PI12
  35  */
  36
  37 #define SUNXI_GPIO_A    0
  38 #define SUNXI_GPIO_B    1
  39 #define SUNXI_GPIO_C    2
  40 #define SUNXI_GPIO_D    3
  41 #define SUNXI_GPIO_E    4
  42 #define SUNXI_GPIO_F    5
  43 #define SUNXI_GPIO_G    6
  44 #define SUNXI_GPIO_H    7
  45 #define SUNXI_GPIO_I    8
  46
  47 /*
  48  * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
  49  * at a different register offset.
  50  *
  51  * sun6i has 2 banks:
  52  * PL0 - PL8  | PM0 - PM7
  53  *
  54  * sun8i has 1 bank:
  55  * PL0 - PL11
  56  *
  57  * sun9i has 3 banks:
  58  * PL0 - PL9  | PM0 - PM15  | PN0 - PN1
  59  */
  60 #define SUNXI_GPIO_L    11
  61 #define SUNXI_GPIO_M    12
  62 #define SUNXI_GPIO_N    13
  63
  64 #define SUN50I_H6_GPIO_POW_MOD_SEL      0x340
  65 #define SUN50I_H6_GPIO_POW_MOD_VAL      0x348
  66
  67 #define SUNXI_GPIOS_PER_BANK    32
  68
  69 #define SUNXI_GPIO_NEXT(__gpio) \
  70         ((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
  71
  72 enum sunxi_gpio_number {
  73         SUNXI_GPIO_A_START = 0,
  74         SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
  75         SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
  76         SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
  77         SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
  78         SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
  79         SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
  80         SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
  81         SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
  82         SUNXI_GPIO_L_START = 352,
  83         SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
  84         SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
  85         SUNXI_GPIO_AXP0_START = 1024,
  86 };
  87
  88 /* SUNXI GPIO number definitions */
  89 #define SUNXI_GPA(_nr)  (SUNXI_GPIO_A_START + (_nr))
  90 #define SUNXI_GPB(_nr)  (SUNXI_GPIO_B_START + (_nr))
  91 #define SUNXI_GPC(_nr)  (SUNXI_GPIO_C_START + (_nr))
  92 #define SUNXI_GPD(_nr)  (SUNXI_GPIO_D_START + (_nr))
  93 #define SUNXI_GPE(_nr)  (SUNXI_GPIO_E_START + (_nr))
  94 #define SUNXI_GPF(_nr)  (SUNXI_GPIO_F_START + (_nr))
  95 #define SUNXI_GPG(_nr)  (SUNXI_GPIO_G_START + (_nr))
  96 #define SUNXI_GPH(_nr)  (SUNXI_GPIO_H_START + (_nr))
  97 #define SUNXI_GPI(_nr)  (SUNXI_GPIO_I_START + (_nr))
  98 #define SUNXI_GPL(_nr)  (SUNXI_GPIO_L_START + (_nr))
  99 #define SUNXI_GPM(_nr)  (SUNXI_GPIO_M_START + (_nr))
 100 #define SUNXI_GPN(_nr)  (SUNXI_GPIO_N_START + (_nr))
 101
 102 #define SUNXI_GPAXP0(_nr)       (SUNXI_GPIO_AXP0_START + (_nr))
 103
 104 /* GPIO pin function config */
 105 #define SUNXI_GPIO_INPUT        0
 106 #define SUNXI_GPIO_OUTPUT       1
 107
 108 #define SUN8I_H3_GPA_UART0      2
 109 #define SUN8I_H3_GPA_UART2      2
 110
 111 #define SUN4I_GPB_PWM           2
 112 #define SUN4I_GPB_TWI0          2
 113 #define SUN4I_GPB_TWI1          2
 114 #define SUN5I_GPB_TWI1          2
 115 #define SUN8I_V3S_GPB_TWI0      2
 116 #define SUN4I_GPB_UART0         2
 117 #define SUN5I_GPB_UART0         2
 118 #define SUN8I_GPB_UART2         2
 119 #define SUN8I_A33_GPB_UART0     3
 120 #define SUN8I_A83T_GPB_UART0    2
 121 #define SUN8I_V3S_GPB_UART0     3
 122 #define SUN50I_GPB_UART0        4
 123
 124 #define SUNXI_GPC_NAND          2
 125 #define SUNXI_GPC_SPI0          3
 126 #define SUNXI_GPC_SDC2          3
 127 #define SUN6I_GPC_SDC3          4
 128 #define SUN50I_GPC_SPI0         4
 129 #define SUNIV_GPC_SPI0          2
 130
 131 #define SUNXI_GPD_LCD0          2
 132 #define SUNXI_GPD_LVDS0         3
 133
 134 #define SUNIV_GPE_UART0         5
 135
 136 #define SUNXI_GPF_SDC0          2
 137 #define SUNXI_GPF_UART0         4
 138 #define SUN8I_GPF_UART0         3
 139
 140 #define SUN4I_GPG_SDC1          4
 141 #define SUN5I_GPG_SDC1          2
 142 #define SUN6I_GPG_SDC1          2
 143 #define SUN8I_GPG_SDC1          2
 144 #define SUN8I_GPG_UART1         2
 145 #define SUN5I_GPG_UART1         4
 146
 147 #define SUN6I_GPH_PWM           2
 148 #define SUN8I_GPH_PWM           2
 149 #define SUN4I_GPH_SDC1          5
 150 #define SUN6I_GPH_TWI0          2
 151 #define SUN8I_GPH_TWI0          2
 152 #define SUN50I_GPH_TWI0         2
 153 #define SUN6I_GPH_TWI1          2
 154 #define SUN8I_GPH_TWI1          2
 155 #define SUN50I_GPH_TWI1         2
 156 #define SUN6I_GPH_UART0         2
 157 #define SUN9I_GPH_UART0         2
 158 #define SUN50I_H6_GPH_UART0     2
 159 #define SUN50I_H616_GPH_UART0   2
 160
 161 #define SUNXI_GPI_SDC3          2
 162
 163 #define SUN6I_GPL0_R_P2WI_SCK   3
 164 #define SUN6I_GPL1_R_P2WI_SDA   3
 165
 166 #define SUN8I_GPL_R_RSB         2
 167 #define SUN8I_H3_GPL_R_TWI      2
 168 #define SUN8I_A23_GPL_R_TWI     3
 169 #define SUN8I_GPL_R_UART        2
 170 #define SUN50I_GPL_R_TWI        2
 171 #define SUN50I_H616_GPL_R_TWI   3
 172
 173 #define SUN9I_GPN_R_RSB         3
 174
 175 #ifdef CONFIG_SUNXI_NEW_PINCTRL
 176         #define SUNXI_PINCTRL_BANK_SIZE 0x30
 177         #define SUNXI_GPIO_DISABLE      0xf
 178 #else
 179         #define SUNXI_PINCTRL_BANK_SIZE 0x24
 180         #define SUNXI_GPIO_DISABLE      0x7
 181 #endif
 182
 183 /* GPIO pin pull-up/down config */
 184 #define SUNXI_GPIO_PULL_DISABLE 0
 185 #define SUNXI_GPIO_PULL_UP      1
 186 #define SUNXI_GPIO_PULL_DOWN    2
 187
 188 /* Virtual AXP0 GPIOs */
 189 #define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
 190 #define SUNXI_GPIO_AXP0_VBUS_ENABLE     5
 191 #define SUNXI_GPIO_AXP0_GPIO_COUNT      6
 192
 193 struct sunxi_gpio_plat {
 194         void                    *regs;
 195         char                    bank_name[3];
 196 };
 197
 198 /* prototypes for the non-DM GPIO/pinctrl functions, used in the SPL */
 199 void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val);
 200 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 201 int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset);
 202 int sunxi_gpio_get_cfgpin(u32 pin);
 203 void sunxi_gpio_set_drv(u32 pin, u32 val);
 204 void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val);
 205 void sunxi_gpio_set_pull(u32 pin, u32 val);
 206 void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val);
 207 int sunxi_name_to_gpio(const char *name);
 208
 209 #if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO
 210 int axp_gpio_init(void);
 211 #else
 212 static inline int axp_gpio_init(void) { return 0; }
 213 #endif
 214
 215 #endif /* _SUNXI_GPIO_H */