arm: vf610: fix double iomux configuration for vf610twr board
[u-boot/qq2440-u-boot.git] / drivers / i2c / davinci_i2c.c
blobe56fe75b15ce653730828fe7618b190fc092c53a
1 /*
2 * TI DaVinci (TMS320DM644x) I2C driver.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * --------------------------------------------------------
8 * SPDX-License-Identifier: GPL-2.0+
9 */
11 #include <common.h>
12 #include <i2c.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/i2c_defs.h>
16 #define CHECK_NACK() \
17 do {\
18 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
19 REG(I2C_CON) = 0;\
20 return(1);\
22 } while (0)
25 static int wait_for_bus(void)
27 int stat, timeout;
29 REG(I2C_STAT) = 0xffff;
31 for (timeout = 0; timeout < 10; timeout++) {
32 if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
33 REG(I2C_STAT) = 0xffff;
34 return(0);
37 REG(I2C_STAT) = stat;
38 udelay(50000);
41 REG(I2C_STAT) = 0xffff;
42 return(1);
46 static int poll_i2c_irq(int mask)
48 int stat, timeout;
50 for (timeout = 0; timeout < 10; timeout++) {
51 udelay(1000);
52 stat = REG(I2C_STAT);
53 if (stat & mask) {
54 return(stat);
58 REG(I2C_STAT) = 0xffff;
59 return(stat | I2C_TIMEOUT);
63 void flush_rx(void)
65 while (1) {
66 if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
67 break;
69 REG(I2C_DRR);
70 REG(I2C_STAT) = I2C_STAT_RRDY;
71 udelay(1000);
76 void i2c_init(int speed, int slaveadd)
78 u_int32_t div, psc;
80 if (REG(I2C_CON) & I2C_CON_EN) {
81 REG(I2C_CON) = 0;
82 udelay (50000);
85 psc = 2;
86 div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
87 REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
88 REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
89 REG(I2C_SCLH) = div - REG(I2C_SCLL);
91 REG(I2C_OA) = slaveadd;
92 REG(I2C_CNT) = 0;
94 /* Interrupts must be enabled or I2C module won't work */
95 REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
96 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
98 /* Now enable I2C controller (get it out of reset) */
99 REG(I2C_CON) = I2C_CON_EN;
101 udelay(1000);
104 int i2c_set_bus_speed(unsigned int speed)
106 i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
107 return 0;
110 int i2c_probe(u_int8_t chip)
112 int rc = 1;
114 if (chip == REG(I2C_OA)) {
115 return(rc);
118 REG(I2C_CON) = 0;
119 if (wait_for_bus()) {return(1);}
121 /* try to read one byte from current (or only) address */
122 REG(I2C_CNT) = 1;
123 REG(I2C_SA) = chip;
124 REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
125 udelay (50000);
127 if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
128 rc = 0;
129 flush_rx();
130 REG(I2C_STAT) = 0xffff;
131 } else {
132 REG(I2C_STAT) = 0xffff;
133 REG(I2C_CON) |= I2C_CON_STP;
134 udelay(20000);
135 if (wait_for_bus()) {return(1);}
138 flush_rx();
139 REG(I2C_STAT) = 0xffff;
140 REG(I2C_CNT) = 0;
141 return(rc);
145 int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
147 u_int32_t tmp;
148 int i;
150 if ((alen < 0) || (alen > 2)) {
151 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
152 return(1);
155 if (wait_for_bus()) {return(1);}
157 if (alen != 0) {
158 /* Start address phase */
159 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
160 REG(I2C_CNT) = alen;
161 REG(I2C_SA) = chip;
162 REG(I2C_CON) = tmp;
164 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
166 CHECK_NACK();
168 switch (alen) {
169 case 2:
170 /* Send address MSByte */
171 if (tmp & I2C_STAT_XRDY) {
172 REG(I2C_DXR) = (addr >> 8) & 0xff;
173 } else {
174 REG(I2C_CON) = 0;
175 return(1);
178 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
180 CHECK_NACK();
181 /* No break, fall through */
182 case 1:
183 /* Send address LSByte */
184 if (tmp & I2C_STAT_XRDY) {
185 REG(I2C_DXR) = addr & 0xff;
186 } else {
187 REG(I2C_CON) = 0;
188 return(1);
191 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
193 CHECK_NACK();
195 if (!(tmp & I2C_STAT_ARDY)) {
196 REG(I2C_CON) = 0;
197 return(1);
202 /* Address phase is over, now read 'len' bytes and stop */
203 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
204 REG(I2C_CNT) = len & 0xffff;
205 REG(I2C_SA) = chip;
206 REG(I2C_CON) = tmp;
208 for (i = 0; i < len; i++) {
209 tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
211 CHECK_NACK();
213 if (tmp & I2C_STAT_RRDY) {
214 buf[i] = REG(I2C_DRR);
215 } else {
216 REG(I2C_CON) = 0;
217 return(1);
221 tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
223 CHECK_NACK();
225 if (!(tmp & I2C_STAT_SCD)) {
226 REG(I2C_CON) = 0;
227 return(1);
230 flush_rx();
231 REG(I2C_STAT) = 0xffff;
232 REG(I2C_CNT) = 0;
233 REG(I2C_CON) = 0;
235 return(0);
239 int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
241 u_int32_t tmp;
242 int i;
244 if ((alen < 0) || (alen > 2)) {
245 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
246 return(1);
248 if (len < 0) {
249 printf("%s(): bogus length %x\n", __FUNCTION__, len);
250 return(1);
253 if (wait_for_bus()) {return(1);}
255 /* Start address phase */
256 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
257 REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
258 REG(I2C_SA) = chip;
259 REG(I2C_CON) = tmp;
261 switch (alen) {
262 case 2:
263 /* Send address MSByte */
264 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
266 CHECK_NACK();
268 if (tmp & I2C_STAT_XRDY) {
269 REG(I2C_DXR) = (addr >> 8) & 0xff;
270 } else {
271 REG(I2C_CON) = 0;
272 return(1);
274 /* No break, fall through */
275 case 1:
276 /* Send address LSByte */
277 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
279 CHECK_NACK();
281 if (tmp & I2C_STAT_XRDY) {
282 REG(I2C_DXR) = addr & 0xff;
283 } else {
284 REG(I2C_CON) = 0;
285 return(1);
289 for (i = 0; i < len; i++) {
290 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
292 CHECK_NACK();
294 if (tmp & I2C_STAT_XRDY) {
295 REG(I2C_DXR) = buf[i];
296 } else {
297 return(1);
301 tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
303 CHECK_NACK();
305 if (!(tmp & I2C_STAT_SCD)) {
306 REG(I2C_CON) = 0;
307 return(1);
310 flush_rx();
311 REG(I2C_STAT) = 0xffff;
312 REG(I2C_CNT) = 0;
313 REG(I2C_CON) = 0;
315 return(0);