arm: vf610: fix double iomux configuration for vf610twr board
[u-boot/qq2440-u-boot.git] / drivers / i2c / tsi108_i2c.c
blobc0779079ab7eaa45cef16674064f84c8ab08870b
1 /*
2 * (C) Copyright 2004 Tundra Semiconductor Corp.
3 * Author: Alex Bounine
5 * SPDX-License-Identifier: GPL-2.0+
6 */
8 #include <config.h>
9 #include <common.h>
11 #include <tsi108.h>
13 #if defined(CONFIG_CMD_I2C)
15 #define I2C_DELAY 100000
16 #undef DEBUG_I2C
18 #ifdef DEBUG_I2C
19 #define DPRINT(x) printf (x)
20 #else
21 #define DPRINT(x)
22 #endif
24 /* All functions assume that Tsi108 I2C block is the only master on the bus */
25 /* I2C read helper function */
27 void i2c_init(int speed, int slaveaddr)
30 * The TSI108 has a fixed I2C clock rate and doesn't support slave
31 * operation. This function only exists as a stub to fit into the
32 * U-Boot I2C API.
36 static int i2c_read_byte (
37 uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
38 uchar chip_addr,/* I2C device address on the bus */
39 uint byte_addr, /* Byte address within I2C device */
40 uchar * buffer /* pointer to data buffer */
43 u32 temp;
44 u32 to_count = I2C_DELAY;
45 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
46 u32 chan_offset = TSI108_I2C_OFFSET;
48 DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
49 i2c_chan, chip_addr, byte_addr));
51 if (0 != i2c_chan)
52 chan_offset = TSI108_I2C_SDRAM_OFFSET;
54 /* Check if I2C operation is in progress */
55 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
57 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
58 I2C_CNTRL2_START))) {
59 /* Set device address and operation (read = 0) */
60 temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
61 ((chip_addr >> 3) & 0x0F);
62 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
63 temp;
65 /* Issue the read command
66 * (at this moment all other parameters are 0
67 * (size = 1 byte, lane = 0)
70 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
71 (I2C_CNTRL2_START);
73 /* Wait until operation completed */
74 do {
75 /* Read I2C operation status */
76 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
78 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
79 if (0 == (temp &
80 (I2C_CNTRL2_I2C_CFGERR |
81 I2C_CNTRL2_I2C_TO_ERR))
82 ) {
83 op_status = TSI108_I2C_SUCCESS;
85 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
86 chan_offset +
87 I2C_RD_DATA);
89 *buffer = (u8) (temp & 0xFF);
90 } else {
91 /* report HW error */
92 op_status = TSI108_I2C_IF_ERROR;
94 DPRINT (("I2C HW error reported: 0x%02x\n", temp));
97 break;
99 } while (to_count--);
100 } else {
101 op_status = TSI108_I2C_IF_BUSY;
103 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
106 DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
107 return op_status;
111 * I2C Read interface as defined in "include/i2c.h" :
112 * chip_addr: I2C chip address, range 0..127
113 * (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
114 * NOTE: The bit 7 in the chip_addr serves as a channel select.
115 * This hack is for enabling "i2c sdram" command on Tsi108 boards
116 * without changes to common code. Used for I2C reads only.
117 * byte_addr: Memory or register address within the chip
118 * alen: Number of bytes to use for addr (typically 1, 2 for larger
119 * memories, 0 for register type devices with only one
120 * register)
121 * buffer: Pointer to destination buffer for data to be read
122 * len: How many bytes to read
124 * Returns: 0 on success, not 0 on failure
127 int i2c_read (uchar chip_addr, uint byte_addr, int alen,
128 uchar * buffer, int len)
130 u32 op_status = TSI108_I2C_PARAM_ERR;
131 u32 i2c_if = 0;
133 /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
134 if (0xD0 == (chip_addr & ~0x07)) {
135 i2c_if = 1;
136 chip_addr &= 0x7F;
138 /* Check for valid I2C address */
139 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
140 while (len--) {
141 op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
143 if (TSI108_I2C_SUCCESS != op_status) {
144 DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
146 break;
151 DPRINT (("I2C read() status: 0x%02x\n", op_status));
152 return op_status;
155 /* I2C write helper function */
157 static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
158 uint byte_addr, /* Byte address within I2C device */
159 uchar * buffer /* pointer to data buffer */
162 u32 temp;
163 u32 to_count = I2C_DELAY;
164 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
166 /* Check if I2C operation is in progress */
167 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
169 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
170 /* Place data into the I2C Tx Register */
171 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
172 I2C_TX_DATA) = (u32) * buffer;
174 /* Set device address and operation */
175 temp =
176 I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
177 ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
178 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
179 I2C_CNTRL1) = temp;
181 /* Issue the write command (at this moment all other parameters
182 * are 0 (size = 1 byte, lane = 0)
185 *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
186 I2C_CNTRL2) = (I2C_CNTRL2_START);
188 op_status = TSI108_I2C_TIMEOUT_ERR;
190 /* Wait until operation completed */
191 do {
192 /* Read I2C operation status */
193 temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
195 if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
196 if (0 == (temp &
197 (I2C_CNTRL2_I2C_CFGERR |
198 I2C_CNTRL2_I2C_TO_ERR))) {
199 op_status = TSI108_I2C_SUCCESS;
200 } else {
201 /* report detected HW error */
202 op_status = TSI108_I2C_IF_ERROR;
204 DPRINT (("I2C HW error reported: 0x%02x\n", temp));
207 break;
210 } while (to_count--);
211 } else {
212 op_status = TSI108_I2C_IF_BUSY;
214 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
217 return op_status;
221 * I2C Write interface as defined in "include/i2c.h" :
222 * chip_addr: I2C chip address, range 0..127
223 * byte_addr: Memory or register address within the chip
224 * alen: Number of bytes to use for addr (typically 1, 2 for larger
225 * memories, 0 for register type devices with only one
226 * register)
227 * buffer: Pointer to data to be written
228 * len: How many bytes to write
230 * Returns: 0 on success, not 0 on failure
233 int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
234 int len)
236 u32 op_status = TSI108_I2C_PARAM_ERR;
238 /* Check for valid I2C address */
239 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
240 while (len--) {
241 op_status =
242 i2c_write_byte (chip_addr, byte_addr++, buffer++);
244 if (TSI108_I2C_SUCCESS != op_status) {
245 DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
247 break;
252 return op_status;
256 * I2C interface function as defined in "include/i2c.h".
257 * Probe the given I2C chip address by reading single byte from offset 0.
258 * Returns 0 if a chip responded, not 0 on failure.
261 int i2c_probe (uchar chip)
263 u32 tmp;
266 * Try to read the first location of the chip.
267 * The Tsi108 HW doesn't support sending just the chip address
268 * and checkong for an <ACK> back.
270 return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
273 #endif