drivers/spi/ftssp010_spi.c

   1 /*
   2  * (C) Copyright 2013
   3  * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
   4  * Kuo-Jung Su <dantesu@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/compat.h>
  11 #include <asm/io.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14
  15 #ifndef CONFIG_FTSSP010_BASE_LIST
  16 #define CONFIG_FTSSP010_BASE_LIST   { CONFIG_FTSSP010_BASE }
  17 #endif
  18
  19 #ifndef CONFIG_FTSSP010_GPIO_BASE
  20 #define CONFIG_FTSSP010_GPIO_BASE   0
  21 #endif
  22
  23 #ifndef CONFIG_FTSSP010_GPIO_LIST
  24 #define CONFIG_FTSSP010_GPIO_LIST   { CONFIG_FTSSP010_GPIO_BASE }
  25 #endif
  26
  27 #ifndef CONFIG_FTSSP010_CLOCK
  28 #define CONFIG_FTSSP010_CLOCK       clk_get_rate("SSP");
  29 #endif
  30
  31 #ifndef CONFIG_FTSSP010_TIMEOUT
  32 #define CONFIG_FTSSP010_TIMEOUT     100
  33 #endif
  34
  35 /* FTSSP010 chip registers */
  36 struct ftssp010_regs {
  37         uint32_t cr[3];/* control register */
  38         uint32_t sr;   /* status register */
  39         uint32_t icr;  /* interrupt control register */
  40         uint32_t isr;  /* interrupt status register */
  41         uint32_t dr;   /* data register */
  42         uint32_t rsvd[17];
  43         uint32_t revr; /* revision register */
  44         uint32_t fear; /* feature register */
  45 };
  46
  47 /* Control Register 0  */
  48 #define CR0_FFMT_MASK       (7 << 12)
  49 #define CR0_FFMT_SSP        (0 << 12)
  50 #define CR0_FFMT_SPI        (1 << 12)
  51 #define CR0_FFMT_MICROWIRE  (2 << 12)
  52 #define CR0_FFMT_I2S        (3 << 12)
  53 #define CR0_FFMT_AC97       (4 << 12)
  54 #define CR0_FLASH           (1 << 11)
  55 #define CR0_FSDIST(x)       (((x) & 0x03) << 8)
  56 #define CR0_LOOP            (1 << 7)  /* loopback mode */
  57 #define CR0_LSB             (1 << 6)  /* LSB */
  58 #define CR0_FSPO            (1 << 5)  /* fs atcive low (I2S only) */
  59 #define CR0_FSJUSTIFY       (1 << 4)
  60 #define CR0_OPM_SLAVE       (0 << 2)
  61 #define CR0_OPM_MASTER      (3 << 2)
  62 #define CR0_OPM_I2S_MSST    (3 << 2)  /* master stereo mode */
  63 #define CR0_OPM_I2S_MSMO    (2 << 2)  /* master mono mode */
  64 #define CR0_OPM_I2S_SLST    (1 << 2)  /* slave stereo mode */
  65 #define CR0_OPM_I2S_SLMO    (0 << 2)  /* slave mono mode */
  66 #define CR0_SCLKPO          (1 << 1)  /* clock polarity */
  67 #define CR0_SCLKPH          (1 << 0)  /* clock phase */
  68
  69 /* Control Register 1 */
  70 #define CR1_PDL(x)   (((x) & 0xff) << 24) /* padding length */
  71 #define CR1_SDL(x)   ((((x) - 1) & 0x1f) << 16) /* data length */
  72 #define CR1_DIV(x)   (((x) - 1) & 0xffff) /* clock divider */
  73
  74 /* Control Register 2 */
  75 #define CR2_CS(x)    (((x) & 3) << 10) /* CS/FS select */
  76 #define CR2_FS       (1 << 9) /* CS/FS signal level */
  77 #define CR2_TXEN     (1 << 8) /* tx enable */
  78 #define CR2_RXEN     (1 << 7) /* rx enable */
  79 #define CR2_RESET    (1 << 6) /* chip reset */
  80 #define CR2_TXFC     (1 << 3) /* tx fifo Clear */
  81 #define CR2_RXFC     (1 << 2) /* rx fifo Clear */
  82 #define CR2_TXDOE    (1 << 1) /* tx data output enable */
  83 #define CR2_EN       (1 << 0) /* chip enable */
  84
  85 /* Status Register */
  86 #define SR_RFF       (1 << 0) /* rx fifo full */
  87 #define SR_TFNF      (1 << 1) /* tx fifo not full */
  88 #define SR_BUSY      (1 << 2) /* chip busy */
  89 #define SR_RFVE(reg) (((reg) >> 4) & 0x1f)  /* rx fifo valid entries */
  90 #define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
  91
  92 /* Feature Register */
  93 #define FEAR_BITS(reg)   ((((reg) >>  0) & 0xff) + 1) /* data width */
  94 #define FEAR_RFSZ(reg)   ((((reg) >>  8) & 0xff) + 1) /* rx fifo size */
  95 #define FEAR_TFSZ(reg)   ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
  96 #define FEAR_AC97        (1 << 24)
  97 #define FEAR_I2S         (1 << 25)
  98 #define FEAR_SPI_MWR     (1 << 26)
  99 #define FEAR_SSP         (1 << 27)
 100 #define FEAR_SPDIF       (1 << 28)
 101
 102 /* FTGPIO010 chip registers */
 103 struct ftgpio010_regs {
 104         uint32_t out;     /* 0x00: Data Output */
 105         uint32_t in;      /* 0x04: Data Input */
 106         uint32_t dir;     /* 0x08: Direction */
 107         uint32_t bypass;  /* 0x0c: Bypass */
 108         uint32_t set;     /* 0x10: Data Set */
 109         uint32_t clr;     /* 0x14: Data Clear */
 110         uint32_t pull_up; /* 0x18: Pull-Up Enabled */
 111         uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
 112 };
 113
 114 struct ftssp010_gpio {
 115         struct ftgpio010_regs *regs;
 116         uint32_t pin;
 117 };
 118
 119 struct ftssp010_spi {
 120         struct spi_slave slave;
 121         struct ftssp010_gpio gpio;
 122         struct ftssp010_regs *regs;
 123         uint32_t fifo;
 124         uint32_t mode;
 125         uint32_t div;
 126         uint32_t clk;
 127         uint32_t speed;
 128         uint32_t revision;
 129 };
 130
 131 static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave)
 132 {
 133         return container_of(slave, struct ftssp010_spi, slave);
 134 }
 135
 136 static int get_spi_chip(int bus, struct ftssp010_spi *chip)
 137 {
 138         uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
 139
 140         if (bus >= ARRAY_SIZE(base) || !base[bus])
 141                 return -1;
 142
 143         chip->regs = (struct ftssp010_regs *)base[bus];
 144
 145         chip->revision = readl(&chip->regs->revr);
 146
 147         fear = readl(&chip->regs->fear);
 148         chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
 149
 150         return 0;
 151 }
 152
 153 static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
 154 {
 155         uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
 156
 157         if (bus >= ARRAY_SIZE(base) || !base[bus])
 158                 return -1;
 159
 160         chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
 161         chip->pin = base[bus] & 0x1f;
 162
 163         /* make it an output pin */
 164         setbits_le32(&chip->regs->dir, 1 << chip->pin);
 165
 166         return 0;
 167 }
 168
 169 static int ftssp010_wait(struct ftssp010_spi *chip)
 170 {
 171         struct ftssp010_regs *regs = chip->regs;
 172         int ret = -1;
 173         ulong t;
 174
 175         /* wait until device idle */
 176         for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
 177                 if (readl(&regs->sr) & SR_BUSY)
 178                         continue;
 179                 ret = 0;
 180                 break;
 181         }
 182
 183         if (ret)
 184                 puts("ftspi010: busy timeout\n");
 185
 186         return ret;
 187 }
 188
 189 static int ftssp010_wait_tx(struct ftssp010_spi *chip)
 190 {
 191         struct ftssp010_regs *regs = chip->regs;
 192         int ret = -1;
 193         ulong t;
 194
 195         /* wait until tx fifo not full */
 196         for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
 197                 if (!(readl(&regs->sr) & SR_TFNF))
 198                         continue;
 199                 ret = 0;
 200                 break;
 201         }
 202
 203         if (ret)
 204                 puts("ftssp010: tx timeout\n");
 205
 206         return ret;
 207 }
 208
 209 static int ftssp010_wait_rx(struct ftssp010_spi *chip)
 210 {
 211         struct ftssp010_regs *regs = chip->regs;
 212         int ret = -1;
 213         ulong t;
 214
 215         /* wait until rx fifo not empty */
 216         for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
 217                 if (!SR_RFVE(readl(&regs->sr)))
 218                         continue;
 219                 ret = 0;
 220                 break;
 221         }
 222
 223         if (ret)
 224                 puts("ftssp010: rx timeout\n");
 225
 226         return ret;
 227 }
 228
 229 static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
 230         const void *tx_buf, void *rx_buf, int len, uint flags)
 231 {
 232         struct ftssp010_regs *regs = chip->regs;
 233         const uint8_t *txb = tx_buf;
 234         uint8_t       *rxb = rx_buf;
 235
 236         while (len > 0) {
 237                 int i, depth = min(chip->fifo >> 2, len);
 238                 uint32_t xmsk = 0;
 239
 240                 if (tx_buf) {
 241                         for (i = 0; i < depth; ++i) {
 242                                 ftssp010_wait_tx(chip);
 243                                 writel(*txb++, &regs->dr);
 244                         }
 245                         xmsk |= CR2_TXEN | CR2_TXDOE;
 246                         if ((readl(&regs->cr[2]) & xmsk) != xmsk)
 247                                 setbits_le32(&regs->cr[2], xmsk);
 248                 }
 249                 if (rx_buf) {
 250                         xmsk |= CR2_RXEN;
 251                         if ((readl(&regs->cr[2]) & xmsk) != xmsk)
 252                                 setbits_le32(&regs->cr[2], xmsk);
 253                         for (i = 0; i < depth; ++i) {
 254                                 ftssp010_wait_rx(chip);
 255                                 *rxb++ = (uint8_t)readl(&regs->dr);
 256                         }
 257                 }
 258
 259                 len -= depth;
 260         }
 261
 262         return 0;
 263 }
 264
 265 static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
 266         const void *tx_buf, void *rx_buf, int len, uint flags)
 267 {
 268         struct ftssp010_regs *regs = chip->regs;
 269         const uint8_t *txb = tx_buf;
 270         uint8_t       *rxb = rx_buf;
 271
 272         while (len > 0) {
 273                 int i, depth = min(chip->fifo >> 2, len);
 274                 uint32_t tmp;
 275
 276                 for (i = 0; i < depth; ++i) {
 277                         ftssp010_wait_tx(chip);
 278                         writel(txb ? (*txb++) : 0, &regs->dr);
 279                 }
 280                 for (i = 0; i < depth; ++i) {
 281                         ftssp010_wait_rx(chip);
 282                         tmp = readl(&regs->dr);
 283                         if (rxb)
 284                                 *rxb++ = (uint8_t)tmp;
 285                 }
 286
 287                 len -= depth;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
 294 {
 295         struct ftssp010_regs *regs = chip->regs;
 296         struct ftssp010_gpio *gpio = &chip->gpio;
 297         uint32_t mask;
 298
 299         /* cs pull high/low */
 300         if (chip->revision >= 0x11900) {
 301                 mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0);
 302                 writel(mask, &regs->cr[2]);
 303         } else if (gpio->regs) {
 304                 mask = 1 << gpio->pin;
 305                 if (high)
 306                         writel(mask, &gpio->regs->set);
 307                 else
 308                         writel(mask, &gpio->regs->clr);
 309         }
 310
 311         /* extra delay for signal propagation */
 312         udelay_masked(1);
 313 }
 314
 315 /*
 316  * Determine if a SPI chipselect is valid.
 317  * This function is provided by the board if the low-level SPI driver
 318  * needs it to determine if a given chipselect is actually valid.
 319  *
 320  * Returns: 1 if bus:cs identifies a valid chip on this board, 0
 321  * otherwise.
 322  */
 323 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 324 {
 325         struct ftssp010_spi chip;
 326
 327         if (get_spi_chip(bus, &chip))
 328                 return 0;
 329
 330         if (!cs)
 331                 return 1;
 332         else if ((cs < 4) && (chip.revision >= 0x11900))
 333                 return 1;
 334
 335         return 0;
 336 }
 337
 338 /*
 339  * Activate a SPI chipselect.
 340  * This function is provided by the board code when using a driver
 341  * that can't control its chipselects automatically (e.g.
 342  * common/soft_spi.c). When called, it should activate the chip select
 343  * to the device identified by "slave".
 344  */
 345 void spi_cs_activate(struct spi_slave *slave)
 346 {
 347         struct ftssp010_spi *chip = to_ftssp010_spi(slave);
 348         struct ftssp010_regs *regs = chip->regs;
 349
 350         /* cs pull */
 351         if (chip->mode & SPI_CS_HIGH)
 352                 ftssp010_cs_set(chip, 1);
 353         else
 354                 ftssp010_cs_set(chip, 0);
 355
 356         /* chip enable + fifo clear */
 357         setbits_le32(&regs->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC);
 358 }
 359
 360 /*
 361  * Deactivate a SPI chipselect.
 362  * This function is provided by the board code when using a driver
 363  * that can't control its chipselects automatically (e.g.
 364  * common/soft_spi.c). When called, it should deactivate the chip
 365  * select to the device identified by "slave".
 366  */
 367 void spi_cs_deactivate(struct spi_slave *slave)
 368 {
 369         struct ftssp010_spi *chip = to_ftssp010_spi(slave);
 370
 371         /* wait until chip idle */
 372         ftssp010_wait(chip);
 373
 374         /* cs pull */
 375         if (chip->mode & SPI_CS_HIGH)
 376                 ftssp010_cs_set(chip, 0);
 377         else
 378                 ftssp010_cs_set(chip, 1);
 379 }
 380
 381 void spi_init(void)
 382 {
 383         /* nothing to do */
 384 }
 385
 386 struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
 387 {
 388         struct ftssp010_spi *chip;
 389
 390         if (mode & SPI_3WIRE) {
 391                 puts("ftssp010: can't do 3-wire\n");
 392                 return NULL;
 393         }
 394
 395         if (mode & SPI_SLAVE) {
 396                 puts("ftssp010: can't do slave mode\n");
 397                 return NULL;
 398         }
 399
 400         if (mode & SPI_PREAMBLE) {
 401                 puts("ftssp010: can't skip preamble bytes\n");
 402                 return NULL;
 403         }
 404
 405         if (!spi_cs_is_valid(bus, cs)) {
 406                 puts("ftssp010: invalid (bus, cs)\n");
 407                 return NULL;
 408         }
 409
 410         chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
 411         if (!chip)
 412                 return NULL;
 413
 414         if (get_spi_chip(bus, chip))
 415                 goto free_out;
 416
 417         if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
 418                 puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
 419                 "controlled by tx engine which is not synced with rx engine,\n"
 420                 "so the clock & cs might be shutdown before rx engine\n"
 421                 "finishs its jobs.\n"
 422                 "If possible, please add a dedicated gpio for it.\n");
 423         }
 424
 425         chip->mode = mode;
 426         chip->clk = CONFIG_FTSSP010_CLOCK;
 427         chip->div = 2;
 428         if (max_hz) {
 429                 while (chip->div < 0xffff) {
 430                         if ((chip->clk / (2 * chip->div)) <= max_hz)
 431                                 break;
 432                         chip->div += 1;
 433                 }
 434         }
 435         chip->speed = chip->clk / (2 * chip->div);
 436
 437         return &chip->slave;
 438
 439 free_out:
 440         free(chip);
 441         return NULL;
 442 }
 443
 444 void spi_free_slave(struct spi_slave *slave)
 445 {
 446         free(slave);
 447 }
 448
 449 int spi_claim_bus(struct spi_slave *slave)
 450 {
 451         struct ftssp010_spi *chip = to_ftssp010_spi(slave);
 452         struct ftssp010_regs *regs = chip->regs;
 453
 454         writel(CR1_SDL(8) | CR1_DIV(chip->div), &regs->cr[1]);
 455
 456         if (chip->revision >= 0x11900) {
 457                 writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
 458                        &regs->cr[0]);
 459                 writel(CR2_TXFC | CR2_RXFC,
 460                        &regs->cr[2]);
 461         } else {
 462                 writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
 463                        &regs->cr[0]);
 464                 writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE,
 465                        &regs->cr[2]);
 466         }
 467
 468         if (chip->mode & SPI_LOOP)
 469                 setbits_le32(&regs->cr[0], CR0_LOOP);
 470
 471         if (chip->mode & SPI_CPOL)
 472                 setbits_le32(&regs->cr[0], CR0_SCLKPO);
 473
 474         if (chip->mode & SPI_CPHA)
 475                 setbits_le32(&regs->cr[0], CR0_SCLKPH);
 476
 477         spi_cs_deactivate(slave);
 478
 479         return 0;
 480 }
 481
 482 void spi_release_bus(struct spi_slave *slave)
 483 {
 484         struct ftssp010_spi *chip = to_ftssp010_spi(slave);
 485         struct ftssp010_regs *regs = chip->regs;
 486
 487         writel(0, &regs->cr[2]);
 488 }
 489
 490 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 491                          const void *dout, void *din, unsigned long flags)
 492 {
 493         struct ftssp010_spi *chip = to_ftssp010_spi(slave);
 494         uint32_t len = bitlen >> 3;
 495
 496         if (flags & SPI_XFER_BEGIN)
 497                 spi_cs_activate(slave);
 498
 499         if (chip->revision >= 0x11900)
 500                 ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
 501         else
 502                 ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
 503
 504         if (flags & SPI_XFER_END)
 505                 spi_cs_deactivate(slave);
 506
 507         return 0;
 508 }